a87ed5c9e8
Rev A5: fixup silkscreen
2025-09-01 22:20:24 +12:00
66a3f033db
Document Jumpers
...
As suggested in #2
2025-07-28 11:40:00 +12:00
9d8a8014e8
Rev A4
2025-02-02 17:13:38 +13:00
576a2a3b4e
BOM: Fixup alternatives for Flash
2024-11-19 22:46:13 +13:00
1965b4e11e
Update release workflow
2024-11-19 19:27:28 +13:00
fef1bcf04a
BOM: List alternative part numbers for Flash
2024-11-19 19:26:20 +13:00
12c777c94e
Update README
2024-11-17 16:46:12 +13:00
c1046351c5
Generate HTML BOM with Mouser part links
2024-09-27 13:15:46 +12:00
adda8d80b0
Fixup part number for D3 and sync schematic & pcb
2024-09-13 12:08:12 +12:00
0eac165e3f
Remove RAM.kicad_sch - this was inadvertantly copied from the CIDER project
2024-09-13 11:55:07 +12:00
32f0f0c3cf
Move protection diode away from resistor to make it easier to replace
2024-09-13 11:53:58 +12:00
816a0f6340
Tweak more footprints to make hand assembly easier
2024-08-28 21:08:41 +12:00
0735f59ba7
Switch to hand-solder footprints for passives
2024-08-28 16:20:36 +12:00
25a272fa1e
Add protection for reverse installation of the board
2024-08-28 16:20:36 +12:00
923cdd0bb3
README: fix typo
2024-08-28 16:14:21 +12:00
bd55aac7c4
Update BOM
...
* Change LED part number
* Fix Polyfuse link
2024-08-28 12:39:53 +12:00
6dd181056c
README: fixup C1,C12 part link (thanks @RetroFletch !)
2024-05-08 21:12:18 +12:00
f068d24f47
Update README
2024-05-08 21:09:50 +12:00
1551249b90
RTL: Fix bug in ROM Bank select
...
At reset the rom bank select was set to follow addr[16:15] until IDE was activated by a write to any IDE reg.
After that it reflects the value of the rom_bankSel register
On a new board with no driver yet in flash this switch would not be triggered, causing the driver to be written to the wrong bank of flash.
Now the switch will flip on any write to the boards range, the flash identification step will trigger this.
2024-04-18 16:25:16 +12:00
7e949f9765
Add option to build for 64K board size
2024-03-02 15:59:49 +13:00
9def334bef
Autoconfig: Don't hardcode upper address bits
...
Kickstart may place the board in the Z2 Memory region if IO area is full.
2024-03-02 15:40:02 +13:00
462a16b953
Update README with links to Release
2024-01-15 09:52:23 +13:00
11ebac607e
Fixup flash rotation in pick and place file
2024-01-15 09:46:33 +13:00
3c19789e4a
Resize RIPPLE.jpg
2024-01-15 08:26:48 +13:00
33704a8391
Update README
...
Note 2TB drive and CD Boot support
2024-01-15 08:25:43 +13:00
33ca76889e
Add photo of Rev A
2024-01-15 08:21:39 +13:00
33b134d813
Add Bill-of-Materials and shoutouts to README
2023-11-18 20:40:39 +00:00
ec1083faf4
RTL: Only use bank select register after ide enabled
...
Before then the ROM bank select is connected to A16 to allow loading modules by the bootloader
2023-11-18 19:51:34 +00:00
5e1237c056
Revert timing changes
2023-11-18 19:49:38 +00:00
b8b0178772
Change R17 from 330 to 1K (IDE LED was insanley bright)
2023-10-22 17:03:44 +02:00
d92e60953c
Fixup pin mapping
2023-10-20 19:06:34 +00:00
b31d9414c2
Change IDECS decode, tweak timing
...
* Don't latch AS_n on falling edge, setup time not guaranteed
* IOW now active from S4
* On Reads, open IDE buffers as soon as UDS/LDS asserted
2023-10-20 19:06:00 +00:00
1f9973fba7
Expose second Bank select pin from CPLD
2023-10-13 11:44:31 +00:00
4ca94ddd3d
Route second bank select
2023-10-13 12:57:01 +02:00
7eb51c0ce6
Add flash bank select
2023-10-11 11:02:29 +00:00
36c812807a
RTL: Add Proto-A2 Extra IDE Chip selects and update UCF
2023-10-11 10:16:39 +00:00
c99f8d6eb1
Route bank select pin to ROM
2023-10-08 16:05:52 +02:00
50fadde109
Fixup LED circuit
2023-10-07 17:04:51 +02:00
1ab028f067
Tweaks after testing feedback
...
* Check RESET length before asserting, seems noise is causing cold-boot issues on BUSRST
* Enable Buffers for reads during S4 regardless of DS'es
* Fixups for Autoconfig
* IDE: don't assert IOW/IOW until S3 to meet address set-up times
2023-09-25 18:55:14 +00:00
ee9068b231
Add CS1 to both IDE channels
2023-09-25 20:45:57 +02:00
dc50974a5e
Rev A1: changes
...
* Dump BUSRST and use regular reset
* Ditch the worthless ferrites
* Add the gadget header
* Add A2000/4000 LED Header
2023-09-20 23:32:05 +02:00
ebacb93b37
Fixups
...
IDE Enable logic wasn't working in A4000/060
2023-09-03 20:20:10 +00:00
819a9eccb6
Proto A1
...
* Fix LED pinout
* Reduce LED resistor to 150 Ohm
* Separate Primary/Secondary channel Activity signals
2023-08-21 22:54:13 +02:00
36e76d08ef
Fixup some issues
...
* Qualify SLAVE_n with AS_n or it will trigger during Z3 cycles
* Don't register CFGIN at AS_n posedge - Z3 cards would prevent this from working
* Disable DTACK/OVR gen as it's not needed
2023-08-20 07:42:59 +00:00
6eb2d8a3fa
Update README
2023-08-14 10:50:35 +00:00
4cd67c076a
Fixup everything and make it actually work
2023-08-14 07:39:20 +00:00
6a7b69fcce
Update CPLD Pin mapping and tweak a few things
2023-07-24 20:24:46 +00:00
a01a926003
Add License.md
2023-07-24 16:58:11 +02:00
279bfcb175
Release Rev_A
2023-07-24 16:56:39 +02:00
101214b9b1
Move Disable jumper
...
Also route the signal through a buffer to protect the CPLD
2023-07-16 17:23:13 +02:00
