LIV2/RIPPLE-IDE
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Revert timing changes

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This commit is contained in:
Matt Harlum 2023-11-18 19:38:38 +00:00
parent b8b0178772
commit 5e1237c056
3 changed files with 726 additions and 717 deletions
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1418
Binary/RIPPLE.jed
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23
RTL/IDE.v
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@ -43,6 +43,7 @@ reg ide_enabled = 0;
reg bank_sel = 0;
reg [1:0] as_delay; // AS_n shifted by CLK
reg S3_n; // S3 has started
assign AS_n_S4 = as_delay[0];
@ -52,8 +53,8 @@ always @(posedge CLK or negedge RESET_n) begin
ROM_BANK <= 0;
end else begin
// IDE enabled on first write to an IDE address
if (ide_access && ADDR[16:15] == 2'b00 && !RW && !UDS_n && !as_delay[0]) ide_enabled <= 1;
if (ide_access && ADDR[16:15] == 2'b01 && !RW && !UDS_n && !as_delay[0]) ROM_BANK <= DIN;
if (ide_access && ADDR[16:15] == 2'b00 && !RW && !UDS_n && !S3_n) ide_enabled <= 1;
if (ide_access && ADDR[16:15] == 2'b01 && !RW && !UDS_n && !S3_n) ROM_BANK <= DIN;
end
end
@ -69,6 +70,14 @@ assign IDE2_CS_n[1] = !( ADDR[14] && CS_1);
// After then, it is mapped to (base address) + 64K
assign IDE_ROMEN = !(!AS_n && ide_access && (!ide_enabled || !(ADDR[12] ^ ADDR[13]) || ADDR[16]));
always @(negedge CLK or negedge RESET_n) begin
if (!RESET_n) begin
S3_n <= 1;
end else begin
S3_n <= AS_n;
end
end
always @(posedge CLK or negedge RESET_n) begin
if (!RESET_n) begin
as_delay <= 2'b11;
@ -76,14 +85,14 @@ always @(posedge CLK or negedge RESET_n) begin
if (AS_n) begin
as_delay[1:0] <= 2'b11;
end else begin
as_delay <= {as_delay[0], AS_n};
as_delay <= {as_delay[0], S3_n};
end
end
end
// IOR Active during states S4-S6
// IOW Active during states S4-S5
assign IOR_n = !(!AS_n && RW && !as_delay[0]);
assign IOW_n = !(!AS_n && !RW && !as_delay[0] && as_delay[1]);
// IOR Active during states S3-S6
// IOW Active during states S3-S5
assign IOR_n = !(!AS_n && RW && !S3_n);
assign IOW_n = !(!AS_n && !RW && !S3_n && as_delay[1]);
endmodule

2
RTL/top.v
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@ -110,6 +110,6 @@ assign OVR_n_2 = 1'bZ;
assign SLAVE_n = !((autoconfig_cycle || ide_access) && !AS_n);
assign IDEBUF_OE = !(!RW || ((autoconfig_cycle || ide_access) && !AS_n && (!UDS_n || !LDS_n) && BERR_n && RESET_n));
assign IDEBUF_OE = !(!RW || ((autoconfig_cycle || ide_access) && !AS_n && !AS_n_S4 && BERR_n && RESET_n));
endmodule