c8b767916e
Fixup address decodes
...
*_region was matching when slave_cycle was true but without checking that the base address matched - this would cause these regions to match when other Z3 boards are being accessed
2025-07-13 22:16:12 +12:00
bd5990cd71
Fixup DOE
...
It must be an inout not an output
Also add a synchronizer for DOE and DS
2025-07-13 22:16:12 +12:00
Stefan Reinauer
418ef069ee
Clean up rom_access.v
2025-07-13 00:20:30 -07:00
Stefan Reinauer
24669ba584
Add xise file
2025-07-11 20:53:25 -07:00
Stefan Reinauer
38c0d42e97
Zorro protocol
2025-07-11 20:51:55 -07:00
Stefan Reinauer
092b4fbe00
No need for DTACK, handled by buffer_control.v
2025-07-11 20:34:21 -07:00
Stefan Reinauer
78978a9f81
Simplify address bus logic
...
We have 2 74ABT16543 to buffer our bus access. So we
can drop logic around doing the same in the CPLD. (Dorken)
2025-07-11 20:14:53 -07:00
Stefan Reinauer
fa917aa47c
Autoconfig update part 2
2025-07-11 20:11:41 -07:00
Stefan Reinauer
f902f963d9
FCS is high active and Z_FCS_n is low active
...
Found by Dorken
2025-07-11 20:08:26 -07:00
Stefan Reinauer
2b05ad6e75
Autoconfig update from Dorken
...
- We need 8 bits for the BAR portion of the address as our address
space is only 16MB, not 256.
- The A4092 is using 16543 for multiplexing the data and address bus,
so we can assume that A[] and D[] are valid when we read them, no
need to look at z3_state.
- Disable Automatic sizing by the OS, this only works with memory cards
- Disable Autoboot for now, until we have all components of the card
actually up and running
2025-07-11 19:33:43 -07:00
Stefan Reinauer
718776d7f0
intreg: NCR_INT is low active,
2025-07-11 18:57:29 -07:00
Stefan Reinauer
9726dcb0e3
MASTER_n is an input in our design
2025-07-03 10:56:19 -07:00
Stefan Reinauer
87c917c7ff
Fix signal names for scsi slave interface
2025-07-02 12:58:45 -07:00
Stefan Reinauer
eee9972f1c
factor out scsi slave module
...
- stub out spi module
- top: A[] is now inout
- top: CLK and MASTER_n are wires
- top: SIZ is an output to the SCSI chip
- straighten zorro arbiter
2025-07-01 23:51:52 -07:00
Stefan Reinauer
d243623362
Clean up sid access
2025-07-01 20:10:49 -07:00
Stefan Reinauer
9dfc5e04bb
INT2_n is shared so it should be 0 or Z
2025-07-01 18:55:58 -07:00
Stefan Reinauer
71b4b70f16
Define MTACK_n and CBACK_n
2025-07-01 18:55:18 -07:00
Stefan Reinauer
7cc5bb32a5
Fix RCHNG in zorro arbiter
...
and add dummy spi module
2025-07-01 13:42:30 -07:00
Stefan Reinauer
824c17327e
Move memory map handling into top.v
...
- Rename Z_7M to C7M
- Rename MYBBUS to MYBUS_n as it is active low
- Don't pass ADDR[] into modules if not needed
(intreg still missing)
- Fix SBG_n in zorro arbiter
2025-07-01 12:43:11 -07:00
Stefan Reinauer
75a9444fe7
buffer_control: Plumb through all buffer enables
...
When an input pin on a BiCMOS logic chip like the SN74ABT543 is left floating
(unconnected), its voltage can drift into an indeterminate state, somewhere
between a valid logic HIGH and a valid logic LOW.
In this intermediate state, both the internal pull-up and pull-down transistors
inside the chip's input buffer can turn on simultaneously. This creates a
low-impedance path directly from the power supply (Vcc) to ground (GND). This
condition is known as shoot-through current, and it causes the chip to draw
excessive power, which is dissipated as heat. This can make the chip get hot
very quickly and can permanently damage it.
2025-06-30 16:47:10 -07:00
Stefan Reinauer
ca54af6007
Move regions to top level
2025-06-29 22:52:32 -07:00
Stefan Reinauer
88725f507f
buffer control was way off
2025-06-28 23:40:52 -07:00
Stefan Reinauer
be5aaffd74
RTL: Address matching for intreg
...
Make address matching for intreg the same as for everything else,
using bits 23-17
2025-06-08 16:17:52 -07:00
Stefan Reinauer
293179aec8
Fix address mapping
2025-06-07 23:36:44 -07:00
Stefan Reinauer
758385b5f3
RTL: Fix signal naming and hook up right bits of DIP
2025-06-07 11:29:29 -07:00
Stefan Reinauer
67f86c9a51
RTL: Drop double assignment of DOE and DS_n
2025-06-07 11:03:33 -07:00
Stefan Reinauer
90f0ecdb1f
Update scsi_access
2025-06-06 23:11:29 -07:00
Stefan Reinauer
7c9bc343cc
Fix Data Bus output
2025-06-05 00:06:45 -07:00
Stefan Reinauer
b6c1ccfd10
Update RTL
2025-06-01 12:38:16 -07:00
Stefan Reinauer
1a213776c6
RTL: Add additional address, data and spi signals
2025-05-30 08:28:22 -07:00
Stefan Reinauer
ae39aab253
RTL: Add additional data and address lines
...
and fix address map
2025-05-30 08:25:34 -07:00
Stefan Reinauer
b5c61a47d2
Add Zorro 3 DMA master
2025-05-28 11:47:16 -07:00
Stefan Reinauer
8a552d0dfb
Add option to move SID into CPLD / flash entirely
2025-05-18 16:18:34 -07:00
Stefan Reinauer
b5d984aef8
Drop PRODID from Makefile
...
It is not used in the code
2025-05-18 10:12:58 -07:00
Stefan Reinauer
2e358d3e1a
Zorro Master Arbiter needs Z_FCS
2025-05-12 07:52:54 -07:00
Stefan Reinauer
726a9127b0
Use Z_LOCK/A1 for intreg
2025-05-12 07:44:38 -07:00
Stefan Reinauer
7965d14fad
Try to fix up pin naming
2025-05-11 23:19:30 -07:00
Stefan Reinauer
07b96fa1a4
More compile fixes.
2025-05-11 16:29:36 -07:00
Stefan Reinauer
5f670d4c0e
Some compilation fixes
2025-05-11 01:14:14 -07:00
Stefan Reinauer
5fb5f5c25a
Fix pin mapping
2025-05-07 22:42:59 +08:00
Stefan Reinauer
dd5269e515
Add clocks, replace 74F74
2025-05-07 13:37:46 +08:00
Stefan Reinauer
89ce4b67ed
Zorro Master Arbiter
2025-05-07 13:34:38 +08:00
Stefan Reinauer
c2f34466f4
Add more remaining signals
2025-05-07 12:22:23 +08:00
Stefan Reinauer
0c1b5945bf
Add INT2 handling
2025-05-07 10:54:10 +08:00
Stefan Reinauer
9584898714
RTL: Add DBLT
2025-05-07 00:04:05 +08:00
Stefan Reinauer
0f8fdc2de6
add actual scsi access and buffer control
2025-05-07 00:00:09 +08:00
Stefan Reinauer
ab2dea27fd
RTL: Drive MTCR_n, CBACK_n, and STERM_n
2025-05-06 23:43:24 +08:00
Stefan Reinauer
7b4b8724b9
Add memory map overview comment to top level module
2025-05-06 23:25:02 +08:00
Stefan Reinauer
c08c96c426
RTL: INTVEC support
2025-05-06 23:17:05 +08:00
Stefan Reinauer
c55ad41d92
RTL: Add intreg access
2025-05-06 23:10:20 +08:00
