RTL: Add intreg access

RTL/intreg_access.v

@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+
+module intreg_access (
+    input wire CLK,
+    input wire RESET_n,
+    input wire [27:0] ADDR,
+    input wire READ,
+    input wire FCS_n,
+    input wire slave_cycle,
+    input wire configured,
+    input wire NCR_INT,
+
+    output reg int_dtack,
+    output reg INT_n
+);
+
+// INTREG is at 0x900000 within the Z3 BAR
+wire intreg_match = slave_cycle && configured && (ADDR[27:1] == 27'h900000 >> 1);
+
+reg int_pending;
+
+always @(posedge CLK or negedge RESET_n) begin
+    if (!RESET_n) begin
+        int_pending <= 0;
+        int_dtack <= 0;
+        INT_n <= 1;
+    end else begin
+        // latch interrupt edge from NCR
+        if (NCR_INT)
+            int_pending <= 1;
+
+        // clear on read to INTREG
+        if (!FCS_n && READ && intreg_match)
+            int_pending <= 0;
+
+        // output level for INT_n (active low)
+        INT_n <= ~int_pending;
+
+        // dtack: one-cycle delay on INTREG read
+        case (int_dtack)
+            1'b0:
+                if (!FCS_n && READ && intreg_match)
+                    int_dtack <= 1;
+            1'b1:
+                if (FCS_n)
+                    int_dtack <= 0;
+        endcase
+    end
+end
+
+endmodule
+

RTL/top.v

@@ -120,6 +120,7 @@ wire autoconfig_dtack;
 wire scsi_dtack;
 wire rom_dtack;
 wire sid_dtack;
+wire int_dtack;
 
 always @(posedge CLK or negedge IORST_n)
 begin
@@ -160,7 +161,8 @@ begin
           end else if ((autoconfig_dtack && autoconfig_cycle) ||
 		       (scsi_dtack && scsi_cycle) ||
 		       rom_dtack ||
-		       sid_dtack) begin
+		       sid_dtack ||
+		       int_dtack) begin
             z3_state <= Z3_END;
           end
         end
@@ -238,4 +240,17 @@ sid_access SID_ACCESS (
   .SID_n(SID_n)
 );
 
+intreg_access INTREG_ACCESS (
+  .CLK(CLK),
+  .RESET_n(IORST_n),
+  .ADDR({ADDR, A[7:0]}),
+  .READ(READ),
+  .FCS_n(FCS_n_sync[1]),
+  .slave_cycle(!MASTER && !BMASTER),
+  .configured(configured),
+  .NCR_INT(NCR_INT),
+  .int_dtack(int_dtack),
+  .INT_n(INT_n)
+);
+
 endmodule