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Fixup address decodes

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*_region was matching when slave_cycle was true but without checking that the base address matched - this would cause these regions to match when other Z3 boards are being accessed
This commit is contained in:
Matt Harlum 2025-07-13 10:11:44 +00:00
parent bd5990cd71
commit c8b767916e
2 changed files with 7 additions and 5 deletions
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3
RTL/intreg_access.v
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@ -17,6 +17,7 @@ module intreg_access (
input wire RESET_n,
input wire FCS_n,
input wire configured,
input wire interrupt_region,
// -- Zorro III Bus Inputs for IACK Cycle
input wire [2:0] FC, // Function Codes
@ -48,7 +49,7 @@ reg [7:0] int_vector; // Stores the interrupt vector written by the driver
// The interrupt control register is mapped to the base address 0x880000.
// A write to this space sets the interrupt vector (INTREG function).
// A read during an IACK cycle retrieves the vector (INTVEC function).
wire match_intreg_write = configured && !LOCK && (ADDR[23:17] == 8'h44) && !READ;
wire match_intreg_write = interrupt_region && !LOCK && !READ;
//wire match_intvec_read = configured && !LOCK && (ADDR[23:17] == 8'h44) && READ; // Reading from the space provides the vector
// Zorro III Interrupt Acknowledge Cycle Detection

9
RTL/top.v
View File

@ -169,10 +169,10 @@ assign CLK = clk_int;
* 000000 ROM
*/
wire rom_region = configured && slave_cycle && (A[23:0] >= 24'h000000 && A[23:0] < 24'h800000);
wire scsi_region = configured && slave_cycle && (A[23:0] >= 24'h800000 && A[23:0] < 24'h880000);
wire interrupt_region = configured && slave_cycle && (A[23:0] >= 24'h880000 && A[23:0] < 24'h8c0000);
wire idreg_region = configured && slave_cycle && (A[23:0] >= 24'h8c0000 && A[23:0] < 24'h8f0000);
wire rom_region = scsi_addr_match && slave_cycle && (A[23:0] >= 24'h000000 && A[23:0] < 24'h800000);
wire scsi_region = scsi_addr_match && slave_cycle && (A[23:0] >= 24'h800000 && A[23:0] < 24'h880000);
wire interrupt_region = scsi_addr_match && slave_cycle && (A[23:0] >= 24'h880000 && A[23:0] < 24'h8c0000);
wire idreg_region = scsi_addr_match && slave_cycle && (A[23:0] >= 24'h8c0000 && A[23:0] < 24'h8f0000);
// --- Address Latching and Matching ---
always @(negedge Z_FCS_n or negedge IORST_n) begin
@ -404,6 +404,7 @@ intreg_access INTREG_ACCESS (
.RESET_n(IORST_n),
.FCS_n(!bfcs),
.configured(configured),
.interrupt_region(interrupt_region),
// --- Zorro III Bus Inputs
.FC(FC),
.ADDR(A[23:17]),