LIV2/A4092-dev
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  • c8b767916e Fixup address decodes main Matt Harlum 2025-07-13 10:11:44 +00:00
  • bd5990cd71 Fixup DOE Matt Harlum 2025-07-13 10:10:42 +00:00
  • 418ef069ee Clean up rom_access.v Stefan Reinauer 2025-07-13 00:20:30 -07:00
  • cdd811c8df a4092flash overhaul Stefan Reinauer 2025-07-13 00:18:14 -07:00
  • 6048c860e7 Fix verification code in a4092flash Stefan Reinauer 2025-07-12 10:25:35 -07:00
  • 24669ba584 Add xise file Stefan Reinauer 2025-07-11 20:53:25 -07:00
  • 38c0d42e97 Zorro protocol Stefan Reinauer 2025-07-11 20:51:55 -07:00
  • 092b4fbe00 No need for DTACK, handled by buffer_control.v Stefan Reinauer 2025-07-11 20:34:21 -07:00
  • 78978a9f81 Simplify address bus logic Stefan Reinauer 2025-07-11 20:14:53 -07:00
  • fa917aa47c Autoconfig update part 2 Stefan Reinauer 2025-07-11 20:11:41 -07:00
  • f902f963d9 FCS is high active and Z_FCS_n is low active Stefan Reinauer 2025-07-11 20:08:26 -07:00
  • 2b05ad6e75 Autoconfig update from Dorken Stefan Reinauer 2025-07-11 19:33:43 -07:00
  • 718776d7f0 intreg: NCR_INT is low active, Stefan Reinauer 2025-07-11 18:57:29 -07:00
  • a3e881544c a4092flash: Fix detection and verification Stefan Reinauer 2025-07-10 13:28:01 -07:00
  • 9726dcb0e3 MASTER_n is an input in our design Stefan Reinauer 2025-07-03 10:56:19 -07:00
  • 87c917c7ff Fix signal names for scsi slave interface Stefan Reinauer 2025-07-02 12:58:45 -07:00
  • eee9972f1c factor out scsi slave module Stefan Reinauer 2025-07-01 23:51:52 -07:00
  • d243623362 Clean up sid access Stefan Reinauer 2025-07-01 20:07:46 -07:00
  • 9dfc5e04bb INT2_n is shared so it should be 0 or Z Stefan Reinauer 2025-07-01 18:55:58 -07:00
  • 71b4b70f16 Define MTACK_n and CBACK_n Stefan Reinauer 2025-07-01 18:55:18 -07:00
  • 7cc5bb32a5 Fix RCHNG in zorro arbiter Stefan Reinauer 2025-07-01 13:42:30 -07:00
  • 824c17327e Move memory map handling into top.v Stefan Reinauer 2025-07-01 12:43:11 -07:00
  • 75a9444fe7 buffer_control: Plumb through all buffer enables Stefan Reinauer 2025-06-30 16:47:10 -07:00
  • ca54af6007 Move regions to top level Stefan Reinauer 2025-06-29 22:52:32 -07:00
  • 88725f507f buffer control was way off Stefan Reinauer 2025-06-28 23:40:52 -07:00
  • 8b470ec6b1 Update kibot config Stefan Reinauer 2025-06-14 21:53:25 -07:00
  • 1de0fdb589 Fix up Makefile / kibot calls Stefan Reinauer 2025-06-14 00:15:44 -07:00
  • 15fd667096 Remove spaces from JLCPCB part numbers Stefan Reinauer 2025-06-13 11:11:11 -07:00
  • c8d9cc29b7 Allow bridged solder mask for Zorro3 connector Stefan Reinauer 2025-06-13 10:53:07 -07:00
  • 0b4546da1a Fix 3d model for TSSOP-48 Stefan Reinauer 2025-06-12 22:49:35 -07:00
  • 3a0176d311 Fix 3d model path Stefan Reinauer 2025-06-12 22:41:31 -07:00
  • 9b43097cfb Clean up a4091flash Stefan Reinauer 2025-06-12 16:31:41 -07:00
  • fa989bfd10 Adjust flash.c for A4092 flash memory mapping Stefan Reinauer 2025-06-12 16:01:52 -07:00
  • f5d57d43b4 Initial attempt at a4092flash, based on LIV2's lideflash Stefan Reinauer 2025-06-12 14:43:17 -07:00
  • c4973d4cc6 Update Backpanel for smaller footprint Stefan Reinauer 2025-06-09 22:55:53 -07:00
  • ae9092d0e7 Add rotations for all parts Stefan Reinauer 2025-06-09 00:36:47 -07:00
  • 50c21e0c83 Fix up capacitor array footprint Stefan Reinauer 2025-06-08 23:22:41 -07:00
  • ebc04245bb Finish DS2107 terminator Stefan Reinauer 2025-06-08 21:46:52 -07:00
  • 21ea04db71 Update DEV version of the terminator Stefan Reinauer 2025-06-08 17:19:40 -07:00
  • 6c63135045 Update LT1118-2.85 based terminator Stefan Reinauer 2025-06-08 16:19:50 -07:00
  • be5aaffd74 RTL: Address matching for intreg Stefan Reinauer 2025-06-07 12:01:37 -07:00
  • 293179aec8 Fix address mapping Stefan Reinauer 2025-06-07 23:36:44 -07:00
  • 758385b5f3 RTL: Fix signal naming and hook up right bits of DIP Stefan Reinauer 2025-06-07 11:29:29 -07:00
  • 67f86c9a51 RTL: Drop double assignment of DOE and DS_n Stefan Reinauer 2025-06-07 11:03:33 -07:00
  • 90f0ecdb1f Update scsi_access Stefan Reinauer 2025-06-05 00:14:09 -07:00
  • 716cb5cb36 Add Gerbers Stefan Reinauer 2025-06-06 17:47:53 -07:00
  • 568c12774c Update PCB image Stefan Reinauer 2025-06-06 17:46:52 -07:00
  • 890b881e16 Update PCB Stefan Reinauer 2025-06-06 13:22:13 -07:00
  • 432fbb9239 Update footprints Stefan Reinauer 2025-06-06 12:54:23 -07:00
  • 64a2fb03db U1-4 routing completed Monse 2025-06-06 12:02:36 -07:00
  • e9f4af8904 Update to use new footprint for U1,2,3,4 Stefan Reinauer 2025-06-06 07:54:29 -07:00
  • 527d8f134f Add SN74ABT16543DGGR symbol / footprint Stefan Reinauer 2025-06-06 07:52:03 -07:00
  • c7179e01c9 Update PCB from Schematics, new image Stefan Reinauer 2025-06-05 21:04:26 -07:00
  • ad624fcb72 Remove ^Z from GAL source Stefan Reinauer 2025-06-05 15:10:50 -07:00
  • a93f6e9c82 Drop u304.txt Stefan Reinauer 2025-06-05 15:15:33 -07:00
  • 7c9bc343cc Fix Data Bus output Stefan Reinauer 2025-06-05 00:06:45 -07:00
  • 411d3726cf Removed fiducial copper and copper sliver rule Monse 2025-06-01 14:32:01 -07:00
  • 8e7f750e63 Update JLCPCB part numbers Stefan Reinauer 2025-06-01 12:38:42 -07:00
  • b6c1ccfd10 Update RTL Stefan Reinauer 2025-06-01 12:38:16 -07:00
  • 3c65920347 Fix 3d image path in footprints Stefan Reinauer 2025-05-31 22:39:22 -07:00
  • 94f827d1ed L4/L3 cleanup Monse 2025-05-31 21:22:38 -07:00
  • d22d7f7d0d A4092 text Top cutout Monse 2025-05-31 17:11:19 -07:00
  • fff5e8e57a DRCs checks Monse 2025-05-30 10:25:55 -07:00
  • 1a213776c6 RTL: Add additional address, data and spi signals Stefan Reinauer 2025-05-30 08:28:22 -07:00
  • ae39aab253 RTL: Add additional data and address lines Stefan Reinauer 2025-05-30 08:25:34 -07:00
  • 0b40860c76 Move A4092 main PCB to subdirectory Stefan Reinauer 2025-05-29 14:13:09 -07:00
  • 160f629b66 Restructure directories, Add Terminator designs Stefan Reinauer 2025-05-29 13:44:19 -07:00
  • c767d02364 Imported netlist Monse 2025-05-28 21:21:52 -07:00
  • 32267e49b8 board cleanup Monse 2025-05-28 19:11:11 -07:00
  • b5c61a47d2 Add Zorro 3 DMA master Stefan Reinauer 2025-05-28 11:47:16 -07:00
  • 113478eaf4 Add GAL source code for reference Stefan Reinauer 2025-05-28 11:42:19 -07:00
  • 3dae3b237d Add bypass cap for Berg connector Stefan Reinauer 2025-05-27 23:40:00 -07:00
  • 3e4f35d1b9 Imported latest netlist Monse 2025-05-27 22:35:58 -07:00
  • f25e716a9a DRCs checks Monse 2025-05-27 22:28:37 -07:00
  • e462978d1c Review fixes on scsi2 page Stefan Reinauer 2025-05-27 22:11:25 -07:00
  • d73007ccb7 routing is completed Monse 2025-05-27 22:19:57 -07:00
  • 8d241f9578 Routing in progress Monse 2025-05-27 22:14:19 -07:00
  • 87926617af Fix 3V3 -> V3_3 Stefan Reinauer 2025-05-27 20:57:37 -07:00
  • 5e84bdbec2 Re-sort address lines Stefan Reinauer 2025-05-27 20:51:56 -07:00
  • 05b7b7bcc4 Routing in progress Monse 2025-05-27 20:46:41 -07:00
  • ae3d69ead8 Add D[12..15] and A[9..16,20] to CPLD Stefan Reinauer 2025-05-27 19:58:01 -07:00
  • e5eff60cdc Recreate PCB from schematics Stefan Reinauer 2025-05-27 14:58:40 -07:00
  • 25593396b6 Hook up Flash page Stefan Reinauer 2025-05-27 14:46:59 -07:00
  • c698792dfd Add SPI flash option and move flash to its own page Stefan Reinauer 2025-05-27 08:28:28 -07:00
  • bfe8762e38 GND vias Monse 2025-05-26 18:08:31 -07:00
  • c679cfd763 Update PCB image Stefan Reinauer 2025-05-25 23:51:47 -07:00
  • aaf76db883 Add fiducials and clean up schematics Stefan Reinauer 2025-05-25 23:46:42 -07:00
  • 5847d02536 routing is completed Monse 2025-05-25 22:09:45 -07:00
  • 221884abca V5 routing in progress Monse 2025-05-25 19:20:11 -07:00
  • a7dcbaf6fa Minor trace and silkscreen fixes Stefan Reinauer 2025-05-23 22:52:11 -07:00
  • e5d209f673 Merge colinear tracks Stefan Reinauer 2025-05-23 21:14:59 -07:00
  • 33bb615178 Update PCB from schematics Stefan Reinauer 2025-05-23 18:33:56 -07:00
  • f99dcb17ac Clean up schematics Stefan Reinauer 2025-05-23 16:42:07 -07:00
  • c3d6261690 Update footprint graphics Stefan Reinauer 2025-05-23 16:40:23 -07:00
  • 3ed2572ea9 Improve Zorro III connector and round off PCB outline Stefan Reinauer 2025-05-22 21:32:29 -07:00
  • dd3c20c540 V5 Routing Monse 2025-05-21 18:29:31 -07:00
  • 2c4ab7893e Update SCSI connector Stefan Reinauer 2025-05-20 23:50:20 -07:00
  • 504886ddd5 Use APAQ Tech 250AVHA470M0606 not AVEA Stefan Reinauer 2025-05-20 22:27:51 -07:00
  • fb26170ed4 Update PCB file Stefan Reinauer 2025-05-20 22:18:09 -07:00
  • 803fbf57a2 Fix LCSC parts issues Stefan Reinauer 2025-05-20 22:17:07 -07:00