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RTL: Address matching for intreg

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Make address matching for intreg the same as for everything else,
using bits 23-17
This commit is contained in:
Stefan Reinauer 2025-06-07 12:01:37 -07:00
parent 293179aec8
commit be5aaffd74
2 changed files with 4 additions and 4 deletions
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6
RTL/intreg_access.v
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@ -20,7 +20,7 @@ module intreg_access (
// -- Zorro III Bus Inputs for IACK Cycle
input wire [2:0] FC, // Function Codes
input wire [23:1] ADDR, // Address Bus
input wire [23:17] ADDR, // Address Bus
input wire LOCK, // Zorro LOCK signal (original A1)
input wire READ,
input wire DS0_n,
@ -48,8 +48,8 @@ reg [7:0] int_vector; // Stores the interrupt vector written by the driver
// The interrupt control register is mapped to the base address 0x880000.
// A write to this space sets the interrupt vector (INTREG function).
// A read during an IACK cycle retrieves the vector (INTVEC function).
wire match_intreg_write = configured && !LOCK && (ADDR[23:4] == 20'h88000) && !READ;
wire match_intvec_read = configured && !LOCK && (ADDR[23:4] == 20'h88000) && READ; // Reading from the space provides the vector
wire match_intreg_write = configured && !LOCK && (ADDR[23:17] == 8'h44) && !READ;
//wire match_intvec_read = configured && !LOCK && (ADDR[23:17] == 8'h44) && READ; // Reading from the space provides the vector
// Zorro III Interrupt Acknowledge Cycle Detection
// An IACK cycle is FC=7 ('111') and targets a specific address range.

2
RTL/top.v
View File

@ -335,7 +335,7 @@ intreg_access INTREG_ACCESS (
.FCS_n(!bfcs),
.configured(configured),
.FC(FC),
.ADDR(full_addr[23:1]),
.ADDR(full_addr[23:17]),
.LOCK(Z_LOCK),
.READ(READ),
.DS0_n(DS_n[0]),