816a0f6340
Tweak more footprints to make hand assembly easier
2024-08-28 21:08:41 +12:00
0735f59ba7
Switch to hand-solder footprints for passives
2024-08-28 16:20:36 +12:00
25a272fa1e
Add protection for reverse installation of the board
2024-08-28 16:20:36 +12:00
923cdd0bb3
README: fix typo
2024-08-28 16:14:21 +12:00
bd55aac7c4
Update BOM
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* Change LED part number
* Fix Polyfuse link
2024-08-28 12:39:53 +12:00
6dd181056c
README: fixup C1,C12 part link (thanks @RetroFletch !)
2024-05-08 21:12:18 +12:00
f068d24f47
Update README
2024-05-08 21:09:50 +12:00
1551249b90
RTL: Fix bug in ROM Bank select
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At reset the rom bank select was set to follow addr[16:15] until IDE was activated by a write to any IDE reg.
After that it reflects the value of the rom_bankSel register
On a new board with no driver yet in flash this switch would not be triggered, causing the driver to be written to the wrong bank of flash.
Now the switch will flip on any write to the boards range, the flash identification step will trigger this.
2024-04-18 16:25:16 +12:00
7e949f9765
Add option to build for 64K board size
2024-03-02 15:59:49 +13:00
9def334bef
Autoconfig: Don't hardcode upper address bits
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Kickstart may place the board in the Z2 Memory region if IO area is full.
2024-03-02 15:40:02 +13:00
462a16b953
Update README with links to Release
2024-01-15 09:52:23 +13:00
11ebac607e
Fixup flash rotation in pick and place file
2024-01-15 09:46:33 +13:00
3c19789e4a
Resize RIPPLE.jpg
2024-01-15 08:26:48 +13:00
33704a8391
Update README
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Note 2TB drive and CD Boot support
2024-01-15 08:25:43 +13:00
33ca76889e
Add photo of Rev A
2024-01-15 08:21:39 +13:00
33b134d813
Add Bill-of-Materials and shoutouts to README
2023-11-18 20:40:39 +00:00
ec1083faf4
RTL: Only use bank select register after ide enabled
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Before then the ROM bank select is connected to A16 to allow loading modules by the bootloader
2023-11-18 19:51:34 +00:00
5e1237c056
Revert timing changes
2023-11-18 19:49:38 +00:00
b8b0178772
Change R17 from 330 to 1K (IDE LED was insanley bright)
2023-10-22 17:03:44 +02:00
d92e60953c
Fixup pin mapping
2023-10-20 19:06:34 +00:00
b31d9414c2
Change IDECS decode, tweak timing
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* Don't latch AS_n on falling edge, setup time not guaranteed
* IOW now active from S4
* On Reads, open IDE buffers as soon as UDS/LDS asserted
2023-10-20 19:06:00 +00:00
1f9973fba7
Expose second Bank select pin from CPLD
2023-10-13 11:44:31 +00:00
4ca94ddd3d
Route second bank select
2023-10-13 12:57:01 +02:00
7eb51c0ce6
Add flash bank select
2023-10-11 11:02:29 +00:00
36c812807a
RTL: Add Proto-A2 Extra IDE Chip selects and update UCF
2023-10-11 10:16:39 +00:00
c99f8d6eb1
Route bank select pin to ROM
2023-10-08 16:05:52 +02:00
50fadde109
Fixup LED circuit
2023-10-07 17:04:51 +02:00
1ab028f067
Tweaks after testing feedback
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* Check RESET length before asserting, seems noise is causing cold-boot issues on BUSRST
* Enable Buffers for reads during S4 regardless of DS'es
* Fixups for Autoconfig
* IDE: don't assert IOW/IOW until S3 to meet address set-up times
2023-09-25 18:55:14 +00:00
ee9068b231
Add CS1 to both IDE channels
2023-09-25 20:45:57 +02:00
dc50974a5e
Rev A1: changes
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* Dump BUSRST and use regular reset
* Ditch the worthless ferrites
* Add the gadget header
* Add A2000/4000 LED Header
2023-09-20 23:32:05 +02:00
ebacb93b37
Fixups
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IDE Enable logic wasn't working in A4000/060
2023-09-03 20:20:10 +00:00
819a9eccb6
Proto A1
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* Fix LED pinout
* Reduce LED resistor to 150 Ohm
* Separate Primary/Secondary channel Activity signals
2023-08-21 22:54:13 +02:00
36e76d08ef
Fixup some issues
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* Qualify SLAVE_n with AS_n or it will trigger during Z3 cycles
* Don't register CFGIN at AS_n posedge - Z3 cards would prevent this from working
* Disable DTACK/OVR gen as it's not needed
2023-08-20 07:42:59 +00:00
6eb2d8a3fa
Update README
2023-08-14 10:50:35 +00:00
4cd67c076a
Fixup everything and make it actually work
2023-08-14 07:39:20 +00:00
6a7b69fcce
Update CPLD Pin mapping and tweak a few things
2023-07-24 20:24:46 +00:00
a01a926003
Add License.md
2023-07-24 16:58:11 +02:00
279bfcb175
Release Rev_A
2023-07-24 16:56:39 +02:00
101214b9b1
Move Disable jumper
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Also route the signal through a buffer to protect the CPLD
2023-07-16 17:23:13 +02:00
c13ef80952
Add JLC Part numbers for IDE Connectors & TH caps
2023-07-13 16:41:54 +02:00
abee39926c
Change some resistor values from 10K to 1K out of paranoia
2023-07-13 15:54:51 +02:00
32846236ff
Add pull-up for unconnected CS1 pin of IDE channels
2023-07-12 20:29:08 +02:00
7f1c8157c8
Moved CPLD and ROM data behind IDE buffers
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* Enable Buffers for IDE, ROM and Autoconfig
* Add SLAVE_n equation
2023-07-12 08:36:13 +00:00
a61b822c16
Add Firmware
2023-07-12 08:36:13 +00:00
2e87b06f37
Move ROM and CPLD data connections to buffered side
2023-07-12 10:30:23 +02:00
9353015e6d
Routing complete, need to double-check
2023-07-10 16:23:03 +02:00
e92db97d39
Rename to RIPPLE, do a bunch more routing etc
2023-07-04 13:03:45 +02:00
ada1612930
A good start
2023-06-25 19:59:43 +02:00
55a873f313
Begin schematic
2023-02-11 20:51:31 +01:00
12f0d58f16
Initial commit.
2023-02-09 14:20:20 +01:00
