LIV2/A4092-dev
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Author SHA1 Message Date
Stefan Reinauer
78dadf5706 Undo silkscreen changes 2025-04-18 19:28:08 -07:00
Stefan Reinauer
553a6931e5 Fix up some silkscreen 2025-04-18 17:50:47 -07:00
Stefan Reinauer
0ccab43bb9 Rename all Uxx parts from U1 to U13 for consistency 2025-04-18 16:46:08 -07:00
Stefan Reinauer
bbba326b4d CPLD fixes 
* Terminate unused CPLD connections with NC
* Move D0 to pin 117 to line up with the other databus pins
 2025-04-18 15:58:48 -07:00
Monse
ace11dcd24 Routing in progress 2025-04-17 19:17:25 -07:00
Monse
78b3afeb5c Routing in progress 2025-04-16 19:35:50 -07:00
Monse
1d25bf4f06 Routing in progress 2025-04-16 17:49:16 -07:00
Monse
932a304793 SCSI Controller breakout 2025-04-15 20:08:50 -07:00
Stefan Reinauer
fd380803f9 Update README 2025-04-14 21:27:13 -07:00
Stefan Reinauer
9f0187f668 Fix 74FCT16543 and CAY16_102J4LF footprints 2025-04-14 21:25:08 -07:00
Monse
d1a2798187 SW1 and U10 breakout 2025-04-13 14:51:56 -07:00
Monse
22ff0ef0f9 Routing in progress 2025-04-12 22:35:14 -07:00
Stefan Reinauer
38fd31814f Add Picture 2025-04-12 22:07:10 -07:00
Stefan Reinauer
0b53dbb027 Ignore backups 2025-04-12 19:40:12 -07:00
Stefan Reinauer
79084b79b6 Drop backup files from repo 2025-04-12 19:37:58 -07:00
Stefan Reinauer
c8c03601eb Fix HS_GND connection on pin2 of the scsi terminators 2025-04-11 22:22:46 -07:00
Stefan Reinauer
c2e3719dd3 Fix Xilinx 3d model in footprint 2025-04-11 22:22:12 -07:00
Stefan Reinauer
1bdfad1356 Fixed SCSI connector footprint. Added 3d models for all parts. 2025-04-11 22:02:46 -07:00
Stefan Reinauer
42f075444b Update Kicad project file 2025-04-10 22:58:50 -07:00
Stefan Reinauer
f7f0f3825d Resync the PCB from Schematics, add some 3d models 2025-04-10 22:56:53 -07:00
Stefan Reinauer
b0e2d4645c Remove large Molex power connector 2025-04-10 22:50:33 -07:00
Stefan Reinauer
ff863a9337 CPLD bypass caps need to be on the 3.3V rail, not 5V 2025-04-10 22:49:20 -07:00
Monse
4abea84415 Routing in progress 2025-04-10 21:44:51 -07:00
Stefan Reinauer
bef80285a5 Remove lock files and ignore them 2025-04-10 17:58:23 -07:00
Stefan Reinauer
5e0244522e Start adding pin descriptions to A4092 RTL 2025-04-09 20:45:10 -07:00
Monse
960d868897 Routed several nets 2025-04-09 20:23:09 -07:00
Monse
36b823e63d Rotaded J1 by 180 degree and re-arrange components close to the controller 2025-04-02 22:07:08 -07:00
Stefan Reinauer
1dcfacda86 Add skeleton to include Gerbers, BOM files, RTL etc 2025-04-02 07:58:30 -07:00
Stefan Reinauer
72844ba9f6 Reorg Kicad files to Kicad/ 2025-04-01 23:51:34 -07:00
Monse
2f4939e0b4 1. Placement looks feasible on 1 layer. Pending routing confirmation. 
2. pages 1-2 placed.
3. components outside the outline are looking for a new home.
 2025-04-01 21:26:29 -07:00
Stefan Reinauer
12a910f4ba Add .gitignore 2025-04-01 19:50:59 -07:00
Stefan Reinauer
7ebd68e339 Move to XC95144XL 
and other changes related to that.
 2025-04-01 08:56:16 -07:00
Stefan Reinauer
2cb31057f9 Free up some pins and add an LED 2025-03-30 16:40:35 -07:00
Stefan Reinauer
9700b1cc85 Move IORST to Reset / GCLR Pin 2025-03-30 14:39:35 -07:00
Stefan Reinauer
490e441d0b Drop 74ABT74 
The 74ABT74 is only used as a divider to create 25MHz from the 50MHz clock, and
it can be removed. Instead, the 50MHz are directly brought to the ATF1508. CLK
will be used as an output, not an input, so move away from GCLK pin. CLKI is no
longer needed on a pin as it doesn't connect to anything anymore.
 2025-03-30 14:16:44 -07:00
Stefan Reinauer
625a067928 Add link to datasheet to cpld 2025-03-30 14:02:10 -07:00
Stefan Reinauer
8ff97c2c74 Incorporate Feedback from LIV2 
- Move CLK, CLKI, Z_7M to GCLK1, GCLK2, GCLK3
  as they are connected to all macro cells.
- OE1 and GCLR on the 1508 are input only, move FC0/FC1 there.

Also found two duplicate signals on the ATF1508, consolidated them.
This leaves us with 8 free I/Os at the moment.
 2025-03-30 07:56:27 -07:00
Stefan Reinauer
7646d554db Remove ABT TODO 2025-03-29 22:27:32 -07:00
Stefan Reinauer
87d739e8c6 Switch to 74ABT16543 2025-03-29 22:25:49 -07:00
Stefan Reinauer
c867456cda Connect VCCINT on CPLD, add GND and V5 to power symbols 2025-03-29 22:14:25 -07:00
Stefan Reinauer
212e09eeee Update RN footprint to CAY16_102J4LF 
- Rename RNs from R to RN.
- Fix U5 footprint
- Rename pages to be consecutive numbers
 2025-03-29 18:14:25 -07:00
Stefan Reinauer
d3c24cddaa Finished first pass at new schematics 2025-03-29 16:26:06 -07:00
Stefan Reinauer
6e3aede482 Add power connectors 2025-03-29 15:54:31 -07:00
Stefan Reinauer
5a63f63940 Latest updates 2025-03-28 21:21:53 -07:00
Stefan Reinauer
8b94a7e42b Update footprints 2025-03-28 21:21:14 -07:00
Stefan Reinauer
e89fb28ce7 More work. Getting there. 2025-03-26 23:33:32 +01:00
Stefan Reinauer
aea2bbd876 Redraw footprints, finish Termination/Connectors 2025-03-24 01:27:30 +01:00
Stefan Reinauer
6c03787002 Add external SCSI connector 2025-03-23 11:19:52 +01:00
Stefan Reinauer
1388c1d05b Update design 2025-03-16 17:55:58 +01:00
Stefan Reinauer
b570a6942d Place CPLD, NCR and last 543 (Latched Trabceiver) 2025-03-12 00:02:37 -07:00