LIV2/A4092-dev
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257 Commits

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Author SHA1 Message Date
Monse
98a45b6a97 Routing 2025-05-03 15:10:52 -07:00
Monse
ad190bc84c Routing 2025-05-03 14:58:31 -07:00
Monse
abd9e35aeb Routing 2025-05-03 11:16:59 -07:00
Stefan Reinauer
18bde198c3 Revert: Rename majority of bypass capacitors to match their Uxx 2025-05-03 21:05:31 +08:00
Stefan Reinauer
97567437f9 Rename majority of bypass capacitors to match their Uxx 
i.e. U4 will have C4A, C4B, C4C, C4D
 2025-05-03 20:59:54 +08:00
Monse
01c3ebf68c Routing 2025-05-01 19:57:34 -07:00
Monse
45935f54b4 Routing 2025-04-29 19:20:59 -07:00
Monse
ae2344c434 General routing 2025-04-28 18:11:13 -07:00
Monse
8e601f0e58 Routing 2025-04-28 16:34:54 -07:00
Monse
ff06de59a7 Routing and J5 placement 2025-04-27 10:09:19 -07:00
Stefan Reinauer
1a6ea47819 Move HPDB50 connector to back panel 2025-04-25 23:09:28 -07:00
Monse
3613b5c4f4 Routing in progress 2025-04-23 18:51:15 -07:00
Monse
f130d11536 Feedback implemented:Make sure card guides don't hit components on the left side 2025-04-23 18:10:06 -07:00
Monse
97008bd268 Feedback impleted for: [200~SCSI_TERMPWR traces should be 0.3mm min~ 2025-04-23 17:35:30 -07:00
Stefan Reinauer
70cc19b265 Implement autoconfig (courtesy Matt Harlum) 2025-04-23 15:25:33 -07:00
Stefan Reinauer
5031868b31 Fix issues #12 and #13 
Z_BEER and SCSI_BUSY were not connected correctly (single net pins)
 2025-04-22 23:50:12 -07:00
Monse
ebe99a0565 more routing 2025-04-21 20:06:47 -07:00
Monse
d60a1cc280 Move transceivers north 2025-04-21 18:43:53 -07:00
Monse
8003925864 Routing 2025-04-21 18:09:14 -07:00
Stefan Reinauer
b6a765bcc7 Update image 2025-04-20 23:47:36 -07:00
Monse
6287c71e0e Routing 2025-04-20 16:31:38 -07:00
Monse
40f2d20c6d Routing 2025-04-20 15:32:08 -07:00
Stefan Reinauer
a4ac5b781b Add pulldown of ROM_CE to PCB 2025-04-19 22:37:17 -07:00
Stefan Reinauer
c26ebc0103 Add footprint to pull down of ROM_CE 2025-04-19 22:34:22 -07:00
Monse
de0dbd279d Routing in progress 2025-04-19 22:28:23 -07:00
Stefan Reinauer
f3ba030b8b Stop tracking A4092.kicad_prl 2025-04-19 22:25:00 -07:00
Stefan Reinauer
8b36b5bb2a Update from schematics 2025-04-19 22:16:00 -07:00
Stefan Reinauer
1774181965 Update sheet, add pull down on ROM_CE 2025-04-19 22:14:09 -07:00
Monse
1fed82290b routin gin progress 2025-04-19 22:00:30 -07:00
Stefan Reinauer
27df2d79d1 Fix various errors from issue #1 2025-04-19 21:48:14 -07:00
Stefan Reinauer
45352a03f9 Clean up top level 2025-04-19 21:47:13 -07:00
Monse
7f520e6e0c Merge remote-tracking branch 'origin/main' 2025-04-19 21:32:48 -07:00
Monse
d67a36646c Add Kicad/A4092.kicad_prl to .gitignore 2025-04-19 21:32:15 -07:00
Monse
6243a7b559 Your commit message 2025-04-19 21:26:37 -07:00
Stefan Reinauer
d23942a577 Update PCB from schematics 2025-04-19 21:14:50 -07:00
Stefan Reinauer
7c6db29d20 CPLD pin net swap (issue #7) 
• PLD_FC0-FC2 nets move from Pin 2-4 to 75-77
• PLD_DS0-DS2 nets move from Pin 33-35 to 78-80
• ROM_WE net move from Pin 102  to 5
• ROM_OE net move from Pin 107 to 4

Additionally moved ROM_CE to P3 and PLD_DS3 to P81
 2025-04-19 21:12:21 -07:00
Stefan Reinauer
c6b5bd3ae3 This should be PLD_DS0, not PLD_DS1 2025-04-19 20:58:21 -07:00
Stefan Reinauer
3398e4abc6 PLD_NACK is only a CPLD internal signal 2025-04-19 20:57:53 -07:00
Monse
a5b9aea8e6 Merge remote-tracking branch 'origin/main' 2025-04-19 20:51:40 -07:00
Monse
34c619aa6e Your commit message 2025-04-19 20:51:09 -07:00
Monse
50a2ea0608 CPLD Routing 2025-04-19 20:45:47 -07:00
Stefan Reinauer
20ab8e32bc Fix Z_LOCK in zorro3 schematics 2025-04-19 20:36:35 -07:00
Stefan Reinauer
0dcc303dda ROM_WE Single net Issue #3 
Connect ROM_WE to CPLD. Also connect ROM_CE.
 2025-04-19 18:42:54 -07:00
Stefan Reinauer
935877a1dc Fix Zorro III symbol 2025-04-19 18:30:19 -07:00
Stefan Reinauer
7d97539ed3 Update Flash part symbol 2025-04-19 18:21:08 -07:00
Stefan Reinauer
1bc5972cb5 Clean up CPLD signals / prepare for rotation 2025-04-19 14:46:19 -07:00
Monse
bf167b5b5e Import netlist from commit: Move D0/D1 (again) and remove PLD_INT 2025-04-18 21:13:54 -07:00
Monse
5113826248 routing progress 2025-04-18 21:04:21 -07:00
Monse
cbed202b6e Routing in progress 2025-04-18 21:04:21 -07:00
Stefan Reinauer
56d8b2b536 Move D0/D1 (again) and remove PLD_INT 2025-04-18 20:50:26 -07:00