Stefan Reinauer
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d98329c228
|
Add remaining part numbers, remove C20, C30, C31
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2025-05-19 23:06:58 -07:00 |
|
Monse
|
9c0159e404
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Update PCB from schematic, routing
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2025-05-19 21:29:42 -07:00 |
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Stefan Reinauer
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43a4fe8f25
|
Pin swap on RN15 the right way
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2025-05-19 21:04:01 -07:00 |
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Monse
|
ce8e3be952
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Routing
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2025-05-19 20:41:48 -07:00 |
|
Stefan Reinauer
|
a4de309288
|
RN15 pin swap
As requested in issue #7
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2025-05-19 20:35:27 -07:00 |
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Stefan Reinauer
|
e65c33c1a7
|
Update PCB from schematic
|
2025-05-19 17:14:53 -07:00 |
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Stefan Reinauer
|
f9cdbfa4fe
|
Add more LCSC parts and mark some parts DNP
|
2025-05-19 17:12:36 -07:00 |
|
Monse
|
96de6372e1
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GND connections
|
2025-05-18 18:55:16 -07:00 |
|
Monse
|
9fbaf22238
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Signal routing
|
2025-05-18 18:05:10 -07:00 |
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Stefan Reinauer
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886f6a69cc
|
Add correct footprints for DIP resistors
And start adding LCSC part numbers
|
2025-05-18 17:24:47 -07:00 |
|
Stefan Reinauer
|
8a552d0dfb
|
Add option to move SID into CPLD / flash entirely
|
2025-05-18 16:18:34 -07:00 |
|
Stefan Reinauer
|
b5d984aef8
|
Drop PRODID from Makefile
It is not used in the code
|
2025-05-18 10:12:58 -07:00 |
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Stefan Reinauer
|
3d6a09f518
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Connect DIP_EXT_TERM to CPLD
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2025-05-18 09:50:20 -07:00 |
|
Stefan Reinauer
|
b032a0b749
|
Remove a rogue NC
|
2025-05-17 22:28:55 -07:00 |
|
Monse
|
badefcfab5
|
PWR routing
|
2025-05-17 18:46:22 -07:00 |
|
Monse
|
0a51863632
|
V3_3 routing
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2025-05-17 18:26:23 -07:00 |
|
Monse
|
cbe8130a3c
|
bypass caps routing
|
2025-05-16 18:36:17 -07:00 |
|
Monse
|
3204de258d
|
DRCs checks
|
2025-05-16 18:03:48 -07:00 |
|
Monse
|
4c9238ead6
|
Signal routing
|
2025-05-16 17:28:38 -07:00 |
|
Monse
|
c21021b366
|
SW1 routing
|
2025-05-16 16:54:12 -07:00 |
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Stefan Reinauer
|
fef639957b
|
Kicad: Pin swaps on RN10 and RN16
Fixes issue #1 and issue #2
|
2025-05-14 22:34:24 -07:00 |
|
Monse
|
9e24298516
|
HD50 conn routing
|
2025-05-14 18:10:30 -07:00 |
|
Monse
|
5741c2ce1a
|
General Routing
|
2025-05-14 17:17:03 -07:00 |
|
Stefan Reinauer
|
2e358d3e1a
|
Zorro Master Arbiter needs Z_FCS
|
2025-05-12 07:52:54 -07:00 |
|
Stefan Reinauer
|
726a9127b0
|
Use Z_LOCK/A1 for intreg
|
2025-05-12 07:44:38 -07:00 |
|
Stefan Reinauer
|
ea5e2dd130
|
Connect SC0 from 53c710 to CPLD
This will let us implement the "False DMA Request Bugfix"
|
2025-05-12 07:13:38 -07:00 |
|
Stefan Reinauer
|
ce30cb22ce
|
Add 3d model to power connector
It somehow got lost along the way
|
2025-05-12 00:05:32 -07:00 |
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Stefan Reinauer
|
7965d14fad
|
Try to fix up pin naming
|
2025-05-11 23:19:30 -07:00 |
|
Stefan Reinauer
|
07b96fa1a4
|
More compile fixes.
|
2025-05-11 16:29:36 -07:00 |
|
Stefan Reinauer
|
5f670d4c0e
|
Some compilation fixes
|
2025-05-11 01:14:14 -07:00 |
|
Stefan Reinauer
|
a93037bb9a
|
Add two missing bulk power caps from old schematics
|
2025-05-09 23:48:36 +08:00 |
|
Stefan Reinauer
|
4b67d20a8b
|
Update termination capacitors to tantalum
and clean up bypass caps in schematic
|
2025-05-09 15:01:30 +08:00 |
|
Stefan Reinauer
|
5fb5f5c25a
|
Fix pin mapping
|
2025-05-07 22:42:59 +08:00 |
|
Stefan Reinauer
|
d52cf8b0e8
|
Fix up molex connector
|
2025-05-07 22:42:31 +08:00 |
|
Stefan Reinauer
|
dd5269e515
|
Add clocks, replace 74F74
|
2025-05-07 13:37:46 +08:00 |
|
Stefan Reinauer
|
89ce4b67ed
|
Zorro Master Arbiter
|
2025-05-07 13:34:38 +08:00 |
|
Stefan Reinauer
|
c2f34466f4
|
Add more remaining signals
|
2025-05-07 12:22:23 +08:00 |
|
Stefan Reinauer
|
0c1b5945bf
|
Add INT2 handling
|
2025-05-07 10:54:10 +08:00 |
|
Stefan Reinauer
|
9584898714
|
RTL: Add DBLT
|
2025-05-07 00:04:05 +08:00 |
|
Stefan Reinauer
|
0f8fdc2de6
|
add actual scsi access and buffer control
|
2025-05-07 00:00:09 +08:00 |
|
Stefan Reinauer
|
ab2dea27fd
|
RTL: Drive MTCR_n, CBACK_n, and STERM_n
|
2025-05-06 23:43:24 +08:00 |
|
Stefan Reinauer
|
7b4b8724b9
|
Add memory map overview comment to top level module
|
2025-05-06 23:25:02 +08:00 |
|
Stefan Reinauer
|
c08c96c426
|
RTL: INTVEC support
|
2025-05-06 23:17:05 +08:00 |
|
Stefan Reinauer
|
c55ad41d92
|
RTL: Add intreg access
|
2025-05-06 23:10:20 +08:00 |
|
Stefan Reinauer
|
5f54e3ecb8
|
RTL: Add SID (SCSI ID jumper) access
|
2025-05-06 23:07:12 +08:00 |
|
Stefan Reinauer
|
1e06c64bed
|
RTL: Add ROM access
|
2025-05-06 22:49:24 +08:00 |
|
Stefan Reinauer
|
43bc62733e
|
Fix up silkscreen across the board
|
2025-05-06 12:06:17 +08:00 |
|
Stefan Reinauer
|
241c847e1d
|
Rename capacitors
|
2025-05-05 15:21:03 +08:00 |
|
Stefan Reinauer
|
a78a35d42a
|
Add more bypass caps
|
2025-05-05 14:46:07 +08:00 |
|
Stefan Reinauer
|
e3e0d59824
|
Replace C47 and C46 with Tantalum capacitors
|
2025-05-05 13:23:53 +08:00 |
|