LIV2/A4092-dev
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Monse 2f4939e0b4 1. Placement looks feasible on 1 layer. Pending routing confirmation. 
2. pages 1-2 placed.
3. components outside the outline are looking for a new home.
2025-04-01 21:26:29 -07:00
Libraries
Move to XC95144XL
2025-04-01 08:56:16 -07:00
.gitignore
Add .gitignore
2025-04-01 19:50:59 -07:00
A4092.kicad_pcb
1. Placement looks feasible on 1 layer. Pending routing confirmation.
2025-04-01 21:26:29 -07:00
A4092.kicad_prl
1. Placement looks feasible on 1 layer. Pending routing confirmation.
2025-04-01 21:26:29 -07:00
A4092.kicad_pro
Redraw footprints, finish Termination/Connectors
2025-03-24 01:27:30 +01:00
A4092.kicad_sch
Update RN footprint to CAY16_102J4LF
2025-03-29 18:14:25 -07:00
cpld.kicad_sch
Move to XC95144XL
2025-04-01 08:56:16 -07:00
fp-lib-table
Move to XC95144XL
2025-04-01 08:56:16 -07:00
power.kicad_sch
Connect VCCINT on CPLD, add GND and V5 to power symbols
2025-03-29 22:14:25 -07:00
README.md
first commit
2025-03-04 22:04:03 -08:00
scsi2.kicad_sch
Move to XC95144XL
2025-04-01 08:56:16 -07:00
sym-lib-table
Move to XC95144XL
2025-04-01 08:56:16 -07:00
Termination.kicad_sch
Update RN footprint to CAY16_102J4LF
2025-03-29 18:14:25 -07:00
zorro3.kicad_sch
Move to XC95144XL
2025-04-01 08:56:16 -07:00

README.md

The file is empty.
Description
No description provided
Readme 27 MiB
Languages
Verilog 50.2%
C 43.9%
Makefile 5.2%
Shell 0.6%
SystemVerilog 0.1%