Add skeleton to include Gerbers, BOM files, RTL etc

.devcontainer/devcontainer.json

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+// For format details, see https://aka.ms/devcontainer.json. For config options, see the
+// README at: https://github.com/devcontainers/templates/tree/main/src/ubuntu
+{
+	"name": "Ubuntu",
+	// Or use a Dockerfile or Docker Compose file. More info: https://containers.dev/guide/dockerfile
+	"image": "mcr.microsoft.com/devcontainers/base:ubuntu",
+	"features": {
+		"ghcr.io/jungaretti/features/make:1": {},
+		"ghcr.io/veryl-lang/devcontainer-features/verilator:1": {}
+	},
+	
+	"onCreateCommand": ".devcontainer/verible.sh",
+
+	"customizations": {
+		"vscode": {
+			"extensions": [
+				"mshr-h.veriloghdl"
+			]
+		}
+	}
+
+	// Features to add to the dev container. More info: https://containers.dev/features.
+	// "features": {},
+
+	// Use 'forwardPorts' to make a list of ports inside the container available locally.
+	// "forwardPorts": [],
+
+	// Use 'postCreateCommand' to run commands after the container is created.
+	// "postCreateCommand": "uname -a",
+
+	// Configure tool-specific properties.
+	// "customizations": {},
+
+	// Uncomment to connect as root instead. More info: https://aka.ms/dev-containers-non-root.
+	// "remoteUser": "root"
+}

.devcontainer/verible.sh

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+#!/bin/bash -eu
+
+case $(arch) in
+    aarch64):
+        ARCH=arm64
+        ;;
+    x86_64):
+        ARCH=x86_64
+        ;;
+    *)
+        echo "Unknown architecture"
+        exit 1
+        ;;
+esac
+
+URL=$(curl -Ls https://api.github.com/repos/chipsalliance/verible/releases/latest | jq --raw-output ".assets[] | select(.name|test(\"${ARCH}\")).browser_download_url")
+
+curl -Lsf ${URL} -o /tmp/verible.tar.gz
+tar xf /tmp/verible.tar.gz -C /tmp 
+sudo mv /tmp/verible-*/bin/* /usr/local/bin
+rm -rf /tmp/verible*

.github/workflows/release.yml

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+name: Generate release files
+
+on:
+  push:
+    tags:
+      - "Release_**"
+      - "Rev**"
+      - "Proto**"
+      - "proto**"
+  workflow_dispatch:
+
+jobs:
+  draft_release:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Zip Gerbers
+        run: zip -r Gerbers.zip Gerbers
+      - name: release
+        uses: softprops/action-gh-release@v1
+        with:
+          draft: true
+          files: |
+            Docs/Schematic.pdf
+            Gerbers/*.csv
+            Docs/*.html
+            Gerbers.zip
+            Binary/*.jed

.gitignore

@@ -1,2 +1 @@
-A4092-backups/
-fp-info-cache
+**/.DS_Store

Kicad/.gitignore

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+**/.DS_Store
+*.zip
+*.xml
+Gerbers
+*-backups/*
+*-bak
+*-erc.txt
+*-drc.txt
+kibot_errors.*

Kicad/Makefile

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+PROJECT=A4092
+KIBOT_CONF=./kibot/release.kibot.yaml
+GERBER_OUTPUT=../Gerbers
+
+DRILLS=$(GERBER_OUTPUT)/$(PROJECT)-NPTH.drl $(GERBER_OUTPUT)/$(PROJECT)-PTH.drl
+
+GERBERS=$(GERBER_OUTPUT)/$(PROJECT)-B_Cu.gbl $(GERBER_OUTPUT)/$(PROJECT)-B_Mask.gbs $(GERBER_OUTPUT)/$(PROJECT)-B_Silkscreen.gbo $(GERBER_OUTPUT)/$(PROJECT)-Edge_Cuts.gm1 $(GERBER_OUTPUT)/$(PROJECT)-F_Cu.gtl $(GERBER_OUTPUT)/$(PROJECT)-F_Mask.gts $(GERBER_OUTPUT)/$(PROJECT)-F_Silkscreen.gto $(GERBER_OUTPUT)/$(PROJECT)-F_Paste.gtp $(GERBER_OUTPUT)/$(PROJECT)-B_Paste.gbp $(DRILLS)
+
+JLCPCB=$(GERBER_OUTPUT)/$(PROJECT)_bom_jlc.csv $(GERBER_OUTPUT)/$(PROJECT)_cpl_jlc.csv
+BOM=$(GERBER_OUTPUT)/$(PROJECT)_bom.html
+
+.PHONY: release
+
+
+all:	$(GERBERS) $(JLCPCB) $(BOM) ../Docs/Schematic.pdf ../Docs/$(PROJECT)-ibom.html
+
+schematic: ../Docs/Schematic.pdf
+gerbers: $(GERBERS)
+jlcpcb: $(JLCPCB)
+bom: $(BOM)
+ibom: ../Docs/$(PROJECT)-ibom.html
+
+$(GERBERS) ../Docs/PCB.png:	$(PROJECT).kicad_pcb
+	kibot -c $(KIBOT_CONF) Gerbers Drills Image
+
+$(JLCPCB): $(PROJECT).kicad_pcb $(PROJECT).kicad_sch
+	kibot --skip-pre all -c $(KIBOT_CONF) JLCPCB_position JLCPCB_bom
+
+../Docs/Schematic.pdf:	$(PROJECT).kicad_sch
+	kibot -s all -c $(KIBOT_CONF) Schematic
+
+../Docs/$(PROJECT)-ibom.html:	$(PROJECT).kicad_pcb
+	kibot -s all -c $(KIBOT_CONF) IBOM
+
+$(BOM): $(PROJECT).kicad_pcb $(PROJECT).kicad_sch
+	kibot --skip-pre all -c $(KIBOT_CONF) html_bom

Kicad/kibot/release.kibot.yaml

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+kibot:
+  version: 1
+
+filters:
+  - name: 'exclude_kibuzzard'
+    type: 'generic'
+    comment: 'Exclude Kibuzzard stuff'
+    exclude_any:
+      - column: References
+        regex: '^kibuzzard.*'
+  - name: 'exclude_tht'
+    type: 'generic'
+    comment: 'Exclude thru-hole parts'
+    exclude_tht: true
+  - name: 'fix_rotation'
+    comment: 'Adjust rotation for JLC'
+    type: rot_footprint
+    rotations:
+      - ["^TSOP-II", 270.0]
+      - ["^TSOP-I-32", 270.0]
+      - ["^SOT-89", 180.0]
+      - ["^SW_DIP_SPSTx04", 270.0]
+      - ["^CP_EIA-3216-18_Kemet-A", 0.0]
+      - ["^SOT-363", 180.0]
+
+
+variants:
+  - name: rotated
+    comment: 'Just a place holder for the rotation filter'
+    type: kibom
+    variant: rotated
+    pre_transform: 'fix_rotation'
+
+preflight:
+  check_zone_fills: true
+  fill_zones: false
+  run_drc: true
+  run_erc: true
+  update_xml: true
+  ignore_unconnected: true
+  filters:
+    - error: 'pin_not_connected'
+      filter: 'Pin not connected'
+    - error: 'silk_overlap'
+      filter: 'Silkscreen overlap'
+    - error: 'pin_not_driven'
+      filter: 'Input pin not driven by output'
+      regex: 'Input pin not driven by any Output pins'
+
+outputs:
+  - name: Gerbers
+    comment: "Generate gerber files"
+    type: gerber
+    dir: '../Gerbers'
+    options:
+      exclude_edge_layer: true
+      exclude_pads_from_silkscreen: true
+      plot_sheet_reference: false
+      plot_footprint_refs: true
+      plot_footprint_values: false
+      force_plot_invisible_refs_vals: false
+      tent_vias: true
+      use_protel_extensions: true
+      create_gerber_job_file: false
+      disable_aperture_macros: true
+      gerber_precision: 4.6
+      use_gerber_x2_attributes: false
+      use_gerber_net_attributes: false
+      line_width: 0.1
+      subtract_mask_from_silk: true
+      inner_extension_pattern: '.g%Nl'
+      use_aux_axis_as_origin: true
+
+    layers:
+      - F.Cu
+      - B.Cu
+      - In1.Cu
+      - In2.Cu
+      - F.SilkS
+      - B.SilkS
+      - F.Paste
+      - B.Paste
+      - F.Mask
+      - B.Mask
+      - Edge.Cuts
+
+  - name: Drills
+    comment: Drill files
+    type: excellon
+    dir: '../Gerbers'
+    options:
+      pth_id: '-PTH'
+      npth_id: '-NPTH'
+      metric_units: true
+      route_mode_for_oval_holes: false
+      pth_and_npth_single_file: false
+      use_aux_axis_as_origin: true
+      output: "%f%i.%x"
+
+  - name: Schematic
+    comment: "Output PDF Schematic"
+    type: pdf_sch_print
+    options:
+      frame: true
+      output: "../Docs/Schematic.pdf"
+
+  - name: IBOM
+    type: ibom
+    comment: "Generate HTML Interactive BOM"
+    dir: ../Docs
+    options:
+      include_tracks: true
+      layer_view: FB
+      highlight_pin1: true
+      include_nets: true
+      dark_mode: true
+      extra_fields: "LCSC #,Mouser #"
+
+  - name: 3dImage
+    type: render_3d
+    comment: "3D Render"
+    run_by_default: true
+    options:
+      ray_tracing: false
+      output: ../Docs/PCB.png
+      zoom: 8
+      view: top
+      no_tht: true
+      orthographic: true
+      download: false
+      width: 1300
+      height: 530
+
+  - name: Image
+    type: pcbdraw
+    comment: "Draw PCB"
+    options:
+      output: ../Docs/PCB.png
+      format: png
+      show_solderpaste: false
+      show_components: none
+
+  - name: 'JLCPCB_position'
+    comment: "Pick and place file, JLCPCB style"
+    type: position
+    options:
+      variant: rotated
+      output: '../Gerbers/%f_cpl_jlc.%x'
+      format: CSV
+      units: millimeters
+      separate_files_for_front_and_back: false
+      use_aux_axis_as_origin: true
+      only_smd: true
+      columns:
+        - id: Ref
+          name: Designator
+        - Val
+        - Package
+        - id: PosX
+          name: "Mid X"
+        - id: PosY
+          name: "Mid Y"
+        - id: Rot
+          name: Rotation
+        - id: Side
+          name: Layer
+
+  - name: 'JLCPCB_bom'
+    comment: "BoM for JLCPCB"
+    type: bom
+    options:
+      output: '../Gerbers/%f_%i_jlc.%x'
+      exclude_filter: 
+        - 'exclude_tht'
+        - 'exclude_kibuzzard'
+      ref_separator: ','
+      columns:
+        - field: 'Quantity Per PCB'
+          name: Qty
+        - field: Value
+          name: Comment
+        - field: References
+          name: Designator
+        - Footprint
+        - field: 'LCSC #'
+          name: 'LCSC Part #'
+      csv:
+        hide_pcb_info: true
+        hide_stats_info: true
+        quote_all: true
+
+  - name: 'html_bom'
+    comment: "BoM"
+    type: bom
+    options:
+      output: '../Docs/%f_%i.%x'
+      exclude_filter: 
+        - 'exclude_kibuzzard'
+      ref_separator: ','
+      columns:
+        - field: 'Quantity Per PCB'
+          name: Qty
+        - field: Value
+          name: Comment
+        - field: References
+          name: Designator
+        - Footprint
+        - field: 'Mouser #'
+          name: 'Mouser Part'
+        - field: 'LCSC #'
+          name: 'LCSC Part'
+      html:
+        title: '%f Bill of materials'
+        hide_pcb_info: true
+        hide_stats_info: true
+        quote_all: true
+        lcsc_link: "LCSC #"
+        mouser_link: "Mouser #"

README.md

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+# A4091
+
+A modern successor to the A4091.
+
+![PCB](Docs/PCB.png?raw=True)
+

RTL/.gitignore

@@ -0,0 +1,7 @@
+_xmsgs
+tmp/
+*.log
+*.err
+*.jed
+*.prj
+local.mk

RTL/Makefile

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+PROJECT=A4092
+PART=XC95144XL-10-TQ144
+WORKDIR=tmp
+SERIAL=0
+PRODID=72
+DEFINES=makedefines SERIAL=32'h${SERIAL} PRODID=${PRODID}
+
+CABLE=usb21
+
+CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper -optimize speed -keepio
+
+.PHONY:	all clean timing
+
+all:	$(PROJECT).jed timing
+
+$(PROJECT).prj: *.v
+	-$(shell rm -f $@)
+	-$(foreach source,$^,$(shell echo verilog work $(source) >> $@))
+
+$(WORKDIR)/$(PROJECT).ngc:	*.v $(PROJECT).prj
+	-@mkdir $(WORKDIR)
+	@sed -r "s#^(-ofn).*#\1 ..\/$@#g;s#^(-ifn).*#\1 ../$(PROJECT).prj#g;s#^(-define).*#\1 {$(DEFINES)}#g" template.xst > $@.xst
+	cd $(WORKDIR) && xst -ifn ../$@.xst -ofn $(PROJECT)-xst.log
+
+$(WORKDIR)/%.ngd:	$(WORKDIR)/%.ngc $(PROJECT).ucf
+	cd $(WORKDIR) && ngdbuild -p $(PART) -uc ../$(PROJECT).ucf ../$< ../$@
+
+$(WORKDIR)/%.rpt $(WORKDIR)/%.vm6:	$(WORKDIR)/%.ngd $(PROJECT).ucf
+	cd $(WORKDIR) && cpldfit $(CPLDFITFLAGS) -p $(PART) ../$< | egrep -v "^CS: block|^$$"
+	cp $(WORKDIR)/$(PROJECT).rpt .
+
+%.jed:	$(WORKDIR)/%.vm6
+	hprep6 -i $<
+	cp $@ ../Binary/
+
+fit:	$(WORKDIR)/$(PROJECT).vm6
+
+
+%.tim:	$(WORKDIR)/%.vm6
+	cd $(WORKDIR) && taengine -l ../$@ -f $(PROJECT)
+
+
+timing:	$(PROJECT).tim
+
+clean:
+	-rm -rvf tmp
+	-rm *.jed
+	-rm *.prj
+
+flash:	$(PROJECT).jed
+	@echo "setMode -bs\n"\
+	"setCable -p $(CABLE)\n"\
+	"identify\n"\
+	"assignfile -p 1 -file $<\n"\
+	"erase -p 1\n"\
+	"program -p 1\n"\
+	"verify -p 1" | LD_PRELOAD=/opt/Xilinx/usb-driver/libusb-driver.so impact -batch

RTL/template.xst

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+set -tmpdir "."
+set -xsthdpdir "."
+run
+-ifn IFN
+-ifmt mixed
+-ofn OFN
+-ofmt NGC
+-p xc9500xl
+-top SETME
+-opt_mode Speed
+-opt_level 2
+-iuc NO
+-keep_hierarchy Yes
+-netlist_hierarchy As_Optimized
+-rtlview No
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-mux_extract Yes
+-resource_sharing YES
+-iobuf YES
+-pld_mp YES
+-pld_xp YES
+-pld_ce YES
+-wysiwyg NO
+-equivalent_register_removal YES
+-define {}