LIV2/A4092-dev
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A4092-dev/RTL
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Matt Harlum c8b767916e Fixup address decodes 
*_region was matching when slave_cycle was true but without checking that the base address matched - this would cause these regions to match when other Z3 boards are being accessed
2025-07-13 22:16:12 +12:00
..
.gitignore
Add skeleton to include Gerbers, BOM files, RTL etc
2025-04-02 07:58:30 -07:00
A4092.ucf
FCS is high active and Z_FCS_n is low active
2025-07-11 20:08:26 -07:00
A4092.xise
Add xise file
2025-07-11 20:53:25 -07:00
autoconfig.v
Autoconfig update from Dorken
2025-07-11 19:33:43 -07:00
buffer_control.v
Move memory map handling into top.v
2025-07-01 12:43:11 -07:00
globalparams.vh
Implement autoconfig (courtesy Matt Harlum)
2025-04-23 15:25:33 -07:00
intreg_access.v
Fixup address decodes
2025-07-13 22:16:12 +12:00
Makefile
Add option to move SID into CPLD / flash entirely
2025-05-18 16:18:34 -07:00
rom_access.v
Clean up rom_access.v
2025-07-13 00:20:30 -07:00
scsi_access.v
Move memory map handling into top.v
2025-07-01 12:43:11 -07:00
scsi_slave.v
Fixup DOE
2025-07-13 22:16:12 +12:00
sid_access.v
Clean up sid access
2025-07-01 20:10:49 -07:00
spi_access.v
factor out scsi slave module
2025-07-01 23:51:52 -07:00
template.xst
Start adding pin descriptions to A4092 RTL
2025-04-09 20:45:10 -07:00
top.v
Fixup address decodes
2025-07-13 22:16:12 +12:00
zorro_dma_master.v
Fix address mapping
2025-06-07 23:36:44 -07:00
zorro_master_arbiter.v
factor out scsi slave module
2025-07-01 23:51:52 -07:00