mirror of
https://github.com/LIV2/A4092-dev.git
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eee9972f1c
- stub out spi module - top: A[] is now inout - top: CLK and MASTER_n are wires - top: SIZ is an output to the SCSI chip - straighten zorro arbiter
108 lines
3.6 KiB
Verilog
108 lines
3.6 KiB
Verilog
`timescale 1ns / 1ps
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//
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// MODULE: zorro_master_arbiter
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// DESCRIPTION:
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// Implementation of the Zorro III bus arbiter from U303.
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//
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module zorro_master_arbiter (
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// --- Inputs ---
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input wire C7M, // This should be the 7MHz arbitration clock (Z_7M)
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input wire RESET_n,
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input wire MASTER_n, // SCSI chip is local master (active high, inverted from MASTER_n)
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input wire SBR_n, // SCSI Bus Request (active low)
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input wire EBG_n, // Zorro Bus Grant (active low)
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input wire FCS, // Zorro FCS
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input wire DTACK_n,
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// --- Outputs ---
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output wire MYBUS_n, // A4091 owns the Zorro bus (active low)
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output wire SBG_n, // SCSI Bus Grant (active low)
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output wire EBR_n, // Zorro Bus Request (active low)
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output wire BMASTER // Buffered MASTER signal
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);
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// Internal state from U303
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reg reged; // Latches that we are registered as a Z3 master
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reg ebr; // The registered bus request signal
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reg rchng; // A change in registration is required
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reg ssbr; // Synchronized SCSI Bus Request
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reg mybus; // Internal, active-high version of MYBUS
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reg blockbg; // after 1st sbg must block any further till unregistered and ebg deasserts
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reg sbg_reg; // A register to hold the state of SBG_n
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reg smaster;
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reg dmaster;
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// wires for combinational logic
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wire sbg_next;
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wire blockbg_next;
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// SCSI Bus Grant logic from u303.pld
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// Describe the NEXT state using purely combinational logic
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assign blockbg_next = ~MASTER_n || (blockbg && reged) || (blockbg && ~EBG_n);
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assign sbg_next = ( (~FCS && DTACK_n && ~SBR_n && ~EBG_n && ~blockbg_next) ||
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(sbg_reg && ~SBR_n && ~blockbg_next) ||
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(sbg_reg && MASTER_n && ~blockbg_next) ) && RESET_n;
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assign MYBUS_n = ~mybus;
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assign SBG_n = ~sbg_reg;
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assign EBR_n = ~ebr;
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assign BMASTER = ~MASTER_n;
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// assign sbg_reg = ( (~FCS && DTACK_n && RESET_n && ~SBR_n && ~EBG_n && ~blockbg) ||
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// (sbg_reg && ~SBR_n && RESET_n && ~blockbg) ||
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// (sbg_reg && MASTER_n && RESET_n && ~blockbg) );
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// assign blockbg = ~MASTER_n || (blockbg && reged) || (blockbg && ~EBG_n);
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always @(posedge C7M or negedge RESET_n) begin
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if (!RESET_n) begin
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reged <= 1'b0;
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ebr <= 1'b0;
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rchng <= 1'b0;
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ssbr <= 1'b0;
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mybus <= 1'b0;
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smaster <= 1'b0;
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dmaster <= 1'b0;
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sbg_reg <= 1'b0;
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blockbg <= 1'b0;
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end else begin
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smaster <= ~MASTER_n;
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dmaster <= smaster;
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// Synchronize the SCSI Bus Request
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ssbr <= ~SBR_n;
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// RCHNG: A change of registration is necessary
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rchng <= (~reged && ssbr && ~ebr) || (reged && ~smaster && ~ebr && dmaster);
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// EBR: Zorro Bus Request is toggled to register/unregister
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if (rchng && ~ebr)
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ebr <= 1'b1;
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else
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ebr <= 1'b0;
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// REGED: The actual registration indicator
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if (~reged && ebr)
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reged <= 1'b1;
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else if (reged && ~ebr)
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reged <= 1'b0;
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// MYBUS: We own the bus when registered and granted
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if (reged && ~EBG_n)
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mybus <= 1'b1;
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else if (!FCS) // Hold the bus until the cycle completes
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mybus <= mybus;
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else
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mybus <= 1'b0;
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// Update the registers with their next state on the clock edge
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sbg_reg <= sbg_next;
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blockbg <= blockbg_next;
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end
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end
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endmodule
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