Stefan Reinauer
9726dcb0e3
MASTER_n is an input in our design
2025-07-03 10:56:19 -07:00
Stefan Reinauer
87c917c7ff
Fix signal names for scsi slave interface
2025-07-02 12:58:45 -07:00
Stefan Reinauer
eee9972f1c
factor out scsi slave module
...
- stub out spi module
- top: A[] is now inout
- top: CLK and MASTER_n are wires
- top: SIZ is an output to the SCSI chip
- straighten zorro arbiter
2025-07-01 23:51:52 -07:00
Stefan Reinauer
d243623362
Clean up sid access
2025-07-01 20:10:49 -07:00
Stefan Reinauer
9dfc5e04bb
INT2_n is shared so it should be 0 or Z
2025-07-01 18:55:58 -07:00
Stefan Reinauer
71b4b70f16
Define MTACK_n and CBACK_n
2025-07-01 18:55:18 -07:00
Stefan Reinauer
7cc5bb32a5
Fix RCHNG in zorro arbiter
...
and add dummy spi module
2025-07-01 13:42:30 -07:00
Stefan Reinauer
824c17327e
Move memory map handling into top.v
...
- Rename Z_7M to C7M
- Rename MYBBUS to MYBUS_n as it is active low
- Don't pass ADDR[] into modules if not needed
(intreg still missing)
- Fix SBG_n in zorro arbiter
2025-07-01 12:43:11 -07:00
Stefan Reinauer
75a9444fe7
buffer_control: Plumb through all buffer enables
...
When an input pin on a BiCMOS logic chip like the SN74ABT543 is left floating
(unconnected), its voltage can drift into an indeterminate state, somewhere
between a valid logic HIGH and a valid logic LOW.
In this intermediate state, both the internal pull-up and pull-down transistors
inside the chip's input buffer can turn on simultaneously. This creates a
low-impedance path directly from the power supply (Vcc) to ground (GND). This
condition is known as shoot-through current, and it causes the chip to draw
excessive power, which is dissipated as heat. This can make the chip get hot
very quickly and can permanently damage it.
2025-06-30 16:47:10 -07:00
Stefan Reinauer
ca54af6007
Move regions to top level
2025-06-29 22:52:32 -07:00
Stefan Reinauer
88725f507f
buffer control was way off
2025-06-28 23:40:52 -07:00
Stefan Reinauer
8b470ec6b1
Update kibot config
2025-06-14 21:53:25 -07:00
Stefan Reinauer
1de0fdb589
Fix up Makefile / kibot calls
2025-06-14 00:15:44 -07:00
Stefan Reinauer
15fd667096
Remove spaces from JLCPCB part numbers
2025-06-13 11:11:11 -07:00
Stefan Reinauer
c8d9cc29b7
Allow bridged solder mask for Zorro3 connector
2025-06-13 10:53:07 -07:00
Stefan Reinauer
0b4546da1a
Fix 3d model for TSSOP-48
2025-06-12 22:49:35 -07:00
Stefan Reinauer
3a0176d311
Fix 3d model path
2025-06-12 22:41:31 -07:00
Stefan Reinauer
9b43097cfb
Clean up a4091flash
2025-06-12 16:31:41 -07:00
Stefan Reinauer
fa989bfd10
Adjust flash.c for A4092 flash memory mapping
2025-06-12 16:01:52 -07:00
Stefan Reinauer
f5d57d43b4
Initial attempt at a4092flash, based on LIV2's lideflash
2025-06-12 14:43:17 -07:00
Stefan Reinauer
c4973d4cc6
Update Backpanel for smaller footprint
2025-06-09 22:55:53 -07:00
Stefan Reinauer
ae9092d0e7
Add rotations for all parts
2025-06-09 00:36:47 -07:00
Stefan Reinauer
50c21e0c83
Fix up capacitor array footprint
...
家裡創 did not like the digikey footprint.
2025-06-08 23:22:41 -07:00
Stefan Reinauer
ebc04245bb
Finish DS2107 terminator
2025-06-08 21:46:52 -07:00
Stefan Reinauer
21ea04db71
Update DEV version of the terminator
...
with switch for experimenting w/ mosfet
2025-06-08 17:19:40 -07:00
Stefan Reinauer
6c63135045
Update LT1118-2.85 based terminator
2025-06-08 16:19:50 -07:00
Stefan Reinauer
be5aaffd74
RTL: Address matching for intreg
...
Make address matching for intreg the same as for everything else,
using bits 23-17
2025-06-08 16:17:52 -07:00
Stefan Reinauer
293179aec8
Fix address mapping
2025-06-07 23:36:44 -07:00
Stefan Reinauer
758385b5f3
RTL: Fix signal naming and hook up right bits of DIP
2025-06-07 11:29:29 -07:00
Stefan Reinauer
67f86c9a51
RTL: Drop double assignment of DOE and DS_n
2025-06-07 11:03:33 -07:00
Stefan Reinauer
90f0ecdb1f
Update scsi_access
2025-06-06 23:11:29 -07:00
Stefan Reinauer
716cb5cb36
Add Gerbers
2025-06-06 17:47:53 -07:00
Stefan Reinauer
568c12774c
Update PCB image
2025-06-06 17:46:52 -07:00
Stefan Reinauer
890b881e16
Update PCB
2025-06-06 13:22:13 -07:00
Stefan Reinauer
432fbb9239
Update footprints
2025-06-06 12:54:23 -07:00
Monse
64a2fb03db
U1-4 routing completed
2025-06-06 12:02:36 -07:00
Stefan Reinauer
e9f4af8904
Update to use new footprint for U1,2,3,4
2025-06-06 07:54:29 -07:00
Stefan Reinauer
527d8f134f
Add SN74ABT16543DGGR symbol / footprint
2025-06-06 07:52:03 -07:00
Stefan Reinauer
c7179e01c9
Update PCB from Schematics, new image
2025-06-05 21:04:26 -07:00
Stefan Reinauer
ad624fcb72
Remove ^Z from GAL source
2025-06-05 15:16:01 -07:00
Stefan Reinauer
a93f6e9c82
Drop u304.txt
2025-06-05 15:15:33 -07:00
Stefan Reinauer
7c9bc343cc
Fix Data Bus output
2025-06-05 00:06:45 -07:00
Monse
411d3726cf
Removed fiducial copper and copper sliver rule
2025-06-01 14:32:01 -07:00
Stefan Reinauer
8e7f750e63
Update JLCPCB part numbers
...
Move to available and, if possible, basic parts
2025-06-01 12:38:42 -07:00
Stefan Reinauer
b6c1ccfd10
Update RTL
2025-06-01 12:38:16 -07:00
Stefan Reinauer
3c65920347
Fix 3d image path in footprints
2025-05-31 22:41:21 -07:00
Monse
94f827d1ed
L4/L3 cleanup
2025-05-31 21:22:38 -07:00
Monse
d22d7f7d0d
A4092 text Top cutout
2025-05-31 17:11:19 -07:00
Monse
fff5e8e57a
DRCs checks
2025-05-30 10:25:55 -07:00
Stefan Reinauer
1a213776c6
RTL: Add additional address, data and spi signals
2025-05-30 08:28:22 -07:00
