On reads, DTACK will now come out 3 clocks after the READ command to the RAM
With a CAS latency of 2, the read data will be valid at READ+2
The A4091 latches data as soon as DTACK is seen, so this delay was needed to make sure the A4091 correctly latches data from GottaGoFaZt3r
Previously the board would assert DTACK very early on reads for a speed
boost...
This usually isn't a problem because Buster is slow to notice but sometimes causes issues for the A4091
Thanks goes to dorken @ a1k.org for pointing this out
Previously ram_cycle would latch at FCSn asserted and not be cleared until another FCSn assertion happened
This caused issues because FCS_n_sync would lead ram_cycle_sync by 1 clock and this caused false memory cycles to start because ram_cycle_sync would still be true when it shouldn't be.
