LIV2/GottaGoFaZt3r
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Remove burst stuff

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Burst feature not working properly and probably not worth the pain
This commit is contained in:
Matt Harlum 2022-06-07 17:59:50 +00:00
parent 83ea78b380
commit d1cbe28505
3 changed files with 1078 additions and 1107 deletions
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2134
Binary/GottaGoFaZt3r.jed
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File diff suppressed because it is too large Load Diff

27
RTL/sdram.v
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@ -237,7 +237,7 @@ begin
// Wait for tRCD and also wait until we see data strobes before committing writes
access_cycle_wait: begin
`cmd(cmd_nop)
if (DS_n[3:0] != 4'b1111 && DOE || RW)
if (DS_n[3:0] != 4'b1111 && DOE)
ram_state <= access_cycle_rw;
else
ram_state <= access_cycle_wait; // No data strobes seen yet, hold off
@ -250,7 +250,7 @@ begin
// This allows for the board to be assembled with 128MB or 256MB without needing separate firmware.
access_cycle_rw: begin
dtack <= 1;
maddr_r[12:0] <= {3'b000,ADDR[27], ADDR[10:2]};
maddr_r[12:0] <= {3'b001,ADDR[27], ADDR[10:2]};
if (!RW) begin
`cmd(cmd_write)
DQM_n[3:0] <= DS_n[3:0];
@ -267,7 +267,6 @@ begin
// Take CKE low until the end of the Zorro cycle in order to hold the read output
// For write cycles, just keep NOP'ing
access_cycle_hold: begin
dtack <= 0;
`cmd(cmd_nop)
if (!FCS_n && DS_n[3:0] != 4'b1111) begin
if (RW)
@ -275,20 +274,13 @@ begin
ram_state <= access_cycle_hold;
end else begin
CKE <= 1;
if (!FCS_n)
// If Data strobes went inactive before FCS_n then it must be a burst
// Go do the next burst cycle
ram_state <= access_cycle_wait;
else
// Otherwise precharge and return to idle state
ram_state <= access_cycle_precharge;
ram_state <= access_cycle_precharge;
end
end
// Precharge all banks
// Wait for auto-precharge to complete
access_cycle_precharge: begin
`cmd(cmd_precharge)
maddr_r[10] <= 1'b1;
`cmd(cmd_nop)
ram_state <= ram_cycle_idle;
end
@ -317,16 +309,15 @@ begin
end
end
reg [3:0] dtack_delayed;
reg [2:0] dtack_delayed;
always @(posedge CLK or negedge RESET_n) begin
if (!RESET_n)
dtack_delayed[3:0] <= 4'b0;
dtack_delayed[2:0] <= 3'b0;
else
dtack_delayed[3:0] <= {dtack_delayed[2:0], dtack};
dtack_delayed[2:0] <= {dtack_delayed[1:0], dtack};
end
// Really bad hack to pulse dtack for 3xClock period during bursts... will be removed
assign DTACK_EN = dtack_delayed[1] || dtack_delayed[2] || dtack_delayed[3];
assign DTACK_EN = dtack_delayed[CAS_LATENCY-1];
endmodule

24
RTL/top.v
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@ -148,25 +148,6 @@ SDRAM SDRAM (
.configured (configured)
);
// Latch DTACK on strobe from SDRAM unit
// Clear on cycle end
FDCP FDCP_inst (
.CLR (FCS_n),
.PRE (1'b0),
.D (1'b1),
.C (ram_dtack),
.Q (dtack_latch)
);
reg bursting;
always @(negedge MTCR_n or posedge FCS_n) begin
if (FCS_n)
bursting <= 1'b0;
else
bursting <= 1'b1;
end
assign AD[31:28] = (autoconfig_cycle && BERR_n && DOE && READ) ? autoconfig_dout[3:0] : 4'bZ;
assign BUFOE_n = !ram_cycle || !DOE || !BERR_n;
@ -174,10 +155,9 @@ assign BUFDIR = READ;
assign CFGOUT_n = (SENSEZ3) ? autoconfig_cfgout : CFGIN_n;
assign SLAVE_n = !(!FCS_n && (autoconfig_cycle || ram_cycle));
// Not the final equation, just testing different ideas to get bursts working well
assign DTACK_n = (!SLAVE_n) ? !(dtack_latch && !bursting || ram_dtack || autoconfig_cycle) : 1'bZ;
assign DTACK_n = (!SLAVE_n) ? !(ram_dtack || autoconfig_cycle) : 1'bZ;
assign MTACK_n = (!SLAVE_n && ram_cycle) ? 1'b0 : 1'bZ;
assign MTACK_n = 1'bZ;
endmodule