mirror of
https://github.com/LIV2/GottaGoFaZt3r.git
synced 2025-12-06 00:32:44 +00:00
Tidy up code and add more comments
This commit is contained in:
parent
bc86047ed7
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bfd8223689
@ -1,5 +1,5 @@
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Programmer Jedec Bit Map
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Date Extracted: Fri Apr 22 17:47:25 2022
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Date Extracted: Sat Apr 23 14:44:35 2022
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QF93312*
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QP100*
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@ -243,12 +243,12 @@ L0008592 000000 000000 000000 000000 000000 000000 000000 000000*
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L0008640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0008704 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0008768 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0008832 00000000 00000000 00000000 00000000 00000000 00000000 00000100 00000000*
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L0008832 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0008896 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0008960 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000*
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L0009024 00000000 00000000 00000000 00000000 00000000 00000000 10000000 00000000*
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L0009088 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0009152 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
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L0009152 00000000 00000000 00000000 00000000 00000000 00000000 00000100 00000000*
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L0009216 000000 000000 000000 000000 000000 000000 000000 000000*
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L0009264 000000 000000 000000 000000 000000 000000 000000 000000*
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L0009312 000000 000000 000000 000000 000000 000000 000000 000000*
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@ -393,13 +393,13 @@ L0017232 000000 000000 000000 000000 000000 000000 000000 000000*
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L0017280 00000000 00000000 00000000 00000000 00000001 00000000 00000011 00000000*
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L0017344 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
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L0017408 00000000 00000000 00000000 00000000 00000010 00000001 00000010 00000000*
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L0017472 00000000 00000000 00000000 00000000 00000011 00000000 00000001 00000000*
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L0017472 00000000 00000000 00000000 00000000 00000011 00000000 00000101 00000000*
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L0017536 00000000 00000000 00000000 00000001 00000010 00000001 00000000 00000000*
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L0017600 00000000 00000000 00000000 00000011 00000010 00000001 00000000 00010000*
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L0017664 00000000 00000000 00000000 00000001 00000011 00000000 00000010 00000001*
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L0017728 00000000 00000000 00000000 00000001 00000000 00000000 00000001 00010011*
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L0017792 00000000 00000001 00000000 00000001 00000001 00000001 10000000 00000000*
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L0017856 000000 000000 000000 000000 000000 000000 000001 000000*
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L0017856 000000 000000 000000 000000 000000 000000 000000 000000*
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L0017904 000000 000000 000000 000000 000000 000000 000000 000000*
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L0017952 000000 000000 000000 000000 000000 000000 000000 000000*
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L0018000 000000 000000 000000 000000 000000 000000 000000 000000*
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@ -458,8 +458,8 @@ L0020992 00000000 00000000 00000000 00000000 00001000 00000000 00000000 00000000
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L0021056 00100000 00000000 00000000 10000000 00000000 00000001 00000000 00000000*
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L0021120 00000000 00000000 00000000 00100000 00000000 00000000 00000000 00000000*
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L0021184 00000000 00000000 00000000 00000000 00000000 00000000 10000001 00000001*
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L0021248 00000000 00000000 00000000 00000001 00000000 00000001 00000100 00000001*
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L0021312 000000 000000 000000 000000 000000 000000 000000 000000*
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L0021248 00000000 00000000 00000000 00000001 00000000 00000001 00000000 00000001*
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L0021312 000000 000000 000000 000000 000000 000000 000001 000000*
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L0021360 000000 000000 000000 000000 000000 000000 000000 000000*
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L0021408 000000 001000 000000 001100 000000 000000 000000 000000*
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L0021456 000000 000000 000000 000100 000000 000000 000000 000000*
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@ -39,17 +39,17 @@ NET "CFGOUT_n" LOC = "P30" ;
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NET "CKE" LOC = "P61" ;
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NET "CLK" LOC = "P27" ;
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NET "CLK" BUFG = "CLK" ;
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NET "CS<0>" LOC = "P35" ;
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NET "CS<1>" LOC = "P60" ;
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NET "CS_n<0>" LOC = "P35" ;
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NET "CS_n<1>" LOC = "P60" ;
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NET "DOE" LOC = "P74" ;
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NET "DQM<0>" LOC = "P68" ;
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NET "DQM<1>" LOC = "P66" ;
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NET "DQM<2>" LOC = "P36" ;
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NET "DQM<3>" LOC = "P37" ;
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NET "DS<0>" LOC = "P2" ;
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NET "DS<1>" LOC = "P70" ;
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NET "DS<2>" LOC = "P87" ;
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NET "DS<3>" LOC = "P86" ;
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NET "DQM_n<0>" LOC = "P68" ;
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NET "DQM_n<1>" LOC = "P66" ;
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NET "DQM_n<2>" LOC = "P36" ;
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NET "DQM_n<3>" LOC = "P37" ;
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NET "DS_n<0>" LOC = "P2" ;
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NET "DS_n<1>" LOC = "P70" ;
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NET "DS_n<2>" LOC = "P87" ;
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NET "DS_n<3>" LOC = "P86" ;
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NET "DTACK_n" LOC = "P90" ;
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NET "E" LOC = "P3" ;
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NET "FC<0>" LOC = "P18" ;
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@ -23,15 +23,15 @@ module Autoconfig (
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`define SERIAL 32'd421
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`define PRODID 8'h72
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`endif
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reg done = 0;
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localparam [15:0] mfg_id = 16'h07DB;
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localparam [7:0] prod_id = `PRODID;
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localparam [31:0] serial = `SERIAL;
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reg shutup;
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reg done = 0;
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reg shutup = 0;
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assign validspace = FC[1] ^ FC[0]; // 1 when FC indicates user/supervisor data/program space
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wire validspace = FC[1] ^ FC[0]; // 1 when FC indicates user/supervisor data/program space
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reg [1:0] vs;
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always @(posedge CLK) begin
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@ -52,40 +52,41 @@ end
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always @(posedge CLK or negedge RESET_n)
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begin
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if (!RESET_n) begin
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DOUT <= 4'b0;
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configured <= 1'b0;
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shutup <= 1'b0;
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addr_match <= 4'b1111;
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DOUT[3:0] <= 4'b0;
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configured <= 1'b0;
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shutup <= 1'b0;
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addr_match[3:0] <= 4'b1111;
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end else if (autoconfig_cycle && !FCS_n) begin
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if (READ) begin
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case ({ADDRL[5:0],ADDRL[6]})
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7'h00: DOUT <= 4'b1010; // Type: Zorro III Memory
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7'h01: DOUT <= 4'b0100; // 256 MB
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7'h02: DOUT <= ~prod_id[7:4]; // Product number
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7'h03: DOUT <= ~prod_id[3:0]; // Product number
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7'h04: DOUT <= ~4'b1011; // Memory device, Size Extension, Zorro III
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7'h05: DOUT <= ~4'b0001; // Automatically sized by OS
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7'h08: DOUT <= ~mfg_id[15:12]; // Manufacturer ID
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7'h09: DOUT <= ~mfg_id[11:8]; // Manufacturer ID
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7'h0A: DOUT <= ~mfg_id[7:4]; // Manufacturer ID
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7'h0B: DOUT <= ~mfg_id[3:0]; // Manufacturer ID
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7'h0C: DOUT <= ~serial[31:28]; // Serial number
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7'h0D: DOUT <= ~serial[27:24]; // Serial number
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7'h0E: DOUT <= ~serial[23:20]; // Serial number
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7'h0F: DOUT <= ~serial[19:16]; // Serial number
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7'h10: DOUT <= ~serial[15:12]; // Serial number
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7'h11: DOUT <= ~serial[11:8]; // Serial number
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7'h12: DOUT <= ~serial[7:4]; // Serial number
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7'h13: DOUT <= ~serial[3:0]; // Serial number
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7'h20: DOUT <= 4'b0;
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7'h21: DOUT <= 4'b0;
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default: DOUT <= 4'hF;
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7'h00: DOUT[3:0] <= 4'b1010; // Type: Zorro III Memory
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7'h01: DOUT[3:0] <= 4'b0100; // 256 MB
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7'h02: DOUT[3:0] <= ~prod_id[7:4]; // Product number
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7'h03: DOUT[3:0] <= ~prod_id[3:0]; // Product number
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7'h04: DOUT[3:0] <= ~4'b1011; // Memory device, Size Extension, Zorro III
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7'h05: DOUT[3:0] <= ~4'b0001; // Automatically sized by OS
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7'h08: DOUT[3:0] <= ~mfg_id[15:12]; // Manufacturer ID
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7'h09: DOUT[3:0] <= ~mfg_id[11:8]; // Manufacturer ID
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7'h0A: DOUT[3:0] <= ~mfg_id[7:4]; // Manufacturer ID
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7'h0B: DOUT[3:0] <= ~mfg_id[3:0]; // Manufacturer ID
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7'h0C: DOUT[3:0] <= ~serial[31:28]; // Serial number
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7'h0D: DOUT[3:0] <= ~serial[27:24]; // Serial number
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7'h0E: DOUT[3:0] <= ~serial[23:20]; // Serial number
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7'h0F: DOUT[3:0] <= ~serial[19:16]; // Serial number
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7'h10: DOUT[3:0] <= ~serial[15:12]; // Serial number
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7'h11: DOUT[3:0] <= ~serial[11:8]; // Serial number
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7'h12: DOUT[3:0] <= ~serial[7:4]; // Serial number
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7'h13: DOUT[3:0] <= ~serial[3:0]; // Serial number
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7'h20: DOUT[3:0] <= 4'b0;
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7'h21: DOUT[3:0] <= 4'b0;
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default: DOUT[3:0] <= 4'hF;
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endcase
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end else begin
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if (ADDRL[5:0] == 6'h13 && !DS_n) begin
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//configured <= 1;
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// Shutup
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shutup <= 1;
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end else if (ADDRL[5:0] == 6'h11 && !DS_n) begin
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// Write base address
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addr_match <= DIN[3:0];
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configured <= 1;
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end
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120
RTL/sdram.v
120
RTL/sdram.v
@ -2,15 +2,12 @@
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module SDRAM(
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input [27:2] ADDR,
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input DS0,
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input DS1,
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input DS2,
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input DS3,
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input [3:0] DS_n,
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input DOE,
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input FCS_n,
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input ram_cycle,
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input RESET_n,
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input RW_n,
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input RW,
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input CLK,
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input ECLK,
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input configured,
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@ -22,7 +19,7 @@ module SDRAM(
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output [1:0] CS_n,
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output WE_n,
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output reg CKE,
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output reg [3:0] DQM,
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output reg [3:0] DQM_n,
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output DTACK_EN
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);
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@ -32,10 +29,10 @@ localparam tRFC = 4;
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localparam CAS_LATENCY = 3'd2;
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`define initcmd(ARG) \
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{ras_n_i, cas_n_i, we_n_i} <= ARG;
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{ras_i_n, cas_i_n, we_i_n} <= ARG;
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`define cmd(ARG) \
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{ras_n_r, cas_n_r, we_n_r} <= ARG;
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{ras_r_n, cas_r_n, we_r_n} <= ARG;
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// RAS CAS WE
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localparam cmd_nop = 3'b111,
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@ -56,14 +53,14 @@ localparam mode_register = {
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3'b0 // M2-0 - Burst length
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};
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reg [1:0] cs_n_i;
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reg ras_n_i;
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reg cas_n_i;
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reg we_n_i;
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reg [1:0] cs_n_r;
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reg ras_n_r;
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reg cas_n_r;
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reg we_n_r;
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reg [1:0] cs_i_n;
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reg ras_i_n;
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reg cas_i_n;
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reg we_i_n;
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reg [1:0] cs_r_n;
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reg ras_r_n;
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reg cas_r_n;
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reg we_r_n;
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reg [12:0] maddr_i;
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reg [12:0] maddr_r;
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@ -77,11 +74,11 @@ reg [1:0] refresh_request;
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reg refreshing;
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assign MADDR = (init_done) ? maddr_r : maddr_i;
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assign BA = ba_r;
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assign CS_n = (init_done) ? cs_n_r : cs_n_i;
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assign RAS_n = (init_done) ? ras_n_r : ras_n_i;
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assign CAS_n = (init_done) ? cas_n_r : cas_n_i;
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assign WE_n = (init_done) ? we_n_r : we_n_i;
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assign BA = ba_r;
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assign CS_n = (init_done) ? cs_r_n : cs_i_n;
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assign RAS_n = (init_done) ? ras_r_n : ras_i_n;
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assign CAS_n = (init_done) ? cas_r_n : cas_i_n;
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assign WE_n = (init_done) ? we_r_n : we_i_n;
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localparam init_cycle_precharge1 = 0,
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init_cycle_refresh1 = init_cycle_precharge1 + tRP,
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@ -92,10 +89,10 @@ localparam init_cycle_precharge1 = 0,
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always @(negedge CLK or negedge RESET_n) begin
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if (!RESET_n) begin
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init_state <= init_cycle_precharge1;
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init_done <= 0;
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maddr_i <= 'b0;
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cs_n_i <= 2'b00;
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init_state <= init_cycle_precharge1;
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init_done <= 0;
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maddr_i <= 13'b0;
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cs_i_n[1:0] <= 2'b00;
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end else begin
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// Ram Initialization //
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if (!init_done && configured) begin
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@ -126,7 +123,7 @@ always @(negedge CLK or negedge RESET_n) begin
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default:
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begin
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`initcmd(cmd_nop)
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cs_n_i <= 2'b00;
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cs_i_n[1:0] <= 2'b00;
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end
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endcase
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end
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@ -151,10 +148,11 @@ localparam access_cycle_start = 5'b00000,
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refresh_cycle_auto = refresh_cycle_pre+tRP,
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refresh_cycle_end = refresh_cycle_auto+tRFC;
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assign refreshreset = !refreshing & RESET_n;
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wire refreshreset = !refreshing & RESET_n;
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always @(posedge ECLK or negedge refreshreset) begin
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if (!refreshreset) begin
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refresh_timer <= 'h4;
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refresh_timer <= 4'h4;
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end else begin
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if (refresh_timer > 0) begin
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refresh_timer <= refresh_timer - 1;
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@ -181,38 +179,42 @@ always @(posedge CLK or negedge RESET_n)
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begin
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if (!RESET_n) begin
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`cmd(cmd_nop)
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maddr_r <= 0;
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ba_r <= 2'b0;
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CKE <= 0;
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dtack <= 0;
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refreshing <= 0;
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DQM <= 4'b1111;
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cs_n_r <= 2'b11;
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ram_state <= 0;
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maddr_r[12:0] <= 13'b0;
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ba_r[1:0] <= 2'b0;
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CKE <= 1'b0;
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dtack <= 1'b0;
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refreshing <= 1'b0;
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DQM_n[3:0] <= 4'b1111;
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cs_r_n[1:0] <= 2'b11;
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ram_state <= 1'b0;
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end else begin
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if (ram_state == 0) begin
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CKE <= 1;
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dtack <= 0;
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DQM <= 4'b1111;
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cs_n_r <= 2'b11;
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refreshing <= 0;
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CKE <= 1'b0;
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dtack <= 1'b0;
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DQM_n[3:0] <= 4'b1111;
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cs_r_n[1:0] <= 2'b11;
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refreshing <= 1'b0;
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if (init_done) begin
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// Refresh has the highest priority
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// If refresh_request active, go do a refresh
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if (refresh_request[1] == 1) begin
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`cmd(cmd_precharge)
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maddr_r[10] <= 1; // Precharge all banks
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cycle_type <= ram_cycle_refresh;
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ram_state[0] <= 1;
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cs_n_r <= 2'b00; // Refresh all modules
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refreshing <= 1;
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maddr_r[10] <= 1'b1; // Precharge all banks
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cycle_type <= ram_cycle_refresh;
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ram_state[0] <= 1'b1;
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cs_r_n[1:0] <= 2'b00; // Refresh all modules
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refreshing <= 1'b1;
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// If refresh_request not active and we're in a ram cycle, go do a ram access
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end else if (ram_cycle_sync[1] && !FCS_n) begin
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`cmd(cmd_active)
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cycle_type <= ram_cycle_access;
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ram_state[0] <= 1;
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maddr_r <= ADDR[23:11];
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ba_r <= ADDR[25:24];
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cs_n_r[1:0] <= {ADDR[26],~ADDR[26]};
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cycle_type <= ram_cycle_access;
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ram_state[0] <= 1'b1;
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maddr_r[12:0] <= ADDR[23:11];
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ba_r[1:0] <= ADDR[25:24];
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cs_r_n[1:0] <= {ADDR[26],~ADDR[26]};
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// No refresh needed at this time and no memory access, idle
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end else begin
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cs_n_r <= 2'b11;
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cs_r_n[1:0] <= 2'b11;
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`cmd(cmd_nop)
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end
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end
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@ -226,7 +228,7 @@ begin
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// Wait for tRCD and also wait until we see data strobes before committing writes
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access_cycle_wait: begin
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`cmd(cmd_nop)
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if (DS0 && DS1 && DS2 && DS3 && !RW_n || !DOE) begin // ! Is DOE needed here? no need to hold off on reads
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if (DS_n[3:0] == 4'b1111 && !RW || !DOE) begin // ! Is DOE needed here? no need to hold off on reads
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ram_state <= access_cycle_wait;
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end
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end
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@ -239,13 +241,13 @@ begin
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access_cycle_rw: begin
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dtack <= 1;
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maddr_r[12:0] <= {3'b000,ADDR[27], ADDR[10:2]};
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if (!RW_n) begin
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if (!RW) begin
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`cmd(cmd_write)
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DQM[3:0] <= {DS3, DS2, DS1, DS0};
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DQM_n[3:0] <= DS_n[3:0];
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end else begin
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`cmd(cmd_read)
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// Reads must return a full long regardless of DS (Zorro III Bus Specifications pg 3-3)
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DQM[3:0] <= 4'b0000;
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DQM_n[3:0] <= 4'b0000;
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end
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end
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@ -256,8 +258,8 @@ begin
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access_cycle_hold: begin
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dtack <= 0;
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`cmd(cmd_nop)
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if (!FCS_n && (!DS0 || !DS1 || !DS2 || !DS3)) begin
|
||||
//if (RW_n)
|
||||
if (!FCS_n && DS_n[3:0] != 4'b1111) begin
|
||||
//if (RW)
|
||||
CKE <= 0;
|
||||
ram_state <= access_cycle_hold;
|
||||
end else begin
|
||||
@ -297,7 +299,7 @@ end
|
||||
reg [3:0] dtack_delayed;
|
||||
always @(posedge CLK or negedge RESET_n) begin
|
||||
if (!RESET_n)
|
||||
dtack_delayed[3:0] <= 'b0;
|
||||
dtack_delayed[3:0] <= 4'b0;
|
||||
else
|
||||
dtack_delayed[3:0] <= {dtack_delayed[2:0], dtack};
|
||||
end
|
||||
|
||||
109
RTL/top.v
109
RTL/top.v
@ -5,7 +5,7 @@ module GottaGoFaZt3r(
|
||||
input CFGIN_n,
|
||||
input CLK,
|
||||
input DOE,
|
||||
input [3:0] DS,
|
||||
input [3:0] DS_n,
|
||||
input E,
|
||||
input [2:0] FC,
|
||||
input FCS_n,
|
||||
@ -24,68 +24,75 @@ module GottaGoFaZt3r(
|
||||
output BUFOE_n,
|
||||
output CAS_n,
|
||||
output CKE,
|
||||
output [1:0] CS,
|
||||
output [1:0] CS_n,
|
||||
output [1:0] BA,
|
||||
output [3:0] DQM,
|
||||
output [3:0] DQM_n,
|
||||
output [12:0] MA,
|
||||
output MEMCLK,
|
||||
output RAS_n,
|
||||
output WE_n
|
||||
);
|
||||
|
||||
assign MEMCLK = ~CLK;
|
||||
assign MEMCLK = ~CLK;
|
||||
|
||||
|
||||
|
||||
// Synchro
|
||||
reg [1:0] DS0_sync;
|
||||
reg [1:0] DS1_sync;
|
||||
reg [1:0] DS2_sync;
|
||||
reg [1:0] DS3_sync;
|
||||
// Synchronizers
|
||||
reg [1:0] DS0_n_sync;
|
||||
reg [1:0] DS1_n_sync;
|
||||
reg [1:0] DS2_n_sync;
|
||||
reg [1:0] DS3_n_sync;
|
||||
reg [1:0] FCS_n_sync;
|
||||
|
||||
always @(posedge CLK or negedge RST_n)
|
||||
begin
|
||||
if (!RST_n) begin
|
||||
DS0_sync[1:0] <= 2'b11;
|
||||
DS1_sync[1:0] <= 2'b11;
|
||||
DS2_sync[1:0] <= 2'b11;
|
||||
DS3_sync[1:0] <= 2'b11;
|
||||
DS0_n_sync[1:0] <= 2'b11;
|
||||
DS1_n_sync[1:0] <= 2'b11;
|
||||
DS2_n_sync[1:0] <= 2'b11;
|
||||
DS3_n_sync[1:0] <= 2'b11;
|
||||
FCS_n_sync[1:0] <= 2'b11;
|
||||
end else begin
|
||||
DS0_sync[1:0] <= {DS0_sync[0], DS[0]};
|
||||
DS1_sync[1:0] <= {DS1_sync[0], DS[1]};
|
||||
DS2_sync[1:0] <= {DS2_sync[0], DS[2]};
|
||||
DS3_sync[1:0] <= {DS3_sync[0], DS[3]};
|
||||
DS0_n_sync[1:0] <= {DS0_n_sync[0], DS_n[0]};
|
||||
DS1_n_sync[1:0] <= {DS1_n_sync[0], DS_n[1]};
|
||||
DS2_n_sync[1:0] <= {DS2_n_sync[0], DS_n[2]};
|
||||
DS3_n_sync[1:0] <= {DS3_n_sync[0], DS_n[3]};
|
||||
FCS_n_sync[1:0] <= {FCS_n_sync[0], FCS_n};
|
||||
end
|
||||
end
|
||||
|
||||
reg [27:8] ADDR;
|
||||
reg match;
|
||||
wire [3:0] addr_match;
|
||||
wire autoconfig_cfgout;
|
||||
wire configured;
|
||||
|
||||
always @(negedge FCS_n or negedge RST_n)
|
||||
begin
|
||||
if (!RST_n) begin
|
||||
ADDR <= 'b0;
|
||||
match <= 1'b0;
|
||||
end else begin
|
||||
ADDR[27:8] <= A[27:8];
|
||||
if (AD[31:28] == addr_match) begin
|
||||
match <= (configured || A[27:24] == 4'hF);
|
||||
end else begin
|
||||
match <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Autoconf
|
||||
wire [3:0] autoconfig_dout;
|
||||
wire autoconfig_cycle;
|
||||
//wire autoconfig_cfgout;
|
||||
wire autoconfig_cfgout;
|
||||
wire configured;
|
||||
|
||||
// addr_match comes from the autoconfig unit
|
||||
// At reset it is 4'hF to match autoconfig cycles
|
||||
// Autoconfig will then change addr_match to the new base address
|
||||
wire [3:0] addr_match;
|
||||
|
||||
// Latch address bits 27-8 on FCS_n asserted
|
||||
//
|
||||
// Also latch whether there's a match (rather than latching Address 31-28)
|
||||
// Doing things this way saves a bunch of space in the CPLD
|
||||
|
||||
reg [27:8] ADDR;
|
||||
reg match;
|
||||
|
||||
always @(negedge FCS_n or negedge RST_n)
|
||||
begin
|
||||
if (!RST_n) begin
|
||||
ADDR <= 20'b0;
|
||||
match <= 1'b0;
|
||||
end else begin
|
||||
ADDR[27:8] <= A[27:8];
|
||||
if (AD[31:28] == addr_match) begin
|
||||
// Match 8 address bits when unconfigured (8'hFF) but only 4 when configured (256MB Blocks)
|
||||
match <= (configured || A[27:24] == 4'hF);
|
||||
end else begin
|
||||
match <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
Autoconfig AUTOCONFIG (
|
||||
.match (match),
|
||||
@ -94,7 +101,7 @@ Autoconfig AUTOCONFIG (
|
||||
.FCS_n (FCS_n_sync[1]),
|
||||
.CLK (CLK),
|
||||
.READ (READ),
|
||||
.DS_n (DS3_sync[1]),
|
||||
.DS_n (DS3_n_sync[1]),
|
||||
.CFGIN_n (CFGIN_n),
|
||||
.DIN (AD[31:28]),
|
||||
.FC (FC[2:0]),
|
||||
@ -109,30 +116,29 @@ Autoconfig AUTOCONFIG (
|
||||
|
||||
SDRAM SDRAM (
|
||||
.ADDR ({ADDR[27:8], A[7:2]}),
|
||||
.DS0 (DS0_sync[1]),
|
||||
.DS1 (DS1_sync[1]),
|
||||
.DS2 (DS2_sync[1]),
|
||||
.DS3 (DS3_sync[1]),
|
||||
.DS_n ({DS3_n_sync[1], DS2_n_sync[1], DS1_n_sync[1], DS0_n_sync[1]}),
|
||||
.DOE (DOE),
|
||||
.FCS_n (FCS_n_sync[1]),
|
||||
.ram_cycle (ram_cycle),
|
||||
.RESET_n (RST_n),
|
||||
.RW_n (READ),
|
||||
.RW (READ),
|
||||
.CLK (CLK),
|
||||
.ECLK (E),
|
||||
.BA (BA),
|
||||
.MADDR (MA),
|
||||
.CAS_n (CAS_n),
|
||||
.RAS_n (RAS_n),
|
||||
.CS_n (CS),
|
||||
.CS_n (CS_n),
|
||||
.WE_n (WE_n),
|
||||
.CKE (CKE),
|
||||
.DQM (DQM),
|
||||
.DQM_n (DQM_n),
|
||||
.DTACK_EN (ram_dtack),
|
||||
.MTCR_n (MTCR_n),
|
||||
.configured (configured)
|
||||
);
|
||||
|
||||
// Latch DTACK on strobe from SDRAM unit
|
||||
// Clear on cycle end
|
||||
FDCP FDCP_inst (
|
||||
.CLR (FCS_n),
|
||||
.PRE (1'b0),
|
||||
@ -140,13 +146,14 @@ FDCP FDCP_inst (
|
||||
.C (ram_dtack),
|
||||
.Q (dtack_latch)
|
||||
);
|
||||
|
||||
reg bursting;
|
||||
|
||||
always @(negedge MTCR_n or posedge FCS_n) begin
|
||||
if (FCS_n)
|
||||
bursting <= 0;
|
||||
bursting <= 1'b0;
|
||||
else
|
||||
bursting <= 1;
|
||||
bursting <= 1'b1;
|
||||
end
|
||||
|
||||
assign AD[31:28] = (autoconfig_cycle && BERR_n && DOE && READ) ? autoconfig_dout[3:0] : 4'bZ;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user