diff --git a/Binary/GottaGoFaZt3r.jed b/Binary/GottaGoFaZt3r.jed
index 1a8e12c..2004616 100644
--- a/Binary/GottaGoFaZt3r.jed
+++ b/Binary/GottaGoFaZt3r.jed
@@ -1,5 +1,5 @@
 Programmer Jedec Bit Map
-Date Extracted: Fri Apr 22 17:47:25 2022
+Date Extracted: Sat Apr 23 14:44:35 2022
 
 QF93312*
 QP100*
@@ -243,12 +243,12 @@ L0008592 000000 000000 000000 000000 000000 000000 000000 000000*
 L0008640 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0008704 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0008768 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
-L0008832 00000000 00000000 00000000 00000000 00000000 00000000 00000100 00000000*
+L0008832 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0008896 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
 L0008960 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000*
 L0009024 00000000 00000000 00000000 00000000 00000000 00000000 10000000 00000000*
 L0009088 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
-L0009152 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0009152 00000000 00000000 00000000 00000000 00000000 00000000 00000100 00000000*
 L0009216 000000 000000 000000 000000 000000 000000 000000 000000*
 L0009264 000000 000000 000000 000000 000000 000000 000000 000000*
 L0009312 000000 000000 000000 000000 000000 000000 000000 000000*
@@ -393,13 +393,13 @@ L0017232 000000 000000 000000 000000 000000 000000 000000 000000*
 L0017280 00000000 00000000 00000000 00000000 00000001 00000000 00000011 00000000*
 L0017344 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000001*
 L0017408 00000000 00000000 00000000 00000000 00000010 00000001 00000010 00000000*
-L0017472 00000000 00000000 00000000 00000000 00000011 00000000 00000001 00000000*
+L0017472 00000000 00000000 00000000 00000000 00000011 00000000 00000101 00000000*
 L0017536 00000000 00000000 00000000 00000001 00000010 00000001 00000000 00000000*
 L0017600 00000000 00000000 00000000 00000011 00000010 00000001 00000000 00010000*
 L0017664 00000000 00000000 00000000 00000001 00000011 00000000 00000010 00000001*
 L0017728 00000000 00000000 00000000 00000001 00000000 00000000 00000001 00010011*
 L0017792 00000000 00000001 00000000 00000001 00000001 00000001 10000000 00000000*
-L0017856 000000 000000 000000 000000 000000 000000 000001 000000*
+L0017856 000000 000000 000000 000000 000000 000000 000000 000000*
 L0017904 000000 000000 000000 000000 000000 000000 000000 000000*
 L0017952 000000 000000 000000 000000 000000 000000 000000 000000*
 L0018000 000000 000000 000000 000000 000000 000000 000000 000000*
@@ -458,8 +458,8 @@ L0020992 00000000 00000000 00000000 00000000 00001000 00000000 00000000 00000000
 L0021056 00100000 00000000 00000000 10000000 00000000 00000001 00000000 00000000*
 L0021120 00000000 00000000 00000000 00100000 00000000 00000000 00000000 00000000*
 L0021184 00000000 00000000 00000000 00000000 00000000 00000000 10000001 00000001*
-L0021248 00000000 00000000 00000000 00000001 00000000 00000001 00000100 00000001*
-L0021312 000000 000000 000000 000000 000000 000000 000000 000000*
+L0021248 00000000 00000000 00000000 00000001 00000000 00000001 00000000 00000001*
+L0021312 000000 000000 000000 000000 000000 000000 000001 000000*
 L0021360 000000 000000 000000 000000 000000 000000 000000 000000*
 L0021408 000000 001000 000000 001100 000000 000000 000000 000000*
 L0021456 000000 000000 000000 000100 000000 000000 000000 000000*
diff --git a/RTL/GottaGoFaZt3r.ucf b/RTL/GottaGoFaZt3r.ucf
index e0e09e0..f81d495 100644
--- a/RTL/GottaGoFaZt3r.ucf
+++ b/RTL/GottaGoFaZt3r.ucf
@@ -39,17 +39,17 @@ NET "CFGOUT_n" LOC = "P30"  ;
 NET "CKE"     LOC = "P61"  ; 
 NET "CLK"     LOC = "P27"  ; 
 NET "CLK"     BUFG = "CLK" ; 
-NET "CS<0>"   LOC = "P35"  ; 
-NET "CS<1>"   LOC = "P60"  ; 
+NET "CS_n<0>"   LOC = "P35"  ; 
+NET "CS_n<1>"   LOC = "P60"  ; 
 NET "DOE"     LOC = "P74"  ; 
-NET "DQM<0>"  LOC = "P68"  ; 
-NET "DQM<1>"  LOC = "P66"  ; 
-NET "DQM<2>"  LOC = "P36"  ; 
-NET "DQM<3>"  LOC = "P37"  ; 
-NET "DS<0>"    LOC = "P2"  ; 
-NET "DS<1>"    LOC = "P70"  ; 
-NET "DS<2>"    LOC = "P87"  ; 
-NET "DS<3>"    LOC = "P86"  ; 
+NET "DQM_n<0>"  LOC = "P68"  ; 
+NET "DQM_n<1>"  LOC = "P66"  ; 
+NET "DQM_n<2>"  LOC = "P36"  ; 
+NET "DQM_n<3>"  LOC = "P37"  ; 
+NET "DS_n<0>"    LOC = "P2"  ; 
+NET "DS_n<1>"    LOC = "P70"  ; 
+NET "DS_n<2>"    LOC = "P87"  ; 
+NET "DS_n<3>"    LOC = "P86"  ; 
 NET "DTACK_n"  LOC = "P90"  ; 
 NET "E"       LOC = "P3"  ; 
 NET "FC<0>"   LOC = "P18"  ; 
diff --git a/RTL/autoconfig.v b/RTL/autoconfig.v
index bf33c75..21a365f 100644
--- a/RTL/autoconfig.v
+++ b/RTL/autoconfig.v
@@ -23,15 +23,15 @@ module Autoconfig (
 `define SERIAL 32'd421
 `define PRODID 8'h72
 `endif
-reg done = 0;
 
 localparam [15:0] mfg_id  = 16'h07DB;
 localparam [7:0]  prod_id = `PRODID;
 localparam [31:0] serial  = `SERIAL;
 
-reg shutup;
+reg done = 0;
+reg shutup = 0;
 
-assign validspace = FC[1] ^ FC[0]; // 1 when FC indicates user/supervisor data/program space
+wire validspace = FC[1] ^ FC[0]; // 1 when FC indicates user/supervisor data/program space
 
 reg [1:0] vs;
 always @(posedge CLK) begin
@@ -52,40 +52,41 @@ end
 always @(posedge CLK or negedge RESET_n)
 begin
   if (!RESET_n) begin
-    DOUT       <= 4'b0;
-    configured <= 1'b0;
-    shutup     <= 1'b0;
-    addr_match <= 4'b1111;
+    DOUT[3:0]       <= 4'b0;
+    configured      <= 1'b0;
+    shutup          <= 1'b0;
+    addr_match[3:0] <= 4'b1111;
   end else if (autoconfig_cycle && !FCS_n) begin
     if (READ) begin
       case ({ADDRL[5:0],ADDRL[6]})
-        7'h00:   DOUT <= 4'b1010;        // Type: Zorro III Memory
-        7'h01:   DOUT <= 4'b0100;        // 256 MB
-        7'h02:   DOUT <= ~prod_id[7:4];  // Product number
-        7'h03:   DOUT <= ~prod_id[3:0];  // Product number
-        7'h04:   DOUT <= ~4'b1011;       // Memory device, Size Extension, Zorro III
-        7'h05:   DOUT <= ~4'b0001;       // Automatically sized by OS
-        7'h08:   DOUT <= ~mfg_id[15:12]; // Manufacturer ID
-        7'h09:   DOUT <= ~mfg_id[11:8];  // Manufacturer ID
-        7'h0A:   DOUT <= ~mfg_id[7:4];   // Manufacturer ID
-        7'h0B:   DOUT <= ~mfg_id[3:0];   // Manufacturer ID
-        7'h0C:   DOUT <= ~serial[31:28]; // Serial number
-        7'h0D:   DOUT <= ~serial[27:24]; // Serial number
-        7'h0E:   DOUT <= ~serial[23:20]; // Serial number
-        7'h0F:   DOUT <= ~serial[19:16]; // Serial number
-        7'h10:   DOUT <= ~serial[15:12]; // Serial number
-        7'h11:   DOUT <= ~serial[11:8];  // Serial number
-        7'h12:   DOUT <= ~serial[7:4];   // Serial number
-        7'h13:   DOUT <= ~serial[3:0];   // Serial number
-        7'h20:   DOUT <= 4'b0;
-        7'h21:   DOUT <= 4'b0;
-        default: DOUT <= 4'hF;
+        7'h00:   DOUT[3:0] <= 4'b1010;        // Type: Zorro III Memory
+        7'h01:   DOUT[3:0] <= 4'b0100;        // 256 MB
+        7'h02:   DOUT[3:0] <= ~prod_id[7:4];  // Product number
+        7'h03:   DOUT[3:0] <= ~prod_id[3:0];  // Product number
+        7'h04:   DOUT[3:0] <= ~4'b1011;       // Memory device, Size Extension, Zorro III
+        7'h05:   DOUT[3:0] <= ~4'b0001;       // Automatically sized by OS
+        7'h08:   DOUT[3:0] <= ~mfg_id[15:12]; // Manufacturer ID
+        7'h09:   DOUT[3:0] <= ~mfg_id[11:8];  // Manufacturer ID
+        7'h0A:   DOUT[3:0] <= ~mfg_id[7:4];   // Manufacturer ID
+        7'h0B:   DOUT[3:0] <= ~mfg_id[3:0];   // Manufacturer ID
+        7'h0C:   DOUT[3:0] <= ~serial[31:28]; // Serial number
+        7'h0D:   DOUT[3:0] <= ~serial[27:24]; // Serial number
+        7'h0E:   DOUT[3:0] <= ~serial[23:20]; // Serial number
+        7'h0F:   DOUT[3:0] <= ~serial[19:16]; // Serial number
+        7'h10:   DOUT[3:0] <= ~serial[15:12]; // Serial number
+        7'h11:   DOUT[3:0] <= ~serial[11:8];  // Serial number
+        7'h12:   DOUT[3:0] <= ~serial[7:4];   // Serial number
+        7'h13:   DOUT[3:0] <= ~serial[3:0];   // Serial number
+        7'h20:   DOUT[3:0] <= 4'b0;
+        7'h21:   DOUT[3:0] <= 4'b0;
+        default: DOUT[3:0] <= 4'hF;
       endcase
     end else begin
       if (ADDRL[5:0] == 6'h13 && !DS_n) begin
-        //configured <= 1;
+        // Shutup
         shutup <= 1;
       end else if (ADDRL[5:0] == 6'h11 && !DS_n) begin
+        // Write base address
         addr_match <= DIN[3:0];
         configured <= 1;
       end
diff --git a/RTL/sdram.v b/RTL/sdram.v
index a0cee2b..885bf37 100644
--- a/RTL/sdram.v
+++ b/RTL/sdram.v
@@ -2,15 +2,12 @@
 
 module SDRAM(
     input [27:2] ADDR,
-    input DS0,
-    input DS1,
-    input DS2,
-    input DS3,
+    input [3:0] DS_n,
     input DOE,
     input FCS_n,
     input ram_cycle,
     input RESET_n,
-    input RW_n,
+    input RW,
     input CLK,
     input ECLK,
     input configured,
@@ -22,7 +19,7 @@ module SDRAM(
     output [1:0] CS_n,
     output WE_n,
     output reg CKE,
-    output reg [3:0] DQM,
+    output reg [3:0] DQM_n,
     output DTACK_EN
     );
 
@@ -32,10 +29,10 @@ localparam tRFC = 4;
 localparam CAS_LATENCY = 3'd2;
 
 `define initcmd(ARG) \
-{ras_n_i, cas_n_i, we_n_i} <= ARG;
+{ras_i_n, cas_i_n, we_i_n} <= ARG;
 
 `define cmd(ARG) \
-{ras_n_r, cas_n_r, we_n_r} <= ARG;
+{ras_r_n, cas_r_n, we_r_n} <= ARG;
 
 // RAS CAS WE
 localparam cmd_nop             = 3'b111,
@@ -56,14 +53,14 @@ localparam mode_register = {
   3'b0         // M2-0   - Burst length
 };
 
-reg [1:0] cs_n_i;
-reg ras_n_i;
-reg cas_n_i;
-reg we_n_i;
-reg [1:0] cs_n_r;
-reg ras_n_r;
-reg cas_n_r;
-reg we_n_r;
+reg [1:0] cs_i_n;
+reg ras_i_n;
+reg cas_i_n;
+reg we_i_n;
+reg [1:0] cs_r_n;
+reg ras_r_n;
+reg cas_r_n;
+reg we_r_n;
 
 reg [12:0] maddr_i;
 reg [12:0] maddr_r;
@@ -77,11 +74,11 @@ reg [1:0] refresh_request;
 reg refreshing;
 
 assign MADDR = (init_done) ? maddr_r : maddr_i;
-assign BA    = ba_r;
-assign CS_n   = (init_done) ? cs_n_r : cs_n_i;
-assign RAS_n  = (init_done) ? ras_n_r : ras_n_i;
-assign CAS_n  = (init_done) ? cas_n_r : cas_n_i;
-assign WE_n   = (init_done) ? we_n_r : we_n_i;
+assign BA     = ba_r;
+assign CS_n   = (init_done) ? cs_r_n : cs_i_n;
+assign RAS_n  = (init_done) ? ras_r_n : ras_i_n;
+assign CAS_n  = (init_done) ? cas_r_n : cas_i_n;
+assign WE_n   = (init_done) ? we_r_n : we_i_n;
 
 localparam init_cycle_precharge1 = 0,
            init_cycle_refresh1   = init_cycle_precharge1 + tRP,
@@ -92,10 +89,10 @@ localparam init_cycle_precharge1 = 0,
 
 always @(negedge CLK or negedge RESET_n) begin
   if (!RESET_n) begin
-    init_state <= init_cycle_precharge1;
-    init_done  <= 0;
-    maddr_i    <= 'b0;
-    cs_n_i      <= 2'b00;
+    init_state  <= init_cycle_precharge1;
+    init_done   <= 0;
+    maddr_i     <= 13'b0;
+    cs_i_n[1:0] <= 2'b00;
   end else begin
      // Ram Initialization //
       if (!init_done && configured) begin
@@ -126,7 +123,7 @@ always @(negedge CLK or negedge RESET_n) begin
           default:
             begin
               `initcmd(cmd_nop)
-              cs_n_i <= 2'b00;
+              cs_i_n[1:0] <= 2'b00;
             end
         endcase
       end
@@ -151,10 +148,11 @@ localparam access_cycle_start     = 5'b00000,
            refresh_cycle_auto     = refresh_cycle_pre+tRP,
            refresh_cycle_end      = refresh_cycle_auto+tRFC;
 
-assign refreshreset = !refreshing & RESET_n;
+wire refreshreset = !refreshing & RESET_n;
+
 always @(posedge ECLK or negedge refreshreset) begin
   if (!refreshreset) begin
-    refresh_timer <= 'h4;
+    refresh_timer <= 4'h4;
   end else begin
     if (refresh_timer > 0) begin
       refresh_timer <= refresh_timer - 1;
@@ -181,38 +179,42 @@ always @(posedge CLK or negedge RESET_n)
 begin
   if (!RESET_n) begin
     `cmd(cmd_nop)
-    maddr_r         <= 0;
-    ba_r            <= 2'b0;
-    CKE             <= 0;
-    dtack           <= 0;
-    refreshing      <= 0;
-    DQM             <= 4'b1111;
-    cs_n_r          <= 2'b11;
-    ram_state       <= 0;
+    maddr_r[12:0]   <= 13'b0;
+    ba_r[1:0]       <= 2'b0;
+    CKE             <= 1'b0;
+    dtack           <= 1'b0;
+    refreshing      <= 1'b0;
+    DQM_n[3:0]      <= 4'b1111;
+    cs_r_n[1:0]     <= 2'b11;
+    ram_state       <= 1'b0;
   end else begin
     if (ram_state == 0) begin
-      CKE        <= 1;
-      dtack      <= 0;
-      DQM        <= 4'b1111;
-      cs_n_r     <= 2'b11;
-      refreshing <= 0;
+      CKE         <= 1'b0;
+      dtack       <= 1'b0;
+      DQM_n[3:0]  <= 4'b1111;
+      cs_r_n[1:0] <= 2'b11;
+      refreshing  <= 1'b0;
       if (init_done) begin
+        // Refresh has the highest priority
+        // If refresh_request active, go do a refresh
         if (refresh_request[1] == 1) begin
           `cmd(cmd_precharge)
-          maddr_r[10]    <= 1; // Precharge all banks
-          cycle_type     <= ram_cycle_refresh;
-          ram_state[0]   <= 1;
-          cs_n_r         <= 2'b00; // Refresh all modules
-          refreshing     <= 1;
+          maddr_r[10]  <= 1'b1; // Precharge all banks
+          cycle_type   <= ram_cycle_refresh;
+          ram_state[0] <= 1'b1;
+          cs_r_n[1:0]  <= 2'b00; // Refresh all modules
+          refreshing   <= 1'b1;
+        // If refresh_request not active and we're in a ram cycle, go do a ram access
         end else if (ram_cycle_sync[1] && !FCS_n) begin
           `cmd(cmd_active)
-          cycle_type     <= ram_cycle_access;
-          ram_state[0]   <= 1;
-          maddr_r        <= ADDR[23:11];
-          ba_r           <= ADDR[25:24];
-          cs_n_r[1:0]    <= {ADDR[26],~ADDR[26]};
+          cycle_type    <= ram_cycle_access;
+          ram_state[0]  <= 1'b1;
+          maddr_r[12:0] <= ADDR[23:11];
+          ba_r[1:0]     <= ADDR[25:24];
+          cs_r_n[1:0]   <= {ADDR[26],~ADDR[26]};
+        // No refresh needed at this time and no memory access, idle
         end else begin
-          cs_n_r      <= 2'b11;
+          cs_r_n[1:0]    <= 2'b11;
           `cmd(cmd_nop)
         end
       end
@@ -226,7 +228,7 @@ begin
           // Wait for tRCD and also wait until we see data strobes before committing writes
           access_cycle_wait: begin
             `cmd(cmd_nop)
-            if (DS0 && DS1 && DS2 && DS3 && !RW_n || !DOE) begin // ! Is DOE needed here? no need to hold off on reads 
+            if (DS_n[3:0] == 4'b1111 && !RW || !DOE) begin // ! Is DOE needed here? no need to hold off on reads 
               ram_state <= access_cycle_wait;
             end
           end
@@ -239,13 +241,13 @@ begin
           access_cycle_rw: begin
             dtack <= 1;
             maddr_r[12:0] <= {3'b000,ADDR[27], ADDR[10:2]};
-            if (!RW_n) begin
+            if (!RW) begin
               `cmd(cmd_write)
-              DQM[3:0] <= {DS3, DS2, DS1, DS0};
+              DQM_n[3:0] <= DS_n[3:0];
             end else begin
               `cmd(cmd_read)
               // Reads must return a full long regardless of DS (Zorro III Bus Specifications pg 3-3)
-              DQM[3:0] <= 4'b0000;
+              DQM_n[3:0] <= 4'b0000;
             end
           end
 
@@ -256,8 +258,8 @@ begin
           access_cycle_hold: begin
             dtack <= 0;
             `cmd(cmd_nop)
-            if (!FCS_n && (!DS0 || !DS1 || !DS2 || !DS3)) begin
-              //if (RW_n)
+            if (!FCS_n && DS_n[3:0] != 4'b1111) begin
+              //if (RW)
                 CKE <= 0;
               ram_state <= access_cycle_hold;
             end else begin
@@ -297,7 +299,7 @@ end
 reg [3:0] dtack_delayed;
 always @(posedge CLK or negedge RESET_n) begin
   if (!RESET_n)
-    dtack_delayed[3:0] <= 'b0;
+    dtack_delayed[3:0] <= 4'b0;
   else
     dtack_delayed[3:0] <= {dtack_delayed[2:0], dtack};
 end
diff --git a/RTL/top.v b/RTL/top.v
index 596701e..948a212 100644
--- a/RTL/top.v
+++ b/RTL/top.v
@@ -5,7 +5,7 @@ module GottaGoFaZt3r(
         input CFGIN_n,
         input CLK,
         input DOE,
-        input [3:0] DS,
+        input [3:0] DS_n,
         input E,
         input [2:0] FC,
         input FCS_n,
@@ -24,68 +24,75 @@ module GottaGoFaZt3r(
         output BUFOE_n,
         output CAS_n,
         output CKE,
-        output [1:0] CS,
+        output [1:0] CS_n,
         output [1:0] BA,
-        output [3:0] DQM,
+        output [3:0] DQM_n,
         output [12:0] MA,
         output MEMCLK,
         output RAS_n,
         output WE_n
     );
 
-assign MEMCLK = ~CLK;
+assign MEMCLK = ~CLK; 
 
-
-
-// Synchro
-reg [1:0] DS0_sync;
-reg [1:0] DS1_sync;
-reg [1:0] DS2_sync;
-reg [1:0] DS3_sync;
+// Synchronizers
+reg [1:0] DS0_n_sync;
+reg [1:0] DS1_n_sync;
+reg [1:0] DS2_n_sync;
+reg [1:0] DS3_n_sync;
 reg [1:0] FCS_n_sync;
 
 always @(posedge CLK or negedge RST_n)
 begin
   if (!RST_n) begin
-    DS0_sync[1:0]  <= 2'b11;
-    DS1_sync[1:0]  <= 2'b11;
-    DS2_sync[1:0]  <= 2'b11;
-    DS3_sync[1:0]  <= 2'b11;
+    DS0_n_sync[1:0] <= 2'b11;
+    DS1_n_sync[1:0] <= 2'b11;
+    DS2_n_sync[1:0] <= 2'b11;
+    DS3_n_sync[1:0] <= 2'b11;
     FCS_n_sync[1:0] <= 2'b11;
   end else begin
-    DS0_sync[1:0]  <= {DS0_sync[0], DS[0]};
-    DS1_sync[1:0]  <= {DS1_sync[0], DS[1]};
-    DS2_sync[1:0]  <= {DS2_sync[0], DS[2]};
-    DS3_sync[1:0]  <= {DS3_sync[0], DS[3]};
+    DS0_n_sync[1:0] <= {DS0_n_sync[0], DS_n[0]};
+    DS1_n_sync[1:0] <= {DS1_n_sync[0], DS_n[1]};
+    DS2_n_sync[1:0] <= {DS2_n_sync[0], DS_n[2]};
+    DS3_n_sync[1:0] <= {DS3_n_sync[0], DS_n[3]};
     FCS_n_sync[1:0] <= {FCS_n_sync[0], FCS_n};
   end
 end
 
-reg [27:8] ADDR;
-reg match;
-wire [3:0] addr_match;
-wire autoconfig_cfgout;
-wire configured;
-
-always @(negedge FCS_n or negedge RST_n)
-begin
-  if (!RST_n) begin
-    ADDR <= 'b0;
-    match <= 1'b0;
-  end else begin
-    ADDR[27:8] <= A[27:8];
-    if (AD[31:28] == addr_match) begin
-      match <= (configured || A[27:24] == 4'hF);
-    end else begin
-      match <= 0;
-    end
-  end
-end
-
 // Autoconf
 wire [3:0] autoconfig_dout;
 wire autoconfig_cycle;
-//wire autoconfig_cfgout;
+wire autoconfig_cfgout;
+wire configured;
+
+// addr_match comes from the autoconfig unit
+// At reset it is 4'hF to match autoconfig cycles
+// Autoconfig will then change addr_match to the new base address
+wire [3:0] addr_match;
+
+// Latch address bits 27-8 on FCS_n asserted
+// 
+// Also latch whether there's a match (rather than latching Address 31-28) 
+// Doing things this way saves a bunch of space in the CPLD
+
+reg [27:8] ADDR;
+reg match;
+
+always @(negedge FCS_n or negedge RST_n)
+begin
+  if (!RST_n) begin
+    ADDR  <= 20'b0;
+    match <= 1'b0;
+  end else begin
+    ADDR[27:8] <= A[27:8];
+    if (AD[31:28] == addr_match) begin
+      // Match 8 address bits when unconfigured (8'hFF) but only 4 when configured (256MB Blocks)
+      match <= (configured || A[27:24] == 4'hF);
+    end else begin
+      match <= 1'b0;
+    end
+  end
+end
 
 Autoconfig AUTOCONFIG (
   .match (match),
@@ -94,7 +101,7 @@ Autoconfig AUTOCONFIG (
   .FCS_n (FCS_n_sync[1]),
   .CLK (CLK),
   .READ (READ),
-  .DS_n (DS3_sync[1]),
+  .DS_n (DS3_n_sync[1]),
   .CFGIN_n (CFGIN_n),
   .DIN (AD[31:28]),
   .FC (FC[2:0]),
@@ -109,30 +116,29 @@ Autoconfig AUTOCONFIG (
 
 SDRAM SDRAM (
   .ADDR ({ADDR[27:8], A[7:2]}),
-  .DS0 (DS0_sync[1]),
-  .DS1 (DS1_sync[1]),
-  .DS2 (DS2_sync[1]),
-  .DS3 (DS3_sync[1]),
+  .DS_n ({DS3_n_sync[1], DS2_n_sync[1], DS1_n_sync[1], DS0_n_sync[1]}),
   .DOE (DOE),
   .FCS_n (FCS_n_sync[1]),
   .ram_cycle (ram_cycle),
   .RESET_n (RST_n),
-  .RW_n (READ),
+  .RW (READ),
   .CLK (CLK),
   .ECLK (E),
   .BA (BA),
   .MADDR (MA),
   .CAS_n (CAS_n),
   .RAS_n (RAS_n),
-  .CS_n (CS),
+  .CS_n (CS_n),
   .WE_n (WE_n),
   .CKE (CKE),
-  .DQM (DQM),
+  .DQM_n (DQM_n),
   .DTACK_EN (ram_dtack),
   .MTCR_n (MTCR_n),
   .configured (configured)
 );
 
+// Latch DTACK on strobe from SDRAM unit
+// Clear on cycle end
 FDCP FDCP_inst (
   .CLR (FCS_n),
   .PRE (1'b0),
@@ -140,13 +146,14 @@ FDCP FDCP_inst (
   .C (ram_dtack),
   .Q (dtack_latch)
 );
+
 reg bursting;
 
 always @(negedge MTCR_n or posedge FCS_n) begin
   if (FCS_n)
-    bursting <= 0;
+    bursting <= 1'b0;
   else
-    bursting <= 1;
+    bursting <= 1'b1;
 end
 
 assign AD[31:28] = (autoconfig_cycle && BERR_n && DOE && READ) ? autoconfig_dout[3:0] : 4'bZ;
