A few cards have shipped with U303 labeled as -02 so uprev to -02.
This way any actual changes in the future will become -03 and can
be correctly identified.
This change is almost cosmetical because the time spent on reading
the ROM is not significant, and ROM access only happens during boot
time.
This will now require a 120ns ROM instead of a 400ns ROM, which is
still about 3x slower than the 45ns W27C512-45Z we've been using.
* The original GAL code incorporates a latch to generate the signal BDTACK
using EDTACK. This is necessary because EDTACK may be too short to be
utilized directly in a synchronous flip-flop. Such a design choice is
common in asynchronous circuits or GALs, particularly when only D
flip-flops with a single clock input per chip are available, enabling
the extension of a signal to the next clock.
* Subsequently, the clock-synchronous signal DTSYNC is derived from
BDTACK by configuring the output as a D flip-flop (using x.D). This
configuration ensures that the original EDTACK signal is synchronized
with a 25 MHz clock. This approach is a standard procedure in such
designs.
* However, an interesting observation is that DTSYNC is utilized once
again as an input for another D flip-flop to generate the
clock-synchronous STERM signal (using .D). Unfortunately, this
arrangement introduces a delay of two clocks in the generation of
STERM. This delay occurs because STERM can only change its state one
clock cycle after DTSYNC. During the first clock cycle when DTSYNC
switches, its output signal has not yet reached the input of the STERM
flip-flop. It arrives a few nanoseconds later, which is too late for
the current clock cycle.
Based on the available Zorro III timing documentation, no specific timing
requirements were found that would justify the described method. In a
test scenario, the term for STERM was directly connected to BDTACK,
resulting in a stable outcome.
This configuration optimizes the system by saving one clock per DMA
transfer, resulting in a greatly improved disk speed of approximately
5.8MB/sec.
Found by dorken @ a1k.org
Turns out it is not required to use a pin for SLAVE.OE generation,
as only one term is used. That lets us reuse Pin 21 for something
else, i.e. the Zorro SHUTUP function.
If the 1GB Zorro III memory range is completely filled up (for
example with two 512MB memory cards), there is no more space for
an A4091. This leads to other cards (even Zorro II I/O cards) to
not be configured anymore if they are in the slot behind the
problematic board, as Autoconfig is blocked at this point.
This happens because CFGOUT is never activated and so the next
Zorro card never becomes active.
Found by dorken @ a1k.org
With the current JED files it should be fine to use all Atmel files
in an A4091. YMMV, but even Chris' picky Amiga 3000D was happy, and
that is quite something.
The name A3090 is sometimes used, and sometimes A4091 is used.
A3090 is the old name of the A4091 board, so rename all occurences
to A4091 for consistency.
In order to track versioning of individual JED files better,
add a better time stamp to each of them:
- If a JED files is checked into git already and no changes
to the file occured, use the timestamp of the last change
to this file. (Default)
- If a JED files is checked into git already and changes to
the file occured, use the timestamp of the file's last
modification.
- If a JED files is NOT checked into git already, also use
the timestamp of the file's last modification.
In addition, recalculate the file checksum (not the same as
the data checksum) after this change, just in case.
Atmel ATF22V10 GALs have pin-keeper circuits that will cause I/Os
to be held either high or low (but not float) when disabled. This
feature consumes extra power, which causes problems with MTCR and
DOE on U306 because there are 4 other GAL inputs hanging off the
output. Thus, they don't securely go to 0V / 5V but get stuck
around 1-2V. Enable MTCR output to actively drive the signal. This
fixes half of the problem.
Alternatively R109E and R109H can be changed from 1kOhm to 560Ohm
to improve the signals.
Found by dorken @ A1K.org
This enables the Zorro III Early Byte-Lane option, which results in an
overall speed increase of about 10% on the A4091.
From the Zorro III Bus Timing Addendum
2.4 Early Byte-Lane Option
There is now an optional early byte lane mode for full cycles. A bus
master can, optionally, drive /DS3-/DS0 according to normal address time
signal timing. Slaves that don't support this mode see /DSN at the
normal data-time, qualified by DOE. Slaves that do support this mode can
latch /DSN on the falling edge of /FCS. If at least one strobe is valid,
the slave gets a valid early byte-lane enable, and may use /DSn during
data time for write data latching. If none are valid, it will be
necessary to use /DSn at data time for sizing information.
Found by dorken @ a1k
Drop the old script. This creates identical files except for time stamps
and serial numbers (previous files were created with WinCupl instead of
the command line tool)
U305 is compiled with higher optimization as requested in the source (and
changes therefore)
