mirror of
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A4091 PALs dualfix
Source: Dave Haynie Files
This commit is contained in:
Stefan Reinauer
parent
d4e06c2b5f
commit
062cde5ddd
@ -1,16 +1,16 @@
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PARTNO U205 ;
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NAME U205 ;
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DATE July 8, 1992 ;
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REV 0 ;
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DATE April 1, 1993 ;
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REV 5 ;
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DESIGNER Dave Haynie ;
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COMPANY Commodore ;
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ASSEMBLY A3090 ;
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ASSEMBLY A4091 ;
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LOCATION West Chester ;
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DEVICE p22v10 ;
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DEVICE g22v10 ;
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/************************************************************************/
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/* */
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/* A3090 Buffer and termination control. */
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/* A4091 Buffer and termination control. */
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/* */
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/* This device manages data buffer direction, enable, and latch */
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/* functions, address buffer enable, and slave cycle termination. */
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@ -20,7 +20,7 @@
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/* DEVICE DATA: */
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/* */
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/* Device: 22V10-15 */
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/* Clock: CLK (33MHz) */
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/* Clock: CLK (25MHz) */
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/* Unused: 16(I/O) */
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/* */
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/************************************************************************/
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@ -28,31 +28,38 @@
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/* REVISION HISTORY: */
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/* */
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/* DBH Jul 8: Original version. */
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/* */
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/* DBH Oct 26: Extended data latching function. */
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/* DBH Nov 2: Modified DTACK again for fast SCSI slave cycle */
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/* termination. */
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/* DBH Nov 19: Changed DBOE for self-reference support. */
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/* DBH Mar 30: Added NOZ3 term for quick Zorro III disconnect, */
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/* to eliminate the multiple A4091 problem. */
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/* DBH Apr 1: Some more NOZ3-related tweaks. */
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/************************************************************************/
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/** INPUTS: **/
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PIN 1 = CLK ; /* 33MHz system clock. */
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PIN 1 = CLK ; /* 25MHz system clock. */
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PIN 2 = !SLAVE ; /* Board select. */
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PIN 3 = !MYBUS ; /* The A3090 has the bus. */
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PIN 3 = !MYBUS ; /* The A4091 has the bus. */
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PIN 4 = DOE ; /* Data phase on Zorro III. */
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PIN 5 = FCS ; /* Z3 full cycle strobe. */
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PIN 6 = READ ; /* The Zorro III read cycle. */
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PIN 7 = !SLACK ; /* The NCR 53C710 slave acknowledge. */
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PIN 8 = !BURST ; /* DMA Burst cycle? */
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PIN 9 = !INTREG ; /* Interrupt register access. */
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PIN 8 = !NOZ3 ; /* Get off the Z3 bus? */
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PIN 9 = INTREG ; /* Interrupt register access. */
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PIN 10 = !INTVEC ; /* Interrupt vector access. */
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PIN 11 = !CFGOUT ; /* Configuration chain output. */
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PIN 13 = !NACK ; /* Network chip acknowledge. */
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PIN 14 = !MTCR ; /* Zorro III burst strobe. */
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PIN 15 = !MASTER ; /* SCSI chip owns the A3090 bus. */
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PIN 16 = !SID ; /* SCSI ID. */
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/** OUTPUTS: **/
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PIN 18 = !D2Z ; /* Data is transferred to Zorro III bus. */
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PIN 19 = !Z2D ; /* Data is transferred from Zorro III bus. */
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PIN 20 = !DBLT ; /* Data is latched. */
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PIN 20 = DBLT ; /* Data is latched. */
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PIN 21 = !DBOE ; /* Data transfer enable. */
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PIN 22 = !ABOEL ; /* Low order address transfer enable. */
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PIN 23 = !ABOEH ; /* High order address transfer enable. */
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@ -61,48 +68,64 @@ PIN 23 = !ABOEH ; /* High order address transfer enable. */
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PIN 17 = !DTACK ; /* Zorro III termination. */
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/** LOGICAL TERMS: **/
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/* It takes both MYBUS and MASTER to fully qualify a cycle. If MYBUS is
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asserted but master not, we're in the process of bus arbitration. If
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MASTER is asserted but not MYBUS, the SCSI chip is master of the A4091
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bus and waiting for a grant to the Zorro bus. In both of these cases,
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as little as possible should be done. */
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mastercyc = MYBUS & MASTER;
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slavecyc = !MYBUS & !MASTER;
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/** OUTPUT TERMS: **/
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/* This is the data output enable control. When data buffers are
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pointed toward the board, they can turn on early in the cycle.
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This is a write for slave access, a read for DMA access. When
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the data buffers are pointed out toward the bus, the have to
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wait until DOE to turn on; this is a slave read or DMA write. */
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wait until DOE to turn on; this is a slave read or DMA write.
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When the board responds to itself, the buffers are left off. If
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the NOZ3 signal is asserted on a write (eg, master driving the
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Zorro III bus), DBOE must be negated immediately. */
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DBOE = !MYBUS & !READ & FCS & SLAVE
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# MYBUS & READ & FCS
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# !MYBUS & READ & FCS & SLAVE & DOE
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# MYBUS & !READ & FCS & DOE;
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DBOE = slavecyc & SLAVE & !READ & FCS
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# slavecyc & SLAVE & READ & FCS & DOE
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# mastercyc & !SLAVE & !READ & FCS & DOE & !ABOEH & !NOZ3
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# mastercyc & !SLAVE & READ & FCS;
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/* The data buffer direction calculations are very simple. The data to
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Zorro III connection is made for slave reads or DMA writes. The Zorro III
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to data bus connection is made for slave writes or DMA reads. */
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D2Z = !MYBUS & !READ & FCS & SLAVE
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# MYBUS & READ & FCS;
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D2Z = slavecyc & READ & FCS & SLAVE
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# mastercyc & !READ & FCS & !SLAVE;
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Z2D = !MYBUS & READ & FCS & SLAVE
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# MYBUS & !READ & FCS;
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Z2D = slavecyc & !READ & FCS & SLAVE
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# mastercyc & READ & FCS & !SLAVE;
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/* The data latching function is also reasonably simple. For either kind of
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access, data is latched when DTACK is asserted and we're in data time.
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For burst DMA access, we have to take into account MTCR and BURST as well. */
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DBLT = !MYBUS & FCS & DTACK & DOE & SLAVE
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# MYBUS & FCS & DTACK & DOE & !BURST
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# MYBUS & FCS & DTACK & DOE & BURST & MTCR;
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/* For either kind of access, data is latched when DTACK is asserted and
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we're in data time. Data is held through the end of the cycle. */
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DBLT = slavecyc & FCS & DTACK & DOE & SLAVE
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# mastercyc & FCS & DTACK & DOE & !SLAVE
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# DBLT & FCS;
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/* The address buffer controls. I want addresses going in unless the SCSI
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device has been granted the A3090 bus. If so, addresses only go out when
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the A3090 has been granted the Zorro III bus. High order addresses also
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go off very quickly after FCS is asserted. */
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go off quickly after FCS is asserted. */
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ABOEL = !MYBUS & !MASTER
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# MYBUS;
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ABOEL.D = slavecyc
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# mastercyc & !FCS
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# mastercyc & FCS & ABOEL;
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ABOEL.AR = NOZ3;
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ABOEH = !MYBUS & !MASTER
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# MYBUS & !FCS;
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ABOEH.D = slavecyc
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# mastercyc & !FCS;
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ABOEH.AR = NOZ3;
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/* The board needs to generate a DTACK here for slave accesses. Most
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of the slave terminations are very simple, since they're either
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@ -111,12 +134,13 @@ ABOEH = !MYBUS & !MASTER
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any write should also be instantly terminated, that would be a
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configuration register write (reads are governed by ROM access). */
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DTACK = SLAVE & FCS & DOE & SLACK
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DTACK = SLAVE & FCS & DOE & SLACK
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# SLAVE & FCS & DOE & INTREG
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# SLAVE & FCS & DOE & INTVEC
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# SLAVE & FCS & DOE & SID
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# SLAVE & FCS & DOE & NACK
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# SLAVE & FCS & DOE & !CFGOUT & !READ
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# SLAVE & FCS & DOE & DTACK;
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DTACK.OE = SLAVE & FCS;
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DTACK.OE = SLAVE & FCS & !NOZ3;
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@ -1,7 +1,7 @@
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PARTNO U305 ;
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NAME U305 ;
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DATE November 2, 1992 ;
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REV 2 ;
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DATE April 5, 1993 ;
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REV 6 ;
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DESIGNER Dave Haynie ;
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COMPANY Commodore ;
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ASSEMBLY A3090 ;
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@ -20,8 +20,8 @@
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/* DEVICE DATA: */
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/* */
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/* Device: 22V10-10 */
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/* Clock: CLK (33MHz) */
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/* Unused: 17(I/O) */
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/* Clock: CLK (25MHz) */
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/* Unused: 9(I),10(I),14(I/O),15(I/),17(I/O) */
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/* */
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/************************************************************************/
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/* */
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@ -31,6 +31,15 @@
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/* DBH Oct 26: Changes made to speed up Zorro III version of */
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/* the FCS signal. */
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/* DBH Nov 2: Hold onto BFCS until AS goes away for slaves. */
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/* DBH Nov 17: ASQ shutoff based on !AS to prevent FCS echo. */
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/* DBH Nov 19: Eliminate A3 passthrough, part of the self- */
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/* reference fix. */
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/* DBH Apr 1: Added the MASTER signal to prevent bogus A4091 */
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/* activities when SCSI has the A4091 bus but not */
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/* the Zorro III bus. */
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/* DBH Apr 5: When things lined up just right, we missed */
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/* the start of the new AS* cycle. Now it's */
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/* interlocked with the end of the FCS cycle. */
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/* COMPILE -M3 */
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/************************************************************************/
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@ -42,10 +51,9 @@ PIN 3 = !AS ; /* SCSI address strobe. */
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PIN 4 = READ ; /* The Zorro III read cycle. */
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PIN 5 = SIZ1 ; /* SCSI transfer size. */
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PIN 6 = SIZ0 ;
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PIN 7 = !BURST ; /* This cycle will be a burst cycle. */
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PIN 7 = !NOZ3 ; /* Zorro III bus cutoff */
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PIN 8 = !MTCR ; /* Zorro III multiple transfer strobe. */
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PIN 9 = BA3 ; /* SCSI burst addresses. */
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PIN 10 = BA2 ;
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PIN 10 = MASTER ; /* SCSI chip owns A4091 bus. */
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PIN 11 = A1 ; /* SCSI sizing addresses. */
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PIN 13 = A0 ;
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PIN 18 = !EFCS ; /* Zorro III cycle strobe. */
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@ -53,8 +61,6 @@ PIN 23 = DOE ; /* Zorro III data ouput enable. */
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/** OUTPUTS: **/
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PIN 14 = A2 ; /* Zorro III addresses. */
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PIN 15 = A3 ;
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PIN 16 = BFCS ; /* Buffered cycle strobe. */
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PIN 17 = !ASQ ; /* Qualified version of the SCSI AS* */
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PIN 19 = !DS0 ; /* Zorro III data strobes. */
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@ -68,20 +74,31 @@ PIN 22 = !DS3 ;
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/** OUTPUT TERMS: **/
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/* The buffered FCS depends on the mode. In non-DMA modes, it's simply
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based on the expansion FCS. In DMA, the expansion FCS can go away
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before the A3090 SCSI chip cycle is complete, so a latching term is
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added. */
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based on the expansion FCS, as long as a SCSI-chip cycle isn't present
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(that would indicate DMA awaiting a grant). In DMA, the expansion
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FCS starts a cycle, but it can go away before the A4091 SCSI chip cycle
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is complete, so a latching term is added. */
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BFCS = EFCS
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/* With MASTER, I could interlock differently.
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BFCS = EFCS & !MASTER & !MYBUS
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# EFCS & MASTER & MYBUS
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# BFCS & AS & ASQ & MYBUS
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# BFCS & AS & !MYBUS;
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# BFCS & AS & !MYBUS;*/
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BFCS = EFCS & !MYBUS & !AS
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# BFCS & !MYBUS & AS
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# EFCS & MYBUS & AS
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# BFCS & MYBUS & AS & ASQ;
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/* A Zorro III cycle is started based on the start of a SCSI cycle and the
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A3090's ownership of the Zorro III bus. This is a qualifier for that
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start. */
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ASQ.D = AS & MYBUS;
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ASQ.AR = !MYBUS;
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ASQ.D = AS & !BFCS & !EFCS & MYBUS
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# ASQ & MYBUS;
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ASQ.AR = !AS;
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/* The data strobes are based on the low order address and size input
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from the SCSI chip. We don't turn these on until the A3090 is bus
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@ -110,19 +127,4 @@ DS0 = READ
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[DS3..0].OE = MYBUS & DOE;
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/* The burst addresses are done here. When a cycle starts, BA2 and BA3
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are directly routed to A2 and A3. On successive burst cycles, these
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two are incremented to provide the proper Zorro III address. */
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A2.D = BA2 & !DOE
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# A2 & !BURST & DOE
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# A2 & BURST & DOE & MTCR
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# !A2 & BURST & DOE & !MTCR;
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A3.D = BA3 & !DOE
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# A3 & !BURST & DOE
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# A3 & BURST & DOE & MTCR
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# (A2 $ A3) & BURST & DOE & !MTCR;
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[A3,A2].OE = MYBUS;
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121
source/u306.pld
121
source/u306.pld
@ -1,12 +1,12 @@
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PARTNO U306 ;
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PARTNO U306;
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NAME U306 ;
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DATE July 9, 1992 ;
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REV 0 ;
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DATE March 29, 1993 ;
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REV 5 ;
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DESIGNER Dave Haynie ;
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COMPANY Commodore ;
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ASSEMBLY A3090 ;
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LOCATION West Chester ;
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DEVICE p22v10 ;
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DEVICE g22v10 ;
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/************************************************************************/
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/* */
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@ -21,21 +21,34 @@
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/* */
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/* Device: 22V10-10 */
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/* Clock: !CLK (33MHz) */
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/* Unused: 11(I),13(I),18(I/O) */
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/* Unused: 13(I) */
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/* */
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/************************************************************************/
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/* */
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/* REVISION HISTORY: */
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/* */
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/* DBH Jul 9: Original version. */
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/* */
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/* DBH Oct 26: The expansion FCS is now generated here. */
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/* DBH Oct 26: Reworked DTSYNC and STERM to free up AR for */
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/* use EFCS. */
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/* DBH Oct 26: Find the missing DTACK. Fix to correct this. */
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/* DBH Oct 28: Changes here for a different FCS/DTACK strategy */
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/* that makes the FCS shutoff delay independent of */
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/* A3090 DTACK sampling. */
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/* DBH Oct 29: Changed above to also insure STERM is generated */
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/* in slave mode, even at 25MHz. */
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/* DBH Mar 29: Stolen the unused BURST pin for NOZ3. This */
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/* is asserted to get the A4091 off the Zorro III */
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/* bus quickly, even when its local FCS may still */
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/* be active. This is designed to fix the */
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/* multiple A4091 problem. */
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/************************************************************************/
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/** INPUTS: **/
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PIN 1 = !CLK ; /* 33MHz system clock. */
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PIN 2 = !MYBUS ; /* SCSI owns the Zorro III bus. */
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PIN 3 = FCS ; /* Zorro III cycle strobe. */
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PIN 3 = BFCS ; /* A3090 local Zorro III cycle strobe. */
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PIN 4 = !MTACK ; /* Zorro III slave burst strobe. */
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PIN 5 = !CBREQ ; /* SCSI burst request. */
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PIN 6 = !SCSI ; /* SCSI slave chip select. */
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@ -43,77 +56,93 @@ PIN 7 = !EDTACK ; /* Zorro III data acknowledge, on bus. */
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PIN 8 = !ABOEH ; /* High order address buffer enable. */
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PIN 9 = !BERR ; /* Zorro III bus error. */
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PIN 10 = !RST ; /* Zorro III reset. */
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PIN 11 = !ASQ ; /* Clocked and qualified SCSI strobe. */
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/** OUTPUTS: **/
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PIN 14 = !BDTACK ; /* Zorro III data acknowledge, buffered. */
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PIN 16 = !STERM ; /* SCSI termination. */
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PIN 17 = !BURST ; /* This cycle will be a burst cycle. */
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PIN 17 = !NOZ3 ; /* Stop driving Zorro III! */
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PIN 18 = !EFCS ; /* Zorro III cycle strobe for DMA. */
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PIN 19 = DOE ; /* Zorro III data ouput enable. */
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PIN 21 = !MTCR ; /* Zorro III multiple transfer strobe. */
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PIN 22 = !LASTBURST ; /* Zorro III end-of-burst indicator. */
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PIN 23 = !CBACK ; /* SCSI burst acknowledge. */
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/** USED INTERNALLY: **/
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PIN 15 = !DTSYNC ; /* Synchronizer for DTACK->STERM. */
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PIN 20 = !DCNT ; /* State bit for Zorro III stuff. */
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PIN 15 = !DCNT ; /* State bit for Zorro III stuff. */
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PIN 20 = !DTSYNC ; /* Synchronizer for DTACK->STERM. */
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PIN 22 = !CYCZ3 ; /* On-bus Zorro III cycle. */
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/** OUTPUT TERMS: **/
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/* The Zorro III cycle starts on-bus as soon as it's certain to be a real
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cycle that's starting. If just starting, the buffered FCS isn't
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asserted but ASQ is. Once on, it stays on until a DTACK is properly
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noticed. */
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CYCZ3 = !RST & MYBUS & !BFCS & ASQ & !BDTACK & !CLK
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# !RST & MYBUS & CYCZ3 & ASQ & !BDTACK;
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/* The master-mode FCS is asserted onto the bus once we have determined
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a real out-to-bus Zorro III cycle should take place. This wasn't
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originally clocked out, but I got nervous about ABOEH setup. */
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EFCS = CLK & MYBUS & CYCZ3 & !RST
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# EFCS & MYBUS & CYCZ3 & !RST;
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EFCS.OE = MYBUS & CYCZ3;
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/* Get off the Zorro III bus right after the EFCS cycle ends, hold it
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until the local cycle ends. */
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NOZ3 = MYBUS & BFCS & !CYCZ3
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# RST;
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/* The data output enable has to wait until a safe "data phase". This is
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guaranteed to be two clocks after FCS falls. DCNT is used to time
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this from cycle's start. */
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DOE.D = FCS & !DOE & MYBUS & DCNT
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# FCS & DOE;
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DOE.D = BFCS & !RST & !DOE & MYBUS & DCNT
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# BFCS & !RST & DOE;
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DOE.OE = MYBUS;
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DOE.AR = RST;
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/* This form FCS, to ensure proper DOE assertion. */
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/* This is a count phase from FCS, to ensure proper DOE assertion. */
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DCNT.D = FCS & !DOE & !DCNT & MYBUS
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# FCS & DCNT;
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DCNT.AR = RST;
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DCNT.D = BFCS & !DOE & !DCNT & MYBUS
|
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# BFCS & DCNT;
|
||||
|
||||
/* This signal samples an incoming DTACK, to help out with STERM
|
||||
generation. */
|
||||
/* This signal samples a termination signal. It used to sample EDTACK, but
|
||||
the quick turnoff of EFCS means that EDTACK may be gone before our sampling
|
||||
edge comes around. Instead, the state where EFCS is negated but BFCS is
|
||||
asserted indicates that the EFCS logic has detected EDTACK. */
|
||||
|
||||
DTSYNC.D = FCS & DOE & !BURST & EDTACK
|
||||
# FCS & DOE & BURST & EDTACK & MTCR;
|
||||
DTSYNC.AR = RST;
|
||||
DTSYNC.D = BFCS & !RST & DOE & BDTACK
|
||||
# BFCS & !RST & DOE & DTSYNC;
|
||||
DTSYNC.AR = !BFCS;
|
||||
|
||||
/* The SCSI termination is based on a synchronized DTACK. I actually
|
||||
/* The SCSI termination is based on a synchronized DTACK. I
|
||||
synchronize DTACK for either slave or master cycle, since the
|
||||
NCR 53C710 wants the effect of SLACK (which makes a DTACK on slave
|
||||
to SCSI cycles) reflected on STERM to actually end the cycle. */
|
||||
|
||||
STERM.D = DTSYNC & EDTACK & FCS & !BURST
|
||||
# DTSYNC & !STERM & FCS & BURST & MTCR;
|
||||
STERM.AR = RST;
|
||||
STERM.D = !RST & MYBUS & BFCS & DTSYNC & !STERM & BDTACK
|
||||
# !RST & !MYBUS & BFCS & BDTACK & !STERM;
|
||||
STERM.AR = !BFCS;
|
||||
|
||||
/* The SCSI chips gets a CBACK any time we have an MTACK. */
|
||||
/* We _never_ issue a CBACK, since BURST isn't supported. */
|
||||
|
||||
CBACK = MYBUS & FCS & MTACK;
|
||||
CBACK.OE = MYBUS;
|
||||
|
||||
/* The burst cycle is based on the burst handshaking between Zorro III and
|
||||
the SCSI chip. This has to be done by DOE time. */
|
||||
|
||||
BURST = MYBUS & MTACK & FCS & CBACK & !DOE
|
||||
# MYBUS & BURST & FCS;
|
||||
|
||||
LASTBURST = MYBUS & BURST & !MTACK & MTCR
|
||||
# MYBUS & LASTBURST & FCS;
|
||||
CBACK = 'b'0;
|
||||
CBACK.OE = 'b'0;
|
||||
|
||||
/* The burst strobe is generated for any burst cycle
|
||||
/* We _never_ issue an MTCR, since BURST isn't supported. */
|
||||
|
||||
MTCR.D = MYBUS & FCS & BURST & DOE & !STERM & !LASTBURST
|
||||
# MYBUS & FCS & BURST & DOE & !STERM & MTCR;
|
||||
MTCR.AR = RST;
|
||||
MTCR = 'b'0;
|
||||
MTCR.OE = 'b'0;
|
||||
|
||||
/* The DTACK line is buffered into the rest of the board. */
|
||||
/* The DTACK line is buffered into the rest of the board. It actually
|
||||
latches the EDTACK line in various ways, since EDTACK isn't necessarily
|
||||
going to hang around long enough to be sampled. */
|
||||
|
||||
BDTACK = EDTACK;
|
||||
BDTACK = !RST & BFCS & EDTACK
|
||||
# !RST & BFCS & BDTACK & !STERM;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user