LIV2/VHDL-6551-ACIA
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David Banks 6434e38151 Fix synchronization issue in ACIA_TX
2021-09-24 21:07:39 +02:00
ACIA_BRGEN.vhd
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2021-09-24 21:07:24 +02:00
ACIA_RX.vhd
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2021-09-24 21:07:24 +02:00
ACIA_TX.vhd
Fix synchronization issue in ACIA_TX
2021-09-24 21:07:39 +02:00
ACIA.vhd
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2021-09-24 21:07:24 +02:00
LICENSE
Initial commit.
2018-07-16 11:59:07 +10:00
README.md
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README.md

VHDL 6551 ACIA

A synthesizable VHDL core for a 6551 ACIA (with a working TX status bit..)

Todo:

  • Implement DSR/DCD & associated interrupts
  • Support word sizes other than 8
  • Support different stop bit counts
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Readme GPL-2.0 43 KiB
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VHDL 100%