LIV2/VHDL-6551-ACIA
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Matt Harlum 2018-07-17 19:15:02 +10:00
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@ -5,6 +5,5 @@ A synthesizable VHDL core for a 6551 ACIA (with a working TX status bit..)
Todo:
- Implement DSR/DCD & associated interrupts
- Implement Parity
- Support word sizes other than 8
- Support different stop bit counts