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6a7b69fcce
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Update CPLD Pin mapping and tweak a few things
Rev_A
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2023-07-24 20:24:46 +00:00 |
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a01a926003
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Add License.md
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2023-07-24 16:58:11 +02:00 |
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279bfcb175
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Release Rev_A
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2023-07-24 16:56:39 +02:00 |
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101214b9b1
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Move Disable jumper
Also route the signal through a buffer to protect the CPLD
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2023-07-16 17:23:13 +02:00 |
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c13ef80952
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Add JLC Part numbers for IDE Connectors & TH caps
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2023-07-13 16:41:54 +02:00 |
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abee39926c
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Change some resistor values from 10K to 1K out of paranoia
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2023-07-13 15:54:51 +02:00 |
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32846236ff
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Add pull-up for unconnected CS1 pin of IDE channels
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2023-07-12 20:29:08 +02:00 |
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7f1c8157c8
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Moved CPLD and ROM data behind IDE buffers
* Enable Buffers for IDE, ROM and Autoconfig
* Add SLAVE_n equation
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2023-07-12 08:36:13 +00:00 |
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a61b822c16
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Add Firmware
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2023-07-12 08:36:13 +00:00 |
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2e87b06f37
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Move ROM and CPLD data connections to buffered side
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2023-07-12 10:30:23 +02:00 |
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9353015e6d
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Routing complete, need to double-check
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2023-07-10 16:23:03 +02:00 |
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e92db97d39
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Rename to RIPPLE, do a bunch more routing etc
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2023-07-04 13:03:45 +02:00 |
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ada1612930
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A good start
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2023-06-25 19:59:43 +02:00 |
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55a873f313
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Begin schematic
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2023-02-11 20:51:31 +01:00 |
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12f0d58f16
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Initial commit.
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2023-02-09 14:20:20 +01:00 |
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