Stefan Reinauer be5aaffd74 RTL: Address matching for intreg ...

Make address matching for intreg the same as for everything else,
using bits 23-17

2025-06-08 16:17:52 -07:00

..

.gitignore

Add skeleton to include Gerbers, BOM files, RTL etc

2025-04-02 07:58:30 -07:00

A4092.ucf

RTL: Fix signal naming and hook up right bits of DIP

2025-06-07 11:29:29 -07:00

autoconfig.v

Implement autoconfig (courtesy Matt Harlum)

2025-04-23 15:25:33 -07:00

buffer_control.v

RTL: Add additional data and address lines

2025-05-30 08:25:34 -07:00

globalparams.vh

Implement autoconfig (courtesy Matt Harlum)

2025-04-23 15:25:33 -07:00

intreg_access.v

RTL: Address matching for intreg

2025-06-08 16:17:52 -07:00

Makefile

Add option to move SID into CPLD / flash entirely

2025-05-18 16:18:34 -07:00

rom_access.v

RTL: Add additional data and address lines

2025-05-30 08:25:34 -07:00

scsi_access.v

Update scsi_access

2025-06-06 23:11:29 -07:00

sid_access.v

RTL: Fix signal naming and hook up right bits of DIP

2025-06-07 11:29:29 -07:00

template.xst

Start adding pin descriptions to A4092 RTL

2025-04-09 20:45:10 -07:00

top.v

RTL: Address matching for intreg

2025-06-08 16:17:52 -07:00

zorro_dma_master.v

Fix address mapping

2025-06-07 23:36:44 -07:00

zorro_master_arbiter.v

Update RTL

2025-06-01 12:38:16 -07:00