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RIPPLE-IDE/RTL/RIPPLE.tim
Matthew Harlum 1551249b90 RTL: Fix bug in ROM Bank select 
At reset the rom bank select was set to follow addr[16:15] until IDE was activated by a write to any IDE reg.

After that it reflects the value of the rom_bankSel register

On a new board with no driver yet in flash this switch would not be triggered, causing the driver to be written to the wrong bank of flash.

Now the switch will flip on any write to the boards range, the flash identification step will trigger this.
2024-04-18 16:25:16 +12:00

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Performance Summary Report
--------------------------
Design: RIPPLE
Device: XC9572XL-10-VQ64
Speed File: Version 3.0
Program: Timing Report Generator: version P.20131013
Date: Thu Apr 18 04:18:38 2024
Performance Summary:
Pad to Pad (tPD) : 24.0ns (2 macrocell levels)
Pad 'ADDR<19>' to Pad 'IDE1_CS_n<0>'
Clock net 'AS_n' path delays:
Clock Pad to Output Pad (tCO) : 30.1ns (3 macrocell levels)
Clock Pad 'AS_n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Minimum Clock Period: 14.0ns
Maximum Internal Clock Speed: 71.4Mhz
(Limited by Clock Pulse Width)
Clock net 'C3n' path delays:
Clock Pad to Output Pad (tCO) : 39.6ns (4 macrocell levels)
Clock Pad 'C3n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Clock to Setup (tCYC) : 19.7ns (2 macrocell levels)
Clock to Q, net 'AUTOCONFIG/ide_base<1>.Q' to TFF Setup(D) at 'IDE/rom_bankSel<0>.D'(Pterm Clock)
Target FF drives output net 'IDE/rom_bankSel<0>'
Setup to Clock at the Pad (tSU) : 4.1ns (1 macrocell levels)
Data signal 'ADDR<17>' to TFF D input Pin at 'IDE/rom_bankSel<0>.D'
Clock pad 'C3n' (Pterm Clock)
Minimum Clock Period: 19.7ns
Maximum Internal Clock Speed: 50.7Mhz
(Limited by Cycle Time)
Clock net 'C1n' path delays:
Clock Pad to Output Pad (tCO) : 39.6ns (4 macrocell levels)
Clock Pad 'C1n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Clock to Setup (tCYC) : 19.7ns (2 macrocell levels)
Clock to Q, net 'AUTOCONFIG/ide_base<1>.Q' to TFF Setup(D) at 'IDE/rom_bankSel<0>.D'(Pterm Clock)
Target FF drives output net 'IDE/rom_bankSel<0>'
Setup to Clock at the Pad (tSU) : 4.1ns (1 macrocell levels)
Data signal 'ADDR<17>' to TFF D input Pin at 'IDE/rom_bankSel<0>.D'
Clock pad 'C1n' (Pterm Clock)
Minimum Clock Period: 19.7ns
Maximum Internal Clock Speed: 50.7Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A A A A A A A A A
\ D D D D D D D D D D D
\ D D D D D D D D D D D
\ R R R R R R R R R R R
\ < < < < < < < < < < <
\ 1 1 1 1 1 1 1 1 2 2 2
\ 2 3 4 5 6 7 8 9 0 1 2
\ > > > > > > > > > > >
\
\
\
\
To \------------------------------------------------------------------
DBUS<12> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<13> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<14> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<15> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
IDE1_CS_n<0> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDE1_CS_n<1> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDE2_CS_n<0> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDE2_CS_n<1> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDEBUF_OE 14.5 23.2 23.2 23.2 23.2 14.5 22.2
IDE_ROMEN 16.3 16.3 16.3 15.5 15.9 14.5 15.5 15.5 15.9
IOR_n
IOW_n
ROM_BANK<0> 14.5
SLAVE_n 14.5 23.2 23.2 23.2 23.2 14.5 22.2
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A B C R R
\ D S E F E W
\ D _ R G S
\ R n R I E
\ < _ N T
\ 2 n _ _
\ 3 n n
\ >
\
\
\
\
To \------------------------------------
DBUS<12> 11.0 11.0 11.0 11.0
DBUS<13> 11.0 11.0 11.0 11.0
DBUS<14> 11.0 11.0 11.0 11.0
DBUS<15> 11.0 11.0 11.0 11.0
IDE1_CS_n<0> 23.6
IDE1_CS_n<1> 23.6
IDE2_CS_n<0> 23.6
IDE2_CS_n<1> 23.6
IDEBUF_OE 23.2 14.5 14.5 14.5 14.5 14.5
IDE_ROMEN 16.3 14.5
IOR_n 14.5 14.5
IOW_n 14.5 14.5
ROM_BANK<0>
SLAVE_n 23.2 14.5 14.5
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From A C C
\ S 1 3
\ _ n n
\ n
\
\
\
\
\
\
\
\
To \------------------
CFGOUT_n 14.7
DBUS<12> 18.9 22.4 22.4
DBUS<13> 18.9 22.4 22.4
DBUS<14> 18.9 22.4 22.4
DBUS<15> 18.9 22.4 22.4
IDE1_CS_n<0> 30.1 39.6 39.6
IDE1_CS_n<1> 30.1 39.6 39.6
IDE2_CS_n<0> 30.1 39.6 39.6
IDE2_CS_n<1> 30.1 39.6 39.6
IDEBUF_OE 30.1 38.8 38.8
IDE_ROMEN 22.4 31.9 31.9
IOR_n 30.1 30.1
IOW_n 30.1 30.1
ROM_BANK<0> 30.1 30.1
ROM_BANK<1> 30.1 30.1
SLAVE_n 30.1 38.8 38.8
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU or tSUF) (nsec)
\ From C C
\ 1 3
\ n n
\
\
\
\
\
\
To \------------
ADDR<15> -4.6 -4.6
ADDR<16> -4.6 -4.6
ADDR<17> 4.1 4.1
ADDR<18> 4.1 4.1
ADDR<19> 4.1 4.1
ADDR<1> -4.6 -4.6
ADDR<20> 4.1 4.1
ADDR<21> -4.6 -4.6
ADDR<22> 3.1 3.1
ADDR<23> 4.1 4.1
ADDR<2> -4.6 -4.6
ADDR<3> -4.6 -4.6
ADDR<4> -4.6 -4.6
ADDR<5> -4.6 -4.6
ADDR<6> -4.6 -4.6
ADDR<7> -4.6 -4.6
ADDR<8> -4.6 -4.6
AS_n -5.6 -5.6
CFGIN_n -5.6 -5.6
DBUS<12> -5.6 -5.6
DBUS<13> -5.6 -5.6
DBUS<14> -4.6 -4.6
DBUS<15> -4.6 -4.6
IDE_OFF_n -5.6 -5.6
RESET_n -5.6 -5.6
RW -4.6 -4.6
UDS_n -4.6 -4.6
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C3n)
\ From A A A A A A A A
\ S U U U U U U U
\ _ T T T T T T T
\ n O O O O O O O
\ _ C C C C C C C
\ S O O O O O O O
\ 4 N N N N N N N
\ . F F F F F F F
\ Q I I I I I I I
\ G G G G G G G
\ / / / / / / /
\ d i i i i i i
\ t d d d d d d
\ a e e e e e e
\ c _ _ _ _ _ _
\ k b b b b b b
\ . a a a a a a
\ Q s s s s s s
\ e e e e e e
\ < < < < < <
\ 1 2 3 4 5 6
\ > > > > > >
\ . . . . . .
\ Q Q Q Q Q Q
\
\
\
\
To \------------------------------------------------
AS_n_S4.D
AUTOCONFIG/dtack.D 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D 10.0
IDE/ide_enabled.D 11.4 11.4 11.0 11.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 19.7 19.7 19.7 11.0 18.7
IDE/rom_bankSel<1>.D 19.7 19.7 19.7 19.7 11.0 18.7
ide_enable.CE
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C3n)
\ From A A A I I I I R
\ U U U D D D D E
\ T T T E E E E S
\ O O O / / / / E
\ C C C S i r r T
\ O O O 3 d o o .
\ N N N _ e m m Q
\ F F F n _ _ _
\ I I I . e b b
\ G G G Q n a a
\ / / / a n n
\ i i s b k k
\ d d h l S S
\ e e u e e e
\ _ _ t d l l
\ b c u . < <
\ a o p Q 0 1
\ s n . > >
\ e f Q . .
\ < i Q Q
\ 7 g
\ > u
\ . r
\ Q e
\ d
\ .
\ Q
\
To \------------------------------------------------
AS_n_S4.D 10.0
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.4 10.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 18.7 11.0 11.0
IDE/rom_bankSel<1>.D 19.7 18.7 11.0 11.0
ide_enable.CE 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C3n)
\ From i
\ d
\ e
\ _
\ e
\ n
\ a
\ b
\ l
\ e
\ .
\ Q
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
To \------
AS_n_S4.D
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE
AUTOCONFIG/ide_base<2>.CE
AUTOCONFIG/ide_base<3>.CE
AUTOCONFIG/ide_base<4>.CE
AUTOCONFIG/ide_base<5>.CE
AUTOCONFIG/ide_base<6>.CE
AUTOCONFIG/ide_base<7>.CE
AUTOCONFIG/ide_configured.CE
AUTOCONFIG/shutup.CE
DBUS<12>.D 10.0
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.0
IDE/rom_bankSel<0>.D 11.0
IDE/rom_bankSel<1>.D 11.0
ide_enable.CE
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C1n)
\ From A A A A A A A A
\ S U U U U U U U
\ _ T T T T T T T
\ n O O O O O O O
\ _ C C C C C C C
\ S O O O O O O O
\ 4 N N N N N N N
\ . F F F F F F F
\ Q I I I I I I I
\ G G G G G G G
\ / / / / / / /
\ d i i i i i i
\ t d d d d d d
\ a e e e e e e
\ c _ _ _ _ _ _
\ k b b b b b b
\ . a a a a a a
\ Q s s s s s s
\ e e e e e e
\ < < < < < <
\ 1 2 3 4 5 6
\ > > > > > >
\ . . . . . .
\ Q Q Q Q Q Q
\
\
\
\
To \------------------------------------------------
AS_n_S4.D
AUTOCONFIG/dtack.D 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D 10.0
IDE/ide_enabled.D 11.4 11.4 11.0 11.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 19.7 19.7 19.7 11.0 18.7
IDE/rom_bankSel<1>.D 19.7 19.7 19.7 19.7 11.0 18.7
ide_enable.CE
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C1n)
\ From A A A I I I I R
\ U U U D D D D E
\ T T T E E E E S
\ O O O / / / / E
\ C C C S i r r T
\ O O O 3 d o o .
\ N N N _ e m m Q
\ F F F n _ _ _
\ I I I . e b b
\ G G G Q n a a
\ / / / a n n
\ i i s b k k
\ d d h l S S
\ e e u e e e
\ _ _ t d l l
\ b c u . < <
\ a o p Q 0 1
\ s n . > >
\ e f Q . .
\ < i Q Q
\ 7 g
\ > u
\ . r
\ Q e
\ d
\ .
\ Q
\
To \------------------------------------------------
AS_n_S4.D 10.0
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.4 10.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 18.7 11.0 11.0
IDE/rom_bankSel<1>.D 19.7 18.7 11.0 11.0
ide_enable.CE 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C1n)
\ From i
\ d
\ e
\ _
\ e
\ n
\ a
\ b
\ l
\ e
\ .
\ Q
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
To \------
AS_n_S4.D
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE
AUTOCONFIG/ide_base<2>.CE
AUTOCONFIG/ide_base<3>.CE
AUTOCONFIG/ide_base<4>.CE
AUTOCONFIG/ide_base<5>.CE
AUTOCONFIG/ide_base<6>.CE
AUTOCONFIG/ide_base<7>.CE
AUTOCONFIG/ide_configured.CE
AUTOCONFIG/shutup.CE
DBUS<12>.D 10.0
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.0
IDE/rom_bankSel<0>.D 11.0
IDE/rom_bankSel<1>.D 11.0
ide_enable.CE
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and ends at register
(Fast Input Register for tSUF) D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers. Pin-to-pin setup
requirement is not reported or
guaranteed for product-term clocks
derived from macrocell feedback
signals.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU. Note that
when the computed Maximum Clock Speed
is limited by tCYC it is computed
assuming that all registers are
rising-edge sensitive.
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