At reset the rom bank select was set to follow addr[16:15] until IDE was activated by a write to any IDE reg.
After that it reflects the value of the rom_bankSel register
On a new board with no driver yet in flash this switch would not be triggered, causing the driver to be written to the wrong bank of flash.
Now the switch will flip on any write to the boards range, the flash identification step will trigger this.
* Check RESET length before asserting, seems noise is causing cold-boot issues on BUSRST
* Enable Buffers for reads during S4 regardless of DS'es
* Fixups for Autoconfig
* IDE: don't assert IOW/IOW until S3 to meet address set-up times
* Qualify SLAVE_n with AS_n or it will trigger during Z3 cycles
* Don't register CFGIN at AS_n posedge - Z3 cards would prevent this from working
* Disable DTACK/OVR gen as it's not needed
