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This commit is contained in:
Matt Harlum 2021-02-10 01:57:17 +01:00
commit 810778d138
27 changed files with 23218 additions and 0 deletions
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13
Gerber/Bluster-NPTH.drl Normal file
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M48
; DRILL file {KiCad (5.1.9)-1} date 02/10/21 01:52:35
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; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.9)-1
; #@! TF.FileFunction,NonPlated,1,2,NPTH
FMAT,2
INCH
%
G90
G05
T0
M30

126
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M48
; DRILL file {KiCad (5.1.9)-1} date 02/10/21 01:52:35
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; #@! TF.GenerationSoftware,Kicad,Pcbnew,(5.1.9)-1
; #@! TF.FileFunction,Plated,1,2,PTH
FMAT,2
INCH
T1C0.0157
T2C0.0315
T3C0.0394
%
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128
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@ -0,0 +1,128 @@
{
"Header":
{
"GenerationSoftware":
{
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "(5.1.9)-1"
},
"CreationDate": "2021-02-10T01:52:36+01:00"
},
"GeneralSpecs":
{
"ProjectId":
{
"Name": "Bluster",
"GUID": "426c7573-7465-4722-9e6b-696361645f70",
"Revision": "rev?"
},
"Size":
{
"X": 22.910,
"Y": 86.410
},
"LayerNumber": 2,
"BoardThickness": 1.600
},
"DesignRules":
[
{
"Layers": "Outer",
"PadToPad": 0.127,
"PadToTrack": 0.127,
"TrackToTrack": 0.127,
"MinLineWidth": 0.127,
"TrackToRegion": 0.254,
"RegionToRegion": 0.254
}
],
"FilesAttributes":
[
{
"Path": "Bluster-F_Cu.gbr",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "Bluster-B_Cu.gbr",
"FileFunction": "Copper,L2,Bot",
"FilePolarity": "Positive"
},
{
"Path": "Bluster-F_Paste.gbr",
"FileFunction": "SolderPaste,Top",
"FilePolarity": "Positive"
},
{
"Path": "Bluster-B_Paste.gbr",
"FileFunction": "SolderPaste,Bot",
"FilePolarity": "Positive"
},
{
"Path": "Bluster-F_SilkS.gbr",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "Bluster-B_SilkS.gbr",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "Bluster-F_Mask.gbr",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "Bluster-B_Mask.gbr",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "Bluster-Edge_Cuts.gbr",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup":
[
{
"Type": "Legend",
"Notes": "Layer F.SilkS"
},
{
"Type": "SolderPaste",
"Notes": "Layer F.Paste"
},
{
"Type": "SolderMask",
"Notes": "Layer F.Mask"
},
{
"Type": "Copper",
"Notes": "Layer F.Cu"
},
{
"Type": "Dielectric",
"Material": "FR4",
"Notes": "Layers L1/L2"
},
{
"Type": "Copper",
"Notes": "Layer B.Cu"
},
{
"Type": "SolderMask",
"Notes": "Layer B.Mask"
},
{
"Type": "SolderPaste",
"Notes": "Layer B.Paste"
},
{
"Type": "Legend",
"Notes": "Layer B.SilkS"
}
]
}

28
Kicad/.gitignore vendored Normal file
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@ -0,0 +1,28 @@
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
# Format documentation: http://kicad-pcb.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv

257
Kicad/Bluster-cache.lib Normal file
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@ -0,0 +1,257 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Buster_Buster
#
DEF Buster_Buster U 0 40 Y Y 2 F N
F0 "U" -50 50 50 H V C CNN
F1 "Buster_Buster" 150 -3200 50 H V C CNN
F2 "Package_DIP:DIP-48_W15.24mm_Socket" 0 -200 50 H V C CNN
F3 "" 0 -200 50 H I C CNN
DRAW
S 850 -3150 0 0 1 1 0 f
S -150 -100 150 -650 2 1 0 f
X ~BR4 10 -100 -400 100 R 50 50 1 1 I
X ~BR5 11 -100 -500 100 R 50 50 1 1 I
X ~SLAVE1 12 -100 -650 100 R 50 50 1 1 I
X ~SLAVE2 13 -100 -750 100 R 50 50 1 1 I
X ~SLAVE3 14 -100 -850 100 R 50 50 1 1 I
X ~SLAVE4 15 -100 -950 100 R 50 50 1 1 I
X ~SLAVE5 16 -100 -1050 100 R 50 50 1 1 I
X ~BG 17 -100 -2150 100 R 50 50 1 1 I
X ~CDAC 18 -100 -2850 100 R 50 50 1 1 I
X C1 19 -100 -2950 100 R 50 50 1 1 I
X ~BG1 2 950 -100 100 L 50 50 1 1 O
X C3 20 -100 -3050 100 R 50 50 1 1 I
X ~C2 21 950 -3050 100 L 50 50 1 1 O
X ~C4 22 950 -2950 100 L 50 50 1 1 O
X ~GBG 23 950 -1950 100 L 50 50 1 1 O
X ~BEER 26 -100 -1750 100 R 50 50 1 1 I
X ~BR 27 950 -2250 100 L 50 50 1 1 O
X ~CBR 28 950 -2350 100 L 50 50 1 1 O
X ~CBG 29 950 -2150 100 L 50 50 1 1 O
X ~BG2 3 950 -200 100 L 50 50 1 1 O
X A19 30 -100 -1200 100 R 50 50 1 1 I
X A20 31 -100 -1300 100 R 50 50 1 1 I
X A21 32 -100 -1400 100 R 50 50 1 1 I
X A22 33 -100 -1500 100 R 50 50 1 1 I
X A23 34 -100 -1600 100 R 50 50 1 1 I
X READ 35 -100 -2050 100 R 50 50 1 1 I
X ~AS 36 -100 -2550 100 R 50 50 1 1 I
X ~LDS 37 -100 -1950 100 R 50 50 1 1 I
X ~UDS 38 -100 -1850 100 R 50 50 1 1 I
X ~BOSS 39 -100 -2250 100 R 50 50 1 1 I
X ~BG3 4 950 -300 100 L 50 50 1 1 O
X ~OVR 40 -100 -2350 100 R 50 50 1 1 I
X ~OWN 41 -100 -2450 100 R 50 50 1 1 I
X ~RST 42 -100 -2650 100 R 50 50 1 1 I
X TEST 43 950 -2650 100 L 50 50 1 1 I
X PTEST 44 950 -2550 100 L 50 50 1 1 I
X ~D2P 45 950 -1550 100 L 50 50 1 1 O
X ~DB0E 46 950 -800 100 L 50 50 1 1 O
X DOE 47 950 -900 100 L 50 50 1 1 O
X ~BG4 5 950 -400 100 L 50 50 1 1 O
X ~BG5 6 950 -500 100 L 50 50 1 1 O
X ~BR1 7 -100 -100 100 R 50 50 1 1 I
X ~BR2 8 -100 -200 100 R 50 50 1 1 I
X ~BR3 9 -100 -300 100 R 50 50 1 1 I
X GND 1 -50 -750 100 U 50 50 2 1 I
X GND 24 50 -750 100 U 50 50 2 1 W
X VCC 25 50 0 100 D 50 50 2 1 W
X VCC 48 -50 0 100 D 50 50 2 1 W
ENDDRAW
ENDDEF
#
# CPLD_Xilinx_XC9572XL-VQ64
#
DEF CPLD_Xilinx_XC9572XL-VQ64 U 0 20 Y Y 1 F N
F0 "U" -650 1600 50 H V C CNN
F1 "CPLD_Xilinx_XC9572XL-VQ64" -650 -1700 50 H V C CNN
F2 "Package_QFP:TQFP-64_10x10mm_P0.5mm" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TQFP*10x10mm*P0.5mm*
$ENDFPLIST
DRAW
S -650 1550 650 -1650 1 1 10 f
X P1 1 -800 0 150 R 50 50 1 1 B
X P10 10 -800 1200 150 R 50 50 1 1 B
X P11 11 -800 1100 150 R 50 50 1 1 B
X P12 12 -800 1000 150 R 50 50 1 1 B
X P13 13 -800 900 150 R 50 50 1 1 B
X GND 14 -100 -1800 150 U 50 50 1 1 W
X I/O/GCK1 15 -800 800 150 R 50 50 1 1 B
X I/O/GCK2 16 -800 700 150 R 50 50 1 1 B
X I/O/GCK3 17 -800 600 150 R 50 50 1 1 B
X P18 18 -800 500 150 R 50 50 1 1 B
X P19 19 -800 400 150 R 50 50 1 1 B
X I/O/GTS2 2 -800 -100 150 R 50 50 1 1 B
X P20 20 -800 300 150 R 50 50 1 1 B
X GND 21 0 -1800 150 U 50 50 1 1 W
X P22 22 800 1500 150 L 50 50 1 1 B
X P23 23 -800 200 150 R 50 50 1 1 B
X P24 24 800 1400 150 L 50 50 1 1 B
X P25 25 800 1300 150 L 50 50 1 1 B
X VCCIO 26 100 1700 150 D 50 50 1 1 W
X P27 27 800 1200 150 L 50 50 1 1 B
X TDI 28 800 -1300 150 L 50 50 1 1 I
X TMS 29 800 -1400 150 L 50 50 1 1 I
X VCC 3 -100 1700 150 D 50 50 1 1 W
X TCK 30 800 -1500 150 L 50 50 1 1 I
X P31 31 800 1100 150 L 50 50 1 1 B
X P32 32 800 1000 150 L 50 50 1 1 B
X P33 33 800 900 150 L 50 50 1 1 B
X P34 34 800 800 150 L 50 50 1 1 B
X P35 35 800 700 150 L 50 50 1 1 B
X P36 36 800 600 150 L 50 50 1 1 B
X VCC 37 0 1700 150 D 50 50 1 1 W
X P38 38 800 500 150 L 50 50 1 1 B
X P39 39 800 400 150 L 50 50 1 1 B
X P4 4 -800 -200 150 R 50 50 1 1 B
X P40 40 800 300 150 L 50 50 1 1 B
X GND 41 100 -1800 150 U 50 50 1 1 W
X P42 42 800 200 150 L 50 50 1 1 B
X P43 43 800 0 150 L 50 50 1 1 B
X P44 44 800 -100 150 L 50 50 1 1 B
X P45 45 800 -200 150 L 50 50 1 1 B
X P46 46 800 -300 150 L 50 50 1 1 B
X P47 47 800 -400 150 L 50 50 1 1 B
X P48 48 800 -500 150 L 50 50 1 1 B
X P49 49 800 -600 150 L 50 50 1 1 B
X I/O/GTS1 5 -800 -300 150 R 50 50 1 1 B
X P50 50 800 -700 150 L 50 50 1 1 B
X P51 51 800 -800 150 L 50 50 1 1 B
X P52 52 800 -900 150 L 50 50 1 1 B
X TDO 53 800 -1600 150 L 50 50 1 1 O
X GND 54 200 -1800 150 U 50 50 1 1 W
X VCCIO 55 200 1700 150 D 50 50 1 1 W
X P56 56 800 -1000 150 L 50 50 1 1 B
X P57 57 800 -1100 150 L 50 50 1 1 B
X P58 58 -800 -600 150 R 50 50 1 1 B
X P59 59 -800 -700 150 R 50 50 1 1 B
X P6 6 -800 -400 150 R 50 50 1 1 B
X P60 60 -800 -800 150 R 50 50 1 1 B
X P61 61 -800 -900 150 R 50 50 1 1 B
X P62 62 -800 -1000 150 R 50 50 1 1 B
X P63 63 -800 -1100 150 R 50 50 1 1 B
X I/O/GSR 64 -800 -1200 150 R 50 50 1 1 B
X P7 7 -800 -500 150 R 50 50 1 1 B
X P8 8 -800 1400 150 R 50 50 1 1 B
X P9 9 -800 1300 150 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Connector_Conn_01x06_Female
#
DEF Connector_Conn_01x06_Female J 0 40 Y N 1 F N
F0 "J" 0 300 50 H V C CNN
F1 "Connector_Conn_01x06_Female" 0 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
A 0 -300 20 901 -901 1 1 6 N 0 -280 0 -320
A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220
A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
A 0 100 20 901 -901 1 1 6 N 0 120 0 80
A 0 200 20 901 -901 1 1 6 N 0 220 0 180
P 2 1 1 6 -50 -300 -20 -300 N
P 2 1 1 6 -50 -200 -20 -200 N
P 2 1 1 6 -50 -100 -20 -100 N
P 2 1 1 6 -50 0 -20 0 N
P 2 1 1 6 -50 100 -20 100 N
P 2 1 1 6 -50 200 -20 200 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 -200 -300 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Regulator_Linear_AP7361C-33E
#
DEF Regulator_Linear_AP7361C-33E U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_AP7361C-33E" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 225 50 H I C CIN
F3 "" 0 -50 50 H I C CNN
ALIAS SPX2920M3-5.0_SOT223 LT1129-3.3_SOT223 LT1129-5.0_SOT223 LM2937xMP AP7361C-10E AP7361C-12E AP7361C-15E AP7361C-18E AP7361C-25E AP7361C-28E AP7361C-33E
$FPLIST
SOT?223*
$ENDFPLIST
DRAW
S -200 -200 200 75 0 1 10 f
X VI 1 -300 0 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X VO 3 300 0 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

2354
Kicad/Bluster.kicad_pcb Normal file
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File diff suppressed because it is too large Load Diff

248
Kicad/Bluster.pro Normal file
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@ -0,0 +1,248 @@
update=13/02/2021 3:47:29 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.127
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.127
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.127
TrackWidth=0.127
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

502
Kicad/Bluster.sch Normal file
View File

@ -0,0 +1,502 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "BLUSTER"
Date ""
Rev "A"
Comp "LIV2"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L CPLD_Xilinx:XC9572XL-VQ64 U1
U 1 1 6011E759
P 5600 2950
F 0 "U1" H 5600 4831 50 0000 C CNN
F 1 "Buster" H 5600 4740 50 0000 C CNN
F 2 "Package_QFP:TQFP-64_10x10mm_P0.5mm" H 5600 2950 50 0001 C CNN
F 3 "" H 5600 2950 50 0001 C CNN
1 5600 2950
1 0 0 -1
$EndComp
$Comp
L Buster:Buster J1
U 1 1 60134927
P 2650 1400
F 0 "J1" H 2650 1450 50 0000 L CNN
F 1 "Buster" H 2650 -1800 50 0000 L CNN
F 2 "Package_DIP:DIP-48_W15.24mm_Socket" H 2828 934 50 0001 L CNN
F 3 "" H 2650 1200 50 0001 C CNN
1 2650 1400
1 0 0 -1
$EndComp
$Comp
L Buster:Buster J1
U 2 1 60130EF0
P 1500 2800
F 0 "J1" H 1350 2900 50 0000 C CNN
F 1 "Buster" H 1250 2000 50 0000 C CNN
F 2 "Package_DIP:DIP-48_W15.24mm_Socket" H 1925 2873 50 0001 C CNN
F 3 "" H 1500 2600 50 0001 C CNN
2 1500 2800
1 0 0 -1
$EndComp
Text Label 2550 1500 2 50 ~ 0
~BR1
Text Label 2550 1600 2 50 ~ 0
~BR2
Text Label 2550 1700 2 50 ~ 0
~BR3
Text Label 2550 1800 2 50 ~ 0
~BR4
Text Label 2550 1900 2 50 ~ 0
~BR5
Text Label 2550 2050 2 50 ~ 0
~SLAVE1
Text Label 2550 2150 2 50 ~ 0
~SLAVE2
Text Label 2550 2250 2 50 ~ 0
~SLAVE3
Text Label 2550 2350 2 50 ~ 0
~SLAVE4
Text Label 2550 2450 2 50 ~ 0
~SLAVE5
Text Label 2550 2600 2 50 ~ 0
~A19
Text Label 2550 2700 2 50 ~ 0
~A20
Text Label 2550 2800 2 50 ~ 0
~A21
Text Label 2550 2900 2 50 ~ 0
~A22
Text Label 2550 3000 2 50 ~ 0
~A23
Text Label 3600 1500 0 50 ~ 0
~BG1
Text Label 3600 1600 0 50 ~ 0
~BG2
Text Label 3600 1700 0 50 ~ 0
~BG3
Text Label 3600 1800 0 50 ~ 0
~BG4
Text Label 3600 1900 0 50 ~ 0
~BG5
Text Label 3600 2200 0 50 ~ 0
~DBOE
Text Label 3600 2300 0 50 ~ 0
DOE
Text Label 3600 2950 0 50 ~ 0
D2P
Text Label 3600 3350 0 50 ~ 0
GBG
Text Label 3600 3550 0 50 ~ 0
~CBG
Text Label 3600 3650 0 50 ~ 0
~BR
Text Label 3600 3750 0 50 ~ 0
~CBR
Text Label 3600 4350 0 50 ~ 0
~C4
Text Label 3600 4450 0 50 ~ 0
~C2
Text Label 2550 3150 2 50 ~ 0
~BEER
Text Label 2550 3250 2 50 ~ 0
~UDS
Text Label 2550 3350 2 50 ~ 0
~LDS
Text Label 2550 3450 2 50 ~ 0
READ
Text Label 2550 3550 2 50 ~ 0
~BG
Text Label 2550 3650 2 50 ~ 0
~BOSS
Text Label 2550 3750 2 50 ~ 0
~OVR
Text Label 2550 3850 2 50 ~ 0
~OWN
Text Label 2550 3950 2 50 ~ 0
~AS
Text Label 2550 4050 2 50 ~ 0
~RST
Text Label 2550 4250 2 50 ~ 0
~CDAC
Text Label 2550 4350 2 50 ~ 0
C1
Text Label 2550 4450 2 50 ~ 0
C3
Wire Wire Line
5800 1250 5700 1250
Connection ~ 5600 1250
Wire Wire Line
5600 1250 5500 1250
Connection ~ 5700 1250
Wire Wire Line
5700 1250 5600 1250
Wire Wire Line
5800 4750 5700 4750
Connection ~ 5600 4750
Wire Wire Line
5600 4750 5500 4750
Connection ~ 5700 4750
Wire Wire Line
5700 4750 5650 4750
Wire Wire Line
5650 5000 5650 4750
$Comp
L power:GND #PWR03
U 1 1 60140644
P 5650 5000
F 0 "#PWR03" H 5650 4750 50 0001 C CNN
F 1 "GND" H 5655 4827 50 0000 C CNN
F 2 "" H 5650 5000 50 0001 C CNN
F 3 "" H 5650 5000 50 0001 C CNN
1 5650 5000
1 0 0 -1
$EndComp
Wire Wire Line
1450 3550 1500 3550
$Comp
L power:GND #PWR01
U 1 1 60142149
P 1500 3550
F 0 "#PWR01" H 1500 3300 50 0001 C CNN
F 1 "GND" H 1505 3377 50 0000 C CNN
F 2 "" H 1500 3550 50 0001 C CNN
F 3 "" H 1500 3550 50 0001 C CNN
1 1500 3550
1 0 0 -1
$EndComp
Connection ~ 1500 3550
Wire Wire Line
1500 3550 1550 3550
$Comp
L Device:C C1
U 1 1 6014581D
P 7300 1500
F 0 "C1" H 7415 1546 50 0000 L CNN
F 1 "0.1u" H 7415 1455 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 7338 1350 50 0001 C CNN
F 3 "~" H 7300 1500 50 0001 C CNN
1 7300 1500
1 0 0 -1
$EndComp
$Comp
L Device:C C2
U 1 1 60147309
P 7700 1500
F 0 "C2" H 7815 1546 50 0000 L CNN
F 1 "0.1u" H 7815 1455 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 7738 1350 50 0001 C CNN
F 3 "~" H 7700 1500 50 0001 C CNN
1 7700 1500
1 0 0 -1
$EndComp
$Comp
L Device:C C3
U 1 1 60147871
P 8100 1500
F 0 "C3" H 8215 1546 50 0000 L CNN
F 1 "0.1u" H 8215 1455 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 8138 1350 50 0001 C CNN
F 3 "~" H 8100 1500 50 0001 C CNN
1 8100 1500
1 0 0 -1
$EndComp
$Comp
L Device:C C4
U 1 1 60147B7A
P 8500 1500
F 0 "C4" H 8615 1546 50 0000 L CNN
F 1 "0.1u" H 8615 1455 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 8538 1350 50 0001 C CNN
F 3 "~" H 8500 1500 50 0001 C CNN
1 8500 1500
1 0 0 -1
$EndComp
Wire Wire Line
7300 1350 7700 1350
Connection ~ 7700 1350
Wire Wire Line
7700 1350 8100 1350
Connection ~ 8100 1350
Wire Wire Line
8100 1350 8500 1350
Wire Wire Line
8500 1650 8100 1650
Connection ~ 7700 1650
Wire Wire Line
7700 1650 7300 1650
Connection ~ 8100 1650
Wire Wire Line
8100 1650 7700 1650
$Comp
L power:GND #PWR08
U 1 1 60149B75
P 8500 1650
F 0 "#PWR08" H 8500 1400 50 0001 C CNN
F 1 "GND" H 8505 1477 50 0000 C CNN
F 2 "" H 8500 1650 50 0001 C CNN
F 3 "" H 8500 1650 50 0001 C CNN
1 8500 1650
1 0 0 -1
$EndComp
Connection ~ 8500 1650
Connection ~ 5650 4750
Wire Wire Line
5650 4750 5600 4750
Text Label 7750 4350 2 50 ~ 0
TMS
Text Label 7750 4450 2 50 ~ 0
TDI
Text Label 7750 4550 2 50 ~ 0
TDO
Text Label 7750 4650 2 50 ~ 0
TCK
Text Label 6400 4250 0 50 ~ 0
TDI
Text Label 6400 4350 0 50 ~ 0
TMS
Text Label 6400 4450 0 50 ~ 0
TCK
Text Label 6400 4550 0 50 ~ 0
TDO
$Comp
L power:GND #PWR06
U 1 1 6015097C
P 7750 4750
F 0 "#PWR06" H 7750 4500 50 0001 C CNN
F 1 "GND" V 7755 4622 50 0000 R CNN
F 2 "" H 7750 4750 50 0001 C CNN
F 3 "" H 7750 4750 50 0001 C CNN
1 7750 4750
0 1 1 0
$EndComp
$Comp
L Connector:Conn_01x06_Female J2
U 1 1 6014B057
P 7950 4550
F 0 "J2" H 7978 4526 50 0000 L CNN
F 1 "Buster" H 7978 4435 50 0000 L CNN
F 2 "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical" H 7950 4550 50 0001 C CNN
F 3 "" H 7950 4550 50 0001 C CNN
1 7950 4550
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR07
U 1 1 60151827
P 7750 4850
F 0 "#PWR07" H 7750 4700 50 0001 C CNN
F 1 "+3.3V" V 7765 4978 50 0000 L CNN
F 2 "" H 7750 4850 50 0001 C CNN
F 3 "" H 7750 4850 50 0001 C CNN
1 7750 4850
0 -1 -1 0
$EndComp
$Comp
L power:+3.3V #PWR05
U 1 1 60152460
P 7300 1350
F 0 "#PWR05" H 7300 1200 50 0001 C CNN
F 1 "+3.3V" H 7315 1523 50 0000 C CNN
F 2 "" H 7300 1350 50 0001 C CNN
F 3 "" H 7300 1350 50 0001 C CNN
1 7300 1350
1 0 0 -1
$EndComp
Connection ~ 7300 1350
Connection ~ 5800 1250
Wire Wire Line
5800 1250 5800 800
$Comp
L power:+3.3V #PWR04
U 1 1 60153D2F
P 5800 800
F 0 "#PWR04" H 5800 650 50 0001 C CNN
F 1 "+3.3V" H 5815 973 50 0000 C CNN
F 2 "" H 5800 800 50 0001 C CNN
F 3 "" H 5800 800 50 0001 C CNN
1 5800 800
1 0 0 -1
$EndComp
$Comp
L Regulator_Linear:AP7361C-33E U2
U 1 1 60156074
P 9700 1390
F 0 "U2" H 9700 1632 50 0000 C CNN
F 1 "TC1262-3.3V" H 9700 1541 50 0000 C CNN
F 2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" H 9700 1615 50 0001 C CIN
F 3 "https://ww1.microchip.com/downloads/en/DeviceDoc/21373C.pdf" H 9700 1340 50 0001 C CNN
1 9700 1390
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR010
U 1 1 6015942C
P 9700 1740
F 0 "#PWR010" H 9700 1490 50 0001 C CNN
F 1 "GND" H 9705 1567 50 0000 C CNN
F 2 "" H 9700 1740 50 0001 C CNN
F 3 "" H 9700 1740 50 0001 C CNN
1 9700 1740
1 0 0 -1
$EndComp
$Comp
L Device:C C5
U 1 1 6015BB09
P 9150 1540
F 0 "C5" H 9265 1586 50 0000 L CNN
F 1 "47u" H 9265 1495 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 9188 1390 50 0001 C CNN
F 3 "~" H 9150 1540 50 0001 C CNN
1 9150 1540
1 0 0 -1
$EndComp
$Comp
L Device:C C6
U 1 1 6015C4F0
P 10250 1540
F 0 "C6" H 10365 1586 50 0000 L CNN
F 1 "10u" H 10365 1495 50 0000 L CNN
F 2 "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" H 10288 1390 50 0001 C CNN
F 3 "~" H 10250 1540 50 0001 C CNN
1 10250 1540
1 0 0 -1
$EndComp
Wire Wire Line
9150 1390 9400 1390
Wire Wire Line
10250 1390 10000 1390
Wire Wire Line
9700 1740 9700 1690
Wire Wire Line
9700 1690 9150 1690
Connection ~ 9700 1690
Wire Wire Line
9700 1690 10250 1690
$Comp
L power:+3.3V #PWR011
U 1 1 60160CDB
P 10250 1390
F 0 "#PWR011" H 10250 1240 50 0001 C CNN
F 1 "+3.3V" H 10265 1563 50 0000 C CNN
F 2 "" H 10250 1390 50 0001 C CNN
F 3 "" H 10250 1390 50 0001 C CNN
1 10250 1390
1 0 0 -1
$EndComp
Connection ~ 10250 1390
$Comp
L power:+5V #PWR09
U 1 1 6016381B
P 9150 1390
F 0 "#PWR09" H 9150 1240 50 0001 C CNN
F 1 "+5V" H 9165 1563 50 0000 C CNN
F 2 "" H 9150 1390 50 0001 C CNN
F 3 "" H 9150 1390 50 0001 C CNN
1 9150 1390
1 0 0 -1
$EndComp
Connection ~ 9150 1390
$Comp
L power:+5V #PWR02
U 1 1 601644A8
P 1550 2800
F 0 "#PWR02" H 1550 2650 50 0001 C CNN
F 1 "+5V" H 1565 2973 50 0000 C CNN
F 2 "" H 1550 2800 50 0001 C CNN
F 3 "" H 1550 2800 50 0001 C CNN
1 1550 2800
1 0 0 -1
$EndComp
Text Label 4800 2950 2 50 ~ 0
~BG1
Text Label 4800 3050 2 50 ~ 0
~BG2
Text Label 4800 3150 2 50 ~ 0
~BG3
Text Label 4800 3250 2 50 ~ 0
~BG4
Text Label 4800 3350 2 50 ~ 0
~BG5
Text Label 4800 3450 2 50 ~ 0
~BR1
Text Label 4800 1550 2 50 ~ 0
~BR2
Text Label 4800 1650 2 50 ~ 0
~BR3
Text Label 4800 1750 2 50 ~ 0
~BR4
Text Label 4800 1850 2 50 ~ 0
~BR5
Text Label 4800 1950 2 50 ~ 0
~SLAVE1
Text Label 4800 2050 2 50 ~ 0
~SLAVE2
Text Label 4800 2150 2 50 ~ 0
~SLAVE3
Text Label 4800 2250 2 50 ~ 0
~SLAVE4
Text Label 4800 2350 2 50 ~ 0
~SLAVE5
Text Label 4800 2450 2 50 ~ 0
~BG
Text Label 4800 2550 2 50 ~ 0
~CDAC
Text Label 4800 2650 2 50 ~ 0
C1
Text Label 6400 1450 0 50 ~ 0
C3
Text Label 4800 2750 2 50 ~ 0
~C2
Text Label 6400 1550 0 50 ~ 0
~C4
Text Label 6400 1650 0 50 ~ 0
GBG
Text Label 4800 4150 2 50 ~ 0
DOE
Text Label 4800 4050 2 50 ~ 0
~DBOE
Text Label 4800 3950 2 50 ~ 0
D2P
Text Label 4800 3850 2 50 ~ 0
~RST
Text Label 4800 3750 2 50 ~ 0
~OWN
Text Label 4800 3650 2 50 ~ 0
~OVR
Text Label 4800 3550 2 50 ~ 0
~BOSS
Text Label 6400 4050 0 50 ~ 0
~UDS
Text Label 6400 3950 0 50 ~ 0
~LDS
Text Label 6400 3850 0 50 ~ 0
~AS
Text Label 6400 3750 0 50 ~ 0
READ
Text Label 6400 3650 0 50 ~ 0
~A23
Text Label 6400 3550 0 50 ~ 0
~A22
Text Label 6400 3450 0 50 ~ 0
~A21
Text Label 6400 3350 0 50 ~ 0
~A20
Text Label 6400 3250 0 50 ~ 0
~A19
Text Label 6400 3150 0 50 ~ 0
~CBG
Text Label 6400 3050 0 50 ~ 0
~CBR
Text Label 6400 2950 0 50 ~ 0
~BR
Text Label 6400 2750 0 50 ~ 0
~BEER
$EndSCHEMATC

3
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EESchema-DOCLIB Version 2.0
#
#End Doc Library

65
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Buster
#
DEF Buster U 0 40 Y Y 2 F N
F0 "U" -50 50 50 H V C CNN
F1 "Buster" 150 -3200 50 H V C CNN
F2 "Package_DIP:DIP-48_W15.24mm_Socket" 0 -200 50 H V C CNN
F3 "" 0 -200 50 H I C CNN
DRAW
S 850 -3150 0 0 1 1 0 f
S -150 -100 150 -650 2 1 0 f
X ~BR4 10 -100 -400 100 R 50 50 1 1 I
X ~BR5 11 -100 -500 100 R 50 50 1 1 I
X ~SLAVE1 12 -100 -650 100 R 50 50 1 1 I
X ~SLAVE2 13 -100 -750 100 R 50 50 1 1 I
X ~SLAVE3 14 -100 -850 100 R 50 50 1 1 I
X ~SLAVE4 15 -100 -950 100 R 50 50 1 1 I
X ~SLAVE5 16 -100 -1050 100 R 50 50 1 1 I
X ~BG 17 -100 -2150 100 R 50 50 1 1 I
X ~CDAC 18 -100 -2850 100 R 50 50 1 1 I
X C1 19 -100 -2950 100 R 50 50 1 1 I
X ~BG1 2 950 -100 100 L 50 50 1 1 O
X C3 20 -100 -3050 100 R 50 50 1 1 I
X ~C2 21 950 -3050 100 L 50 50 1 1 O
X ~C4 22 950 -2950 100 L 50 50 1 1 O
X ~GBG 23 950 -1950 100 L 50 50 1 1 O
X ~BEER 26 -100 -1750 100 R 50 50 1 1 I
X ~BR 27 950 -2250 100 L 50 50 1 1 O
X ~CBR 28 950 -2350 100 L 50 50 1 1 O
X ~CBG 29 950 -2150 100 L 50 50 1 1 O
X ~BG2 3 950 -200 100 L 50 50 1 1 O
X A19 30 -100 -1200 100 R 50 50 1 1 I
X A20 31 -100 -1300 100 R 50 50 1 1 I
X A21 32 -100 -1400 100 R 50 50 1 1 I
X A22 33 -100 -1500 100 R 50 50 1 1 I
X A23 34 -100 -1600 100 R 50 50 1 1 I
X READ 35 -100 -2050 100 R 50 50 1 1 I
X ~AS 36 -100 -2550 100 R 50 50 1 1 I
X ~LDS 37 -100 -1950 100 R 50 50 1 1 I
X ~UDS 38 -100 -1850 100 R 50 50 1 1 I
X ~BOSS 39 -100 -2250 100 R 50 50 1 1 I
X ~BG3 4 950 -300 100 L 50 50 1 1 O
X ~OVR 40 -100 -2350 100 R 50 50 1 1 I
X ~OWN 41 -100 -2450 100 R 50 50 1 1 I
X ~RST 42 -100 -2650 100 R 50 50 1 1 I
X TEST 43 950 -2650 100 L 50 50 1 1 I
X PTEST 44 950 -2550 100 L 50 50 1 1 I
X ~D2P 45 950 -1550 100 L 50 50 1 1 O
X ~DB0E 46 950 -800 100 L 50 50 1 1 O
X DOE 47 950 -900 100 L 50 50 1 1 O
X ~BG4 5 950 -400 100 L 50 50 1 1 O
X ~BG5 6 950 -500 100 L 50 50 1 1 O
X ~BR1 7 -100 -100 100 R 50 50 1 1 I
X ~BR2 8 -100 -200 100 R 50 50 1 1 I
X ~BR3 9 -100 -300 100 R 50 50 1 1 I
X GND 1 -50 -750 100 U 50 50 2 1 I
X GND 24 50 -750 100 U 50 50 2 1 W
X VCC 25 50 0 100 D 50 50 2 1 W
X VCC 48 -50 0 100 D 50 50 2 1 W
ENDDRAW
ENDDEF
#
#End Library

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(sym_lib_table
(lib (name Buster)(type Legacy)(uri ${KIPRJMOD}/Buster.lib)(options "")(descr ""))
)

189
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13
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# Bluster - A2000 CPLD Buster replacment
This is a replacement for the Buster IC used in the Amiga 2000
![PCB](Docs/PCB.png?raw=True)
### Bill of materials
|Component|Location|QTY|Link|
|---------|--------|---|------|
|XC9572XL-10VQ64C|U1|1|[Mouser](https://www.mouser.se/ProductDetail/217-C9572XL-10VQG64C)|
|TC1262-3.3|U2|1|[Mouser](https://www.mouser.com/ProductDetail/579-TC1262-3.3VDB)|
|4.7uF Ceramic Capacitor, 0805|C5|1|[Mouser](https://www.mouser.com/ProductDetail/187-CL21A475KOFNNNG)|
|0.1uF Ceramic Capacitor, 0805|C1-4|4|[Mouser](https://www.mouser.com/ProductDetail/963-EMF212B7104MGHT)|
|10uF Ceramic Capacitor, 0805|C6|1|[Mouser](https://www.mouser.com/ProductDetail/187-CL21A106KOQNNNG)|

51
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#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "ADDR<19>" LOC = "P46" ;
NET "ADDR<20>" LOC = "P47" ;
NET "ADDR<21>" LOC = "P48" ;
NET "ADDR<22>" LOC = "P49" ;
NET "ADDR<23>" LOC = "P50" ;
NET "ASn" LOC = "P52" ;
NET "BEERn" LOC = "P42" ;
NET "BG<1>" LOC = "P1" ;
NET "BG<2>" LOC = "P2" ;
NET "BG<3>" LOC = "P4" ;
NET "BG<4>" LOC = "P5" ;
NET "BG<5>" LOC = "P6" ;
NET "BGn" LOC = "P18" ;
NET "BOSSn" LOC = "P58" ;
NET "BR<1>" LOC = "P7" ;
NET "BR<2>" LOC = "P8" ;
NET "BR<3>" LOC = "P9" ;
NET "BR<4>" LOC = "P10" ;
NET "BR<5>" LOC = "P11" ;
NET "BRn" LOC = "P43" ;
NET "C1" LOC = "P20" ;
NET "C2n" LOC = "P23" ;
NET "C3" LOC = "P22" ;
NET "C4n" LOC = "P24" ;
NET "CBGn" LOC = "P45" ;
NET "CBRn" LOC = "P44" ;
NET "CDACn" LOC = "P19" ;
NET "D2Pn" LOC = "P62" ;
NET "DBOEn" LOC = "P63" ;
NET "DOE" LOC = "P64" ;
NET "GBGn" LOC = "P25" ;
NET "LDSn" LOC = "P57" ;
NET "OVRn" LOC = "P59" ;
NET "OWNn" LOC = "P60" ;
NET "READ" LOC = "P51" ;
NET "RESETn" LOC = "P61" ;
NET "SLV<1>" LOC = "P12" ;
NET "SLV<2>" LOC = "P13" ;
NET "SLV<3>" LOC = "P15" ;
NET "SLV<4>" LOC = "P16" ;
NET "SLV<5>" LOC = "P17" ;
NET "UDSn" LOC = "P56" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

173
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/*
BUSTIN' MAKES ME FEEL GOOD!
Bluster - CPLD Replacement for Amiga 2000's Buster
Copyright 2021 Matthew Harlum
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//`define badbuster // Emulate 1st rev of Buster that had a bug requiring buster tower
module Buster(
input [5:1] BR,
input [5:1] SLV,
input [23:19] ADDR,
input UDSn,
input LDSn,
input READ,
input BGn,
input BOSSn,
input OVRn,
input OWNn,
input ASn,
input RESETn,
input CDACn,
input C1,
input C3,
inout BEERn,
inout CBRn,
inout CBGn,
output DOE,
output DBOEn,
output D2Pn,
output GBGn,
output reg BRn,
output reg [5:1] BG,
output reg C4n,
output reg C2n
);
// Clocks
wire C7M;
assign C7M = !(C1 ^ C3);
always @(posedge CDACn)
begin
C2n <= !C1;
end
always @(negedge CDACn)
begin
C4n <= !C3;
end
// Collision
wire nocollision;
wire mainboard;
// Reserved address ranges
// Buster triggers a bus error if a PIC answers to these addresses (unless it asserts OVR)
assign mainboard = (
ADDR[23:21] == 3'b000 | // $000000-0FFFFF - Chip RAM
ADDR[23:21] == 3'b101 | // $A00000-BFFFFF - RESERVED
ADDR[23:21] == 3'b110 | // $C00000-DFFFFF - Pseudo-Fast RAM
ADDR[23:19] == 5'b11100 | // $E00000-E7FFFF - RESERVED
ADDR[23:19] == 5'b11111 // $F80000-FFFFFF - Kickstart ROM
) & !ASn & RESETn & OVRn;
// If more than one PIC answers at the same time throw a bus error.
assign nocollision = (!SLV[5] ^ !SLV[4] ^ !SLV[3] ^ !SLV[2] ^ !SLV[1] ^ mainboard) | (SLV[5] & SLV[4] & SLV[3] & SLV[2] & SLV[1] & !mainboard);
assign BEERn = (!nocollision & RESETn) ? 1'b0 : 1'bZ;
/// Steering
// Delayed ASn needed for buffer control and DOE
// Based on the circuitry of the German A2000
// Not really sure why it uses C2? Perhaps they were worried about metastability
reg ASnd1; // ASn delayed until C2
reg ASnd2; // ASnd1 delayed until C7M
always @(negedge C2n or posedge ASn)
begin
if (ASn) begin
ASnd1 <= 1;
end else begin
ASnd1 <= ASn;
end
end
always @(posedge C7M or posedge ASn)
begin
if (ASn) begin
ASnd2 <= 1;
end else begin
ASnd2 <= ASnd1;
end
end
assign DOE = !ASnd2;
// Data buffer direction control
assign D2Pn = !(
OWNn & READ & (!SLV[1]|!SLV[2]|!SLV[3]|!SLV[4]|!SLV[5]) | // CPU reading from Zorro card
!OWNn & !READ & SLV[1] & SLV[2] & SLV[3] & SLV[4] & SLV[5] // Zorro master writing to mainboard
`ifndef badbuster
| !OWNn & (!SLV[1] | !SLV[2] | !SLV[3] | !SLV[4] | !SLV[5]) // Zorro to Zorro
`endif
);
// Need to double-check this against real Buster, initial look seems to always enable the buffer for every access. need to confirm...
// Data buffer output enable
assign DBOEn = !(
/* // Based on pal equations in A500/2000 TRM
!ASn & !READ & BEERn & OWNn | // CPU writing to Zorro
(!UDSn|!LDSn) & READ & !ASnd2 & BEERn & OWNn | // CPU reading from Zorro
!ASn & !READ & BEERn & !OWNn & SLV[1] & SLV[2] & SLV[3] & SLV[4] & SLV[5] | // Zorro DMA to mainboard
(!UDSn|!LDSn) & READ & !ASnd2 & BEERn & !OWNn & SLV[1] & SLV[2] & SLV[3] & SLV[4] & SLV[5] // Zorro DMA from mainboard
*/
// Observed behavior on Rev 4.4 B2000
!ASn & !READ & BEERn
| (!UDSn|!LDSn) & READ & !ASnd2 & BEERn
);
// Arbitration
// Here be dragons
//
// I am not 100% sure about the coprocessor logic here and have no good way of testing it.
reg BGOLDn;
reg COPBG;
wire BGRANT;
// If BOSS asserted, switch the direction of CBG and CBR
assign CBGn = (BOSSn) ? COPBG : 1'bZ;
assign CBRn = (!BOSSn) ? BRn : 1'bZ;
assign BGRANT = (BOSSn) ? BGn : CBGn;
assign GBGn = (BOSSn) ? BGn : CBGn;
always @(posedge C7M)
begin
BGOLDn <= BGRANT; // Store old state of BG
// Generate requests & hold grants
// Coprocessor has highest priority
COPBG = !(( RESETn & !BGRANT & BGOLDn & BOSSn & !CBRn ) | (RESETn & !BGn & !COPBG));
BG[1] = !(( RESETn & !BGRANT & BGOLDn & (CBRn | !BOSSn) & !BR[1] ) | (RESETn & !BGRANT & !BG[1]));
BG[2] = !(( RESETn & !BGRANT & BGOLDn & (CBRn | !BOSSn) & BR[1] & !BR[2] ) | (RESETn & !BGRANT & !BG[2]));
BG[3] = !(( RESETn & !BGRANT & BGOLDn & (CBRn | !BOSSn) & BR[1] & BR[2] & !BR[3] ) | (RESETn & !BGRANT & !BG[3]));
BG[4] = !(( RESETn & !BGRANT & BGOLDn & (CBRn | !BOSSn) & BR[1] & BR[2] & BR[3] & !BR[4] ) | (RESETn & !BGRANT & !BG[4]));
BG[5] = !(( RESETn & !BGRANT & BGOLDn & (CBRn | !BOSSn) & BR[1] & BR[2] & BR[3] & BR[4] & !BR[5] ) | (RESETn & !BGRANT & !BG[5]));
BRn <= (!RESETn | ((CBRn | !BOSSn) & BR[1] & BR[2] & BR[3] & BR[4] & BR[5]));
end
endmodule