LIV2/A4092-dev
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156 Commits

Author SHA1 Message Date
Stefan Reinauer
8b470ec6b1 Update kibot config 2025-06-14 21:53:25 -07:00
Stefan Reinauer
1de0fdb589 Fix up Makefile / kibot calls 2025-06-14 00:15:44 -07:00
Stefan Reinauer
15fd667096 Remove spaces from JLCPCB part numbers 2025-06-13 11:11:11 -07:00
Stefan Reinauer
c8d9cc29b7 Allow bridged solder mask for Zorro3 connector 2025-06-13 10:53:07 -07:00
Stefan Reinauer
0b4546da1a Fix 3d model for TSSOP-48 2025-06-12 22:49:35 -07:00
Stefan Reinauer
3a0176d311 Fix 3d model path 2025-06-12 22:41:31 -07:00
Stefan Reinauer
c4973d4cc6 Update Backpanel for smaller footprint 2025-06-09 22:55:53 -07:00
Stefan Reinauer
ae9092d0e7 Add rotations for all parts 2025-06-09 00:36:47 -07:00
Stefan Reinauer
50c21e0c83 Fix up capacitor array footprint 
家裡創 did not like the digikey footprint.
 2025-06-08 23:22:41 -07:00
Stefan Reinauer
ebc04245bb Finish DS2107 terminator 2025-06-08 21:46:52 -07:00
Stefan Reinauer
21ea04db71 Update DEV version of the terminator 
with switch for experimenting w/ mosfet
 2025-06-08 17:19:40 -07:00
Stefan Reinauer
6c63135045 Update LT1118-2.85 based terminator 2025-06-08 16:19:50 -07:00
Stefan Reinauer
890b881e16 Update PCB 2025-06-06 13:22:13 -07:00
Stefan Reinauer
432fbb9239 Update footprints 2025-06-06 12:54:23 -07:00
Monse
64a2fb03db U1-4 routing completed 2025-06-06 12:02:36 -07:00
Stefan Reinauer
e9f4af8904 Update to use new footprint for U1,2,3,4 2025-06-06 07:54:29 -07:00
Stefan Reinauer
527d8f134f Add SN74ABT16543DGGR symbol / footprint 2025-06-06 07:52:03 -07:00
Stefan Reinauer
c7179e01c9 Update PCB from Schematics, new image 2025-06-05 21:04:26 -07:00
Monse
411d3726cf Removed fiducial copper and copper sliver rule 2025-06-01 14:32:01 -07:00
Stefan Reinauer
8e7f750e63 Update JLCPCB part numbers 
Move to available and, if possible, basic parts
 2025-06-01 12:38:42 -07:00
Stefan Reinauer
3c65920347 Fix 3d image path in footprints 2025-05-31 22:41:21 -07:00
Monse
94f827d1ed L4/L3 cleanup 2025-05-31 21:22:38 -07:00
Monse
d22d7f7d0d A4092 text Top cutout 2025-05-31 17:11:19 -07:00
Monse
fff5e8e57a DRCs checks 2025-05-30 10:25:55 -07:00
Stefan Reinauer
0b40860c76 Move A4092 main PCB to subdirectory 
- Move current main design to A4092
- Add fp-lib-table and sym-lib-table with correct paths to
  each sub directory
 2025-05-29 14:13:09 -07:00
Stefan Reinauer
160f629b66 Restructure directories, Add Terminator designs 2025-05-29 14:01:20 -07:00
Monse
c767d02364 Imported netlist 2025-05-28 21:21:52 -07:00
Monse
32267e49b8 board cleanup 2025-05-28 19:11:11 -07:00
Stefan Reinauer
3dae3b237d Add bypass cap for Berg connector 2025-05-27 23:40:00 -07:00
Monse
3e4f35d1b9 Imported latest netlist 2025-05-27 22:35:58 -07:00
Monse
f25e716a9a DRCs checks 2025-05-27 22:28:54 -07:00
Stefan Reinauer
e462978d1c Review fixes on scsi2 page 
* R11 is 22 Ohm not 120 in the original schematics
* FETCH# is NC in the original, not V5
 2025-05-27 22:25:26 -07:00
Monse
d73007ccb7 routing is completed 2025-05-27 22:19:57 -07:00
Monse
8d241f9578 Routing in progress 2025-05-27 22:14:19 -07:00
Stefan Reinauer
87926617af Fix 3V3 -> V3_3 2025-05-27 20:57:37 -07:00
Stefan Reinauer
5e84bdbec2 Re-sort address lines 2025-05-27 20:53:30 -07:00
Monse
05b7b7bcc4 Routing in progress 2025-05-27 20:46:41 -07:00
Stefan Reinauer
ae3d69ead8 Add D[12..15] and A[9..16,20] to CPLD 2025-05-27 19:58:01 -07:00
Stefan Reinauer
e5eff60cdc Recreate PCB from schematics 
Changed footprints to sync cleanly on the Mac
 2025-05-27 14:58:40 -07:00
Stefan Reinauer
25593396b6 Hook up Flash page 2025-05-27 14:46:59 -07:00
Stefan Reinauer
c698792dfd Add SPI flash option and move flash to its own page 2025-05-27 08:28:28 -07:00
Monse
bfe8762e38 GND vias 2025-05-26 18:08:31 -07:00
Stefan Reinauer
aaf76db883 Add fiducials and clean up schematics 2025-05-25 23:46:42 -07:00
Monse
5847d02536 routing is completed 2025-05-25 22:09:45 -07:00
Monse
221884abca V5 routing in progress 2025-05-25 19:20:11 -07:00
Stefan Reinauer
a7dcbaf6fa Minor trace and silkscreen fixes 2025-05-23 22:52:11 -07:00
Stefan Reinauer
e5d209f673 Merge colinear tracks 2025-05-23 21:14:59 -07:00
Stefan Reinauer
33bb615178 Update PCB from schematics 2025-05-23 18:33:56 -07:00
Stefan Reinauer
f99dcb17ac Clean up schematics 2025-05-23 16:42:07 -07:00
Stefan Reinauer
c3d6261690 Update footprint graphics 
Unify using a dot rather than asterisk for pin 1
Remove pin 1 designator for ferrites
 2025-05-23 16:40:23 -07:00