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PR target/84786

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* config/i386/sse.md (vshift_count): New mode attr.
	(<shift_insn><mode>3<mask_name>): Use <vshift_count>N instead of vN
	as last operand's constraint for VI2_AVX2_AVX512BW shifts.  Use YvN
	instead of vN as last operand's constraint for VI48_AVX2 shifts.

	* gcc.target/i386/avx512f-pr84786-3.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@262103 138bc75d-0d04-0410-961f-82ee72b054a4
This commit is contained in:
jakub 2018-06-25 17:55:15 +00:00
parent 49b51f41d2
commit 9b8452d997
4 changed files with 85 additions and 7 deletions
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6
gcc/ChangeLog
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@ -1,5 +1,11 @@
2018-06-25 Jakub Jelinek <jakub@redhat.com>
PR target/84786
* config/i386/sse.md (vshift_count): New mode attr.
(<shift_insn><mode>3<mask_name>): Use <vshift_count>N instead of vN
as last operand's constraint for VI2_AVX2_AVX512BW shifts. Use YvN
instead of vN as last operand's constraint for VI48_AVX2 shifts.
Backported from mainline
2018-06-20 Jakub Jelinek <jakub@redhat.com>

33
gcc/config/i386/sse.md
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@ -10546,30 +10546,49 @@
(const_string "0")))
(set_attr "mode" "<sseinsnmode>")])
(define_mode_attr vshift_count
[(V32HI "v") (V16HI "x") (V8HI "x")])
(define_insn "<shift_insn><mode>3<mask_name>"
[(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v")
[(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v,v")
(any_lshift:VI2_AVX2_AVX512BW
(match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v")
(match_operand:DI 2 "nonmemory_operand" "xN,vN")))]
(match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v,v")
(match_operand:DI 2 "nonmemory_operand" "xN,<vshift_count>N,vN")))]
"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
[(set_attr "isa" "noavx,avx,avx512vl")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
(set_attr "prefix_data16" "1,*,*")
(set_attr "prefix" "orig,vex,vex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*<shift_insn><mode>3<mask_name>_1"
[(set (match_operand:VI48_AVX2 0 "register_operand" "=v")
(any_lshift:VI48_AVX2
(match_operand:VI48_AVX2 1 "register_operand" "v")
(match_operand:DI 2 "nonmemory_operand" "vN")))]
"TARGET_AVX512BW && TARGET_AVX512VL"
"vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseishft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<shift_insn><mode>3<mask_name>"
[(set (match_operand:VI48_AVX2 0 "register_operand" "=x,x,v")
(any_lshift:VI48_AVX2
(match_operand:VI48_AVX2 1 "register_operand" "0,x,v")
(match_operand:DI 2 "nonmemory_operand" "xN,xN,vN")))]
(match_operand:DI 2 "nonmemory_operand" "xN,xN,xN")))]
"TARGET_SSE2 && <mask_mode512bit_condition>"
"@
p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}

3
gcc/testsuite/ChangeLog
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@ -1,5 +1,8 @@
2018-06-25 Jakub Jelinek <jakub@redhat.com>
PR target/84786
* gcc.target/i386/avx512f-pr84786-3.c: New test.
Backported from mainline
2018-06-20 Jakub Jelinek <jakub@redhat.com>

50
gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c Normal file
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@ -0,0 +1,50 @@
/* PR target/84786 */
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-mavx512f -mno-avx512vl -O2" } */
#include <x86intrin.h>
__m512i v;
__m128i w;
__m128i
foo (__m128i x, int y)
{
__m128i z;
#define A(n) register __m512i zmm##n __asm ("zmm" #n);
#define B A(1) A(2) A(3) A(4) A(5) A(6) A(7) \
A(8) A(9) A(10) A(11) A(12) A(13) A(14)
B
#undef A
#define A(n) asm volatile ("" : "=v" (zmm##n) : "0" (v));
B
asm volatile ("" : "=x" (z) : "0" (w));
x = _mm_srli_epi16 (x, y);
asm volatile ("" : : "x" (z));
#undef A
#define A(n) asm volatile ("" : : "v" (zmm##n));
B
return x;
}
__m256i
bar (__m256i x, int y)
{
__m128i z;
#undef A
#define A(n) register __m512i zmm##n __asm ("zmm" #n);
B
#undef A
#define A(n) asm volatile ("" : "=v" (zmm##n) : "0" (v));
B
asm volatile ("" : "=x" (z) : "0" (w));
x = _mm256_slli_epi16 (x, y);
asm volatile ("" : : "x" (z));
#undef A
#define A(n) asm volatile ("" : : "v" (zmm##n));
B
return x;
}
/* { dg-final { scan-assembler-not "vpsrlw\[\^\n\r]*xmm(1\[6-9]|\[23]\[0-9])" } } */
/* { dg-final { scan-assembler-not "vpsllw\[\^\n\r]*xmm(1\[6-9]|\[23]\[0-9])" } } */