mirror of
https://github.com/LIV2/WinUAE.git
synced 2025-12-06 00:12:52 +00:00
64812 lines
1.8 MiB
64812 lines
1.8 MiB
#include "sysconfig.h"
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#include "sysdeps.h"
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#include "options.h"
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#include "memory.h"
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#include "custom.h"
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#include "events.h"
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#include "newcpu.h"
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#include "cpu_prefetch.h"
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#include "cputbl.h"
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#define SET_ALWAYS_CFLG(x) SET_CFLG(x)
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#define SET_ALWAYS_NFLG(x) SET_NFLG(x)
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/* OR.B #<data>.B,Dn */
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uae_u32 REGPARAM2 op_0000_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s8 src = get_dibyte(2);
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uae_s8 dst = m68k_dreg(regs, dstreg);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
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m68k_incpc(4);
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return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.B #<data>.B,(An) */
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uae_u32 REGPARAM2 op_0010_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg);
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uae_s8 dst = get_byte(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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m68k_incpc(4);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.B #<data>.B,(An)+ */
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uae_u32 REGPARAM2 op_0018_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg);
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uae_s8 dst = get_byte(dsta);
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m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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m68k_incpc(4);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.B #<data>.B,-(An) */
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uae_u32 REGPARAM2 op_0020_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
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uae_s8 dst = get_byte(dsta);
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m68k_areg(regs, dstreg) = dsta;
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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m68k_incpc(4);
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return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.B #<data>.B,(d16,An) */
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uae_u32 REGPARAM2 op_0028_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
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uae_s8 dst = get_byte(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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m68k_incpc(6);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* OR.B #<data>.B,(d8,An,Xn) */
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uae_u32 REGPARAM2 op_0030_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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m68k_incpc(4);
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dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
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uae_s8 dst = get_byte(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 2,0 */
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/* OR.B #<data>.B,(xxx).W */
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uae_u32 REGPARAM2 op_0038_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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dsta = (uae_s32)(uae_s16)get_diword(4);
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uae_s8 dst = get_byte(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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m68k_incpc(6);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* OR.B #<data>.B,(xxx).L */
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uae_u32 REGPARAM2 op_0039_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_s8 src = get_dibyte(2);
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uaecptr dsta;
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dsta = get_dilong(4);
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uae_s8 dst = get_byte(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s8)(src)) == 0);
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SET_NFLG(((uae_s8)(src)) < 0);
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put_byte(dsta, src);
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m68k_incpc(8);
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return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 8 0,0 */
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/* ORSR.B #<data>.W */
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uae_u32 REGPARAM2 op_003c_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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MakeSR();
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uae_s16 src = get_diword(2);
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src &= 0xFF;
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regs.sr |= src;
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MakeFromSR();
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m68k_incpc(4);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.W #<data>.W,Dn */
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uae_u32 REGPARAM2 op_0040_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s16 src = get_diword(2);
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uae_s16 dst = m68k_dreg(regs, dstreg);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
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m68k_incpc(4);
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return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.W #<data>.W,(An) */
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uae_u32 REGPARAM2 op_0050_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg);
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uae_s16 dst = get_word(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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m68k_incpc(4);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.W #<data>.W,(An)+ */
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uae_u32 REGPARAM2 op_0058_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg);
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uae_s16 dst = get_word(dsta);
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m68k_areg(regs, dstreg) += 2;
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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m68k_incpc(4);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.W #<data>.W,-(An) */
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uae_u32 REGPARAM2 op_0060_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg) - 2;
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uae_s16 dst = get_word(dsta);
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m68k_areg(regs, dstreg) = dsta;
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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m68k_incpc(4);
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return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.W #<data>.W,(d16,An) */
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uae_u32 REGPARAM2 op_0068_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
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uae_s16 dst = get_word(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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m68k_incpc(6);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* OR.W #<data>.W,(d8,An,Xn) */
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uae_u32 REGPARAM2 op_0070_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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m68k_incpc(4);
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dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
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uae_s16 dst = get_word(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 2,0 */
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/* OR.W #<data>.W,(xxx).W */
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uae_u32 REGPARAM2 op_0078_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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dsta = (uae_s32)(uae_s16)get_diword(4);
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uae_s16 dst = get_word(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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m68k_incpc(6);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* OR.W #<data>.W,(xxx).L */
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uae_u32 REGPARAM2 op_0079_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_s16 src = get_diword(2);
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uaecptr dsta;
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dsta = get_dilong(4);
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uae_s16 dst = get_word(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s16)(src)) == 0);
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SET_NFLG(((uae_s16)(src)) < 0);
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put_word(dsta, src);
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m68k_incpc(8);
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return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 8 0,0 */
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/* ORSR.W #<data>.W */
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uae_u32 REGPARAM2 op_007c_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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if (!regs.s) {
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Exception(8);
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return 0;
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}
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MakeSR();
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uae_s16 src = get_diword(2);
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if(regs.t0) check_t0_trace();
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regs.sr |= src;
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MakeFromSR();
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m68k_incpc(4);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* OR.L #<data>.L,Dn */
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uae_u32 REGPARAM2 op_0080_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s32 src;
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src = get_dilong(2);
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uae_s32 dst = m68k_dreg(regs, dstreg);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s32)(src)) == 0);
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SET_NFLG(((uae_s32)(src)) < 0);
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m68k_dreg(regs, dstreg) = (src);
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m68k_incpc(6);
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return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* OR.L #<data>.L,(An) */
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uae_u32 REGPARAM2 op_0090_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s32 src;
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src = get_dilong(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg);
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uae_s32 dst = get_long(dsta);
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s32)(src)) == 0);
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SET_NFLG(((uae_s32)(src)) < 0);
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put_long(dsta, src);
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m68k_incpc(6);
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return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* OR.L #<data>.L,(An)+ */
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uae_u32 REGPARAM2 op_0098_0_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_s32 src;
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src = get_dilong(2);
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uaecptr dsta;
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dsta = m68k_areg(regs, dstreg);
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uae_s32 dst = get_long(dsta);
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m68k_areg(regs, dstreg) += 4;
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src |= dst;
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CLEAR_CZNV();
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SET_ZFLG(((uae_s32)(src)) == 0);
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SET_NFLG(((uae_s32)(src)) < 0);
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put_long(dsta, src);
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m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* OR.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_00a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* OR.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_00a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* OR.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_00b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* OR.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_00b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* OR.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_00b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(10);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* CHK2.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
m68k_incpc(4);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CHK2.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
m68k_incpc(8);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.B #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.B #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_00fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s8)get_byte(dsta);
|
|
upper = (uae_s32)(uae_s8)get_byte(dsta + 1);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BTST.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_0100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVPMR.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_0108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_u16 val = (get_byte(mempa) & 0xff) << 8;
|
|
val |= (get_byte(mempa + 2) & 0xff);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_0110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BTST.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_0118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BTST.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_0120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BTST.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* BTST.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BTST.B Dn,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_013a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = 2;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 2;
|
|
dsta += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B Dn,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_013b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = 3;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* BTST.B Dn,#<data>.B */
|
|
uae_u32 REGPARAM2 op_013c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = get_dibyte(2);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_0140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVPMR.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_0148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_u32 val = (get_byte(mempa) & 0xff) << 24;
|
|
val |= (get_byte(mempa + 2) & 0xff) << 16;
|
|
val |= (get_byte(mempa + 4) & 0xff) << 8;
|
|
val |= (get_byte(mempa + 6) & 0xff);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((4 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_0150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCHG.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_0158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCHG.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_0160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCHG.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* BCHG.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCLR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_0180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVPRM.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
put_byte(mempa, src >> 8);
|
|
put_byte(mempa + 2, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_0190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_0198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_01a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_01a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_01b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* BCLR.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_01b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_01b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BSET.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_01c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVPRM.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_01c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
put_byte(mempa, src >> 24);
|
|
put_byte(mempa + 2, src >> 16);
|
|
put_byte(mempa + 4, src >> 8);
|
|
put_byte(mempa + 6, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((4 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_01d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BSET.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_01d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BSET.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_01e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BSET.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_01e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_01f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* BSET.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_01f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_01f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_0200_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B #<data>.B,(An) */
|
|
uae_u32 REGPARAM2 op_0210_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B #<data>.B,(An)+ */
|
|
uae_u32 REGPARAM2 op_0218_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B #<data>.B,-(An) */
|
|
uae_u32 REGPARAM2 op_0220_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B #<data>.B,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0228_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0230_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* AND.B #<data>.B,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0238_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.B #<data>.B,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0239_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* ANDSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_023c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
src |= 0xff00;
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0240_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0250_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0258_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0260_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0268_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0270_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* AND.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0278_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0279_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* ANDSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_027c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0280_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.L #<data>.L,(An) */
|
|
uae_u32 REGPARAM2 op_0290_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.L #<data>.L,(An)+ */
|
|
uae_u32 REGPARAM2 op_0298_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_02a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_02a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* AND.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_02b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* AND.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_02b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* AND.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_02b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(10);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* CHK2.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
m68k_incpc(4);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CHK2.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
m68k_incpc(8);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.W #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.W #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_02fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = (uae_s32)(uae_s16)get_word(dsta);
|
|
upper = (uae_s32)(uae_s16)get_word(dsta + 2);
|
|
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* SUB.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_0400_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B #<data>.B,(An) */
|
|
uae_u32 REGPARAM2 op_0410_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B #<data>.B,(An)+ */
|
|
uae_u32 REGPARAM2 op_0418_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B #<data>.B,-(An) */
|
|
uae_u32 REGPARAM2 op_0420_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B #<data>.B,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0428_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0430_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* SUB.B #<data>.B,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0438_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.B #<data>.B,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0439_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* SUB.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0440_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0450_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0458_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0460_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0468_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0470_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* SUB.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0478_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0479_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* SUB.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0480_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L #<data>.L,(An) */
|
|
uae_u32 REGPARAM2 op_0490_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L #<data>.L,(An)+ */
|
|
uae_u32 REGPARAM2 op_0498_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_04a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_04a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* SUB.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_04b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* SUB.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_04b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* SUB.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_04b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(10);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* CHK2.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
m68k_incpc(4);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CHK2.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
m68k_incpc(8);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
m68k_incpc(6);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK2.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_04fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
|
|
lower = get_long(dsta); upper = get_long(dsta + 4);
|
|
SET_CFLG(0);
|
|
SET_ZFLG(0);
|
|
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
|
|
if(upper == reg || lower == reg) {
|
|
SET_ZFLG(1);
|
|
}else{
|
|
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
|
|
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
|
|
}
|
|
if ((extra & 0x800) && GET_CFLG()) {
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* ADD.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_0600_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B #<data>.B,(An) */
|
|
uae_u32 REGPARAM2 op_0610_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B #<data>.B,(An)+ */
|
|
uae_u32 REGPARAM2 op_0618_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B #<data>.B,-(An) */
|
|
uae_u32 REGPARAM2 op_0620_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B #<data>.B,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0628_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0630_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* ADD.B #<data>.B,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0638_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.B #<data>.B,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0639_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* ADD.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0640_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0650_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0658_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0660_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0668_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0670_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* ADD.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0678_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0679_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* ADD.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0680_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L #<data>.L,(An) */
|
|
uae_u32 REGPARAM2 op_0690_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L #<data>.L,(An)+ */
|
|
uae_u32 REGPARAM2 op_0698_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_06a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_06a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* ADD.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_06b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* ADD.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_06b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* ADD.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_06b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(10);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* RTM.L Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* RTM.L An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CALLM.L (d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_06fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
op_illg(opcode);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* BTST.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0800_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0810_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0818_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0820_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0828_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0830_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* BTST.B #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0838_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0839_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(8);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_083a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BTST.B #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_083b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* BCHG.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0840_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0850_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0858_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0860_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0868_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0870_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* BCHG.B #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0878_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0879_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* BCLR.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0880_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0890_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0898_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_08a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_08a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_08b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* BCLR.B #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_08b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_08b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* BSET.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_08c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_08d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_08d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_08e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_08e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BSET.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_08f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* BSET.B #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_08f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BSET.B #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_08f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EOR.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_0a00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B #<data>.B,(An) */
|
|
uae_u32 REGPARAM2 op_0a10_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B #<data>.B,(An)+ */
|
|
uae_u32 REGPARAM2 op_0a18_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B #<data>.B,-(An) */
|
|
uae_u32 REGPARAM2 op_0a20_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B #<data>.B,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0a28_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0a30_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* EOR.B #<data>.B,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0a38_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.B #<data>.B,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0a39_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a3c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0a40_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0a50_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0a58_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0a60_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0a68_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0a70_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* EOR.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0a78_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0a79_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a7c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0a80_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.L #<data>.L,(An) */
|
|
uae_u32 REGPARAM2 op_0a90_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.L #<data>.L,(An)+ */
|
|
uae_u32 REGPARAM2 op_0a98_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_0aa0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0aa8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EOR.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0ab0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* EOR.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0ab8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EOR.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0ab9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(10);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* CAS.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ad0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ad8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ae0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ae8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(8);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CMP.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_0c00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B #<data>.B,(An) */
|
|
uae_u32 REGPARAM2 op_0c10_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B #<data>.B,(An)+ */
|
|
uae_u32 REGPARAM2 op_0c18_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B #<data>.B,-(An) */
|
|
uae_u32 REGPARAM2 op_0c20_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B #<data>.B,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0c28_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0c30_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* CMP.B #<data>.B,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0c38_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.B #<data>.B,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0c39_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(8);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* CMP.B #<data>.B,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0c3a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CMP.B #<data>.B,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0c3b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CMP.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0c40_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0c50_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0c58_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_0c60_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0c68_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0c70_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* CMP.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0c78_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0c79_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(8);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* CMP.W #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0c7a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CMP.W #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0c7b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CMP.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0c80_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.L #<data>.L,(An) */
|
|
uae_u32 REGPARAM2 op_0c90_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.L #<data>.L,(An)+ */
|
|
uae_u32 REGPARAM2 op_0c98_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_0ca0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0ca8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* CMP.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0cb0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* CMP.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_0cb8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* CMP.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_0cb9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(10);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* CMP.L #<data>.L,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 6;
|
|
dsta += (uae_s32)(uae_s16)get_diword(6);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CMP.L #<data>.L,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cbb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(4);
|
|
op_unimpl (opcode);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cd8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
cpu_restore_fixup();
|
|
m68k_incpc(4);
|
|
op_unimpl (opcode);
|
|
mmufixup[0].reg = -1;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ce0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
cpu_restore_fixup();
|
|
m68k_incpc(4);
|
|
op_unimpl (opcode);
|
|
mmufixup[0].reg = -1;
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ce8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(6);
|
|
op_unimpl (opcode);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 12 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
op_unimpl (opcode);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(6);
|
|
op_unimpl (opcode);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 12 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
if ((dsta & 1) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(8);
|
|
op_unimpl (opcode);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(8);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 16 0,0 */
|
|
|
|
#endif
|
|
/* CAS2.W #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cfc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 extra;
|
|
extra = get_dilong(2);
|
|
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
|
|
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
|
|
uae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);
|
|
uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
|
|
int flgo = ((uae_s16)(dst1)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg(regs, extra & 7)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, extra & 7))) < 0;
|
|
int flgo = ((uae_s16)(dst2)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, extra & 7))) > ((uae_u16)(dst2)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(rn2, m68k_dreg(regs, (extra >> 6) & 7));
|
|
put_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));
|
|
}
|
|
}
|
|
if (!GET_ZFLG()) {
|
|
m68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);
|
|
m68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e10_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e18_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e20_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e28_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e30_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e38_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e39_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e50_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e58_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e60_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e68_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e70_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_word(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e78_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e79_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e90_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e98_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ea0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ea8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_long(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ed0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(4);
|
|
op_unimpl (opcode);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(4);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ed8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
cpu_restore_fixup();
|
|
m68k_incpc(4);
|
|
op_unimpl (opcode);
|
|
mmufixup[0].reg = -1;
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ee0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
cpu_restore_fixup();
|
|
m68k_incpc(4);
|
|
op_unimpl (opcode);
|
|
mmufixup[0].reg = -1;
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ee8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(6);
|
|
op_unimpl (opcode);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(6);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 12 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
op_unimpl (opcode);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(6);
|
|
op_unimpl (opcode);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(6);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 12 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
if ((dsta & 3) && currprefs.int_no_unimplemented && get_cpu_model() == 68060) {
|
|
m68k_incpc(8);
|
|
op_unimpl (opcode);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(8);
|
|
return (40 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 16 0,0 */
|
|
|
|
#endif
|
|
/* CAS2.L #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0efc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 extra;
|
|
extra = get_dilong(2);
|
|
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
|
|
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
|
|
uae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);
|
|
uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
|
|
int flgo = ((uae_s32)(dst1)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg(regs, extra & 7)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, extra & 7))) < 0;
|
|
int flgo = ((uae_s32)(dst2)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, extra & 7))) > ((uae_u32)(dst2)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(rn2, m68k_dreg(regs, (extra >> 6) & 7));
|
|
put_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));
|
|
}
|
|
}
|
|
if (!GET_ZFLG()) {
|
|
m68k_dreg(regs, (extra >> 16) & 7) = dst1;
|
|
m68k_dreg(regs, (extra >> 0) & 7) = dst2;
|
|
}
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVE.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_1000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An),Dn */
|
|
uae_u32 REGPARAM2 op_1010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_1018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B -(An),Dn */
|
|
uae_u32 REGPARAM2 op_1020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_1028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_1030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_1038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_1039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_103a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_103b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_103c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_1080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An),(An) */
|
|
uae_u32 REGPARAM2 op_1090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An)+,(An) */
|
|
uae_u32 REGPARAM2 op_1098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B -(An),(An) */
|
|
uae_u32 REGPARAM2 op_10a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (d16,An),(An) */
|
|
uae_u32 REGPARAM2 op_10a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_10b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (xxx).W,(An) */
|
|
uae_u32 REGPARAM2 op_10b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,(An) */
|
|
uae_u32 REGPARAM2 op_10b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),(An) */
|
|
uae_u32 REGPARAM2 op_10ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_10bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B #<data>.B,(An) */
|
|
uae_u32 REGPARAM2 op_10bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_10c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An),(An)+ */
|
|
uae_u32 REGPARAM2 op_10d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An)+,(An)+ */
|
|
uae_u32 REGPARAM2 op_10d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B -(An),(An)+ */
|
|
uae_u32 REGPARAM2 op_10e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (d16,An),(An)+ */
|
|
uae_u32 REGPARAM2 op_10e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_10f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (xxx).W,(An)+ */
|
|
uae_u32 REGPARAM2 op_10f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,(An)+ */
|
|
uae_u32 REGPARAM2 op_10f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),(An)+ */
|
|
uae_u32 REGPARAM2 op_10fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_10fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B #<data>.B,(An)+ */
|
|
uae_u32 REGPARAM2 op_10fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_1100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An),-(An) */
|
|
uae_u32 REGPARAM2 op_1110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (An)+,-(An) */
|
|
uae_u32 REGPARAM2 op_1118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_1120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.B (d16,An),-(An) */
|
|
uae_u32 REGPARAM2 op_1128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_1130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (xxx).W,-(An) */
|
|
uae_u32 REGPARAM2 op_1138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,-(An) */
|
|
uae_u32 REGPARAM2 op_1139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),-(An) */
|
|
uae_u32 REGPARAM2 op_113a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_113b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B #<data>.B,-(An) */
|
|
uae_u32 REGPARAM2 op_113c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_1140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_1150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (An)+,(d16,An) */
|
|
uae_u32 REGPARAM2 op_1158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B -(An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_1160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d16,An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_1168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_1170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (xxx).W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_1178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_1179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),(d16,An) */
|
|
uae_u32 REGPARAM2 op_117a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_117b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B #<data>.B,(d16,An) */
|
|
uae_u32 REGPARAM2 op_117c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_1180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_1190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (An)+,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_1198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B -(An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.B (d16,An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,2 */
|
|
|
|
/* MOVE.B (xxx).W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.B (xxx).L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* MOVE.B (d16,PC),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,2 */
|
|
|
|
/* MOVE.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_11c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (An)+,(xxx).W */
|
|
uae_u32 REGPARAM2 op_11d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B -(An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.B (d16,An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (xxx).W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_11f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_11f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B #<data>.B,(xxx).W */
|
|
uae_u32 REGPARAM2 op_11fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_13c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (An)+,(xxx).L */
|
|
uae_u32 REGPARAM2 op_13d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B -(An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.B (d16,An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.B (xxx).W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_13f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.B (xxx).L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_13f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(10);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* MOVE.B (d16,PC),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.B #<data>.B,(xxx).L */
|
|
uae_u32 REGPARAM2 op_13fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_2000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L An,Dn */
|
|
uae_u32 REGPARAM2 op_2008_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_2010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_2018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_2020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_2028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_2030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_2038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_2039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_203a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_203b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_203c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVEA.L Dn,An */
|
|
uae_u32 REGPARAM2 op_2040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.L An,An */
|
|
uae_u32 REGPARAM2 op_2048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.L (An),An */
|
|
uae_u32 REGPARAM2 op_2050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.L (An)+,An */
|
|
uae_u32 REGPARAM2 op_2058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.L -(An),An */
|
|
uae_u32 REGPARAM2 op_2060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.L (d16,An),An */
|
|
uae_u32 REGPARAM2 op_2068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_2070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVEA.L (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_2078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.L (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_2079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVEA.L (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_207a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_207b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVEA.L #<data>.L,An */
|
|
uae_u32 REGPARAM2 op_207c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L Dn,(An) */
|
|
uae_u32 REGPARAM2 op_2080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L An,(An) */
|
|
uae_u32 REGPARAM2 op_2088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An),(An) */
|
|
uae_u32 REGPARAM2 op_2090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An)+,(An) */
|
|
uae_u32 REGPARAM2 op_2098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L -(An),(An) */
|
|
uae_u32 REGPARAM2 op_20a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (d16,An),(An) */
|
|
uae_u32 REGPARAM2 op_20a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_20b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (xxx).W,(An) */
|
|
uae_u32 REGPARAM2 op_20b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,(An) */
|
|
uae_u32 REGPARAM2 op_20b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),(An) */
|
|
uae_u32 REGPARAM2 op_20ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_20bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L #<data>.L,(An) */
|
|
uae_u32 REGPARAM2 op_20bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_20c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L An,(An)+ */
|
|
uae_u32 REGPARAM2 op_20c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An),(An)+ */
|
|
uae_u32 REGPARAM2 op_20d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An)+,(An)+ */
|
|
uae_u32 REGPARAM2 op_20d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L -(An),(An)+ */
|
|
uae_u32 REGPARAM2 op_20e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (d16,An),(An)+ */
|
|
uae_u32 REGPARAM2 op_20e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_20f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (xxx).W,(An)+ */
|
|
uae_u32 REGPARAM2 op_20f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,(An)+ */
|
|
uae_u32 REGPARAM2 op_20f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),(An)+ */
|
|
uae_u32 REGPARAM2 op_20fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_20fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L #<data>.L,(An)+ */
|
|
uae_u32 REGPARAM2 op_20fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_2100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L An,-(An) */
|
|
uae_u32 REGPARAM2 op_2108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An),-(An) */
|
|
uae_u32 REGPARAM2 op_2110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (An)+,-(An) */
|
|
uae_u32 REGPARAM2 op_2118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_2120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.L (d16,An),-(An) */
|
|
uae_u32 REGPARAM2 op_2128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_2130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (xxx).W,-(An) */
|
|
uae_u32 REGPARAM2 op_2138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,-(An) */
|
|
uae_u32 REGPARAM2 op_2139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),-(An) */
|
|
uae_u32 REGPARAM2 op_213a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_213b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L #<data>.L,-(An) */
|
|
uae_u32 REGPARAM2 op_213c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_2140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L An,(d16,An) */
|
|
uae_u32 REGPARAM2 op_2148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_2150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (An)+,(d16,An) */
|
|
uae_u32 REGPARAM2 op_2158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L -(An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_2160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d16,An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_2168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_2170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (xxx).W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_2178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_2179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),(d16,An) */
|
|
uae_u32 REGPARAM2 op_217a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_217b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L #<data>.L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_217c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L An,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (An)+,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L -(An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.L (d16,An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,2 */
|
|
|
|
/* MOVE.L (xxx).W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.L (xxx).L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* MOVE.L (d16,PC),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,2 */
|
|
|
|
/* MOVE.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* MOVE.L Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_21c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L An,(xxx).W */
|
|
uae_u32 REGPARAM2 op_21c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (An)+,(xxx).W */
|
|
uae_u32 REGPARAM2 op_21d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L -(An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.L (d16,An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (xxx).W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_21f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_21f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L #<data>.L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_21fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_23c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L An,(xxx).L */
|
|
uae_u32 REGPARAM2 op_23c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (An)+,(xxx).L */
|
|
uae_u32 REGPARAM2 op_23d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L -(An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.L (d16,An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.L (xxx).W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_23f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L (xxx).L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_23f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(10);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* MOVE.L (d16,PC),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.L #<data>.L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_23fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(10);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* MOVE.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_3000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W An,Dn */
|
|
uae_u32 REGPARAM2 op_3008_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_3010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_3018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_3020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_3028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_3030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_3038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_3039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_303a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_303b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_303c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.W Dn,An */
|
|
uae_u32 REGPARAM2 op_3040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.W An,An */
|
|
uae_u32 REGPARAM2 op_3048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.W (An),An */
|
|
uae_u32 REGPARAM2 op_3050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.W (An)+,An */
|
|
uae_u32 REGPARAM2 op_3058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.W -(An),An */
|
|
uae_u32 REGPARAM2 op_3060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVEA.W (d16,An),An */
|
|
uae_u32 REGPARAM2 op_3068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_3070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVEA.W (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_3078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.W (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_3079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVEA.W (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_307a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVEA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_307b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVEA.W #<data>.W,An */
|
|
uae_u32 REGPARAM2 op_307c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W Dn,(An) */
|
|
uae_u32 REGPARAM2 op_3080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W An,(An) */
|
|
uae_u32 REGPARAM2 op_3088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An),(An) */
|
|
uae_u32 REGPARAM2 op_3090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An)+,(An) */
|
|
uae_u32 REGPARAM2 op_3098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W -(An),(An) */
|
|
uae_u32 REGPARAM2 op_30a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (d16,An),(An) */
|
|
uae_u32 REGPARAM2 op_30a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_30b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (xxx).W,(An) */
|
|
uae_u32 REGPARAM2 op_30b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,(An) */
|
|
uae_u32 REGPARAM2 op_30b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),(An) */
|
|
uae_u32 REGPARAM2 op_30ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_30bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_30bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_30c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W An,(An)+ */
|
|
uae_u32 REGPARAM2 op_30c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An),(An)+ */
|
|
uae_u32 REGPARAM2 op_30d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An)+,(An)+ */
|
|
uae_u32 REGPARAM2 op_30d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W -(An),(An)+ */
|
|
uae_u32 REGPARAM2 op_30e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (d16,An),(An)+ */
|
|
uae_u32 REGPARAM2 op_30e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_30f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (xxx).W,(An)+ */
|
|
uae_u32 REGPARAM2 op_30f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,(An)+ */
|
|
uae_u32 REGPARAM2 op_30f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),(An)+ */
|
|
uae_u32 REGPARAM2 op_30fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_30fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_30fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_3100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W An,-(An) */
|
|
uae_u32 REGPARAM2 op_3108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An),-(An) */
|
|
uae_u32 REGPARAM2 op_3110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (An)+,-(An) */
|
|
uae_u32 REGPARAM2 op_3118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_3120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MOVE.W (d16,An),-(An) */
|
|
uae_u32 REGPARAM2 op_3128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_3130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (xxx).W,-(An) */
|
|
uae_u32 REGPARAM2 op_3138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,-(An) */
|
|
uae_u32 REGPARAM2 op_3139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),-(An) */
|
|
uae_u32 REGPARAM2 op_313a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_313b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_313c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_3140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W An,(d16,An) */
|
|
uae_u32 REGPARAM2 op_3148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_3150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (An)+,(d16,An) */
|
|
uae_u32 REGPARAM2 op_3158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W -(An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_3160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d16,An),(d16,An) */
|
|
uae_u32 REGPARAM2 op_3168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_3170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (xxx).W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_3178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,(d16,An) */
|
|
uae_u32 REGPARAM2 op_3179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),(d16,An) */
|
|
uae_u32 REGPARAM2 op_317a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_317b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_317c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W An,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (An)+,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W -(An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MOVE.W (d16,An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,2 */
|
|
|
|
/* MOVE.W (xxx).W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.W (xxx).L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(6);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 2,0 */
|
|
|
|
/* MOVE.W (d16,PC),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,2 */
|
|
|
|
/* MOVE.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MOVE.W Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_31c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W An,(xxx).W */
|
|
uae_u32 REGPARAM2 op_31c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (An)+,(xxx).W */
|
|
uae_u32 REGPARAM2 op_31d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W -(An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MOVE.W (d16,An),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (xxx).W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_31f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,(xxx).W */
|
|
uae_u32 REGPARAM2 op_31f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_31fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_33c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W An,(xxx).L */
|
|
uae_u32 REGPARAM2 op_33c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (An)+,(xxx).L */
|
|
uae_u32 REGPARAM2 op_33d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W -(An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MOVE.W (d16,An),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.W (xxx).W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_33f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.W (xxx).L,(xxx).L */
|
|
uae_u32 REGPARAM2 op_33f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(6);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(10);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 10 0,0 */
|
|
|
|
/* MOVE.W (d16,PC),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_33fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* NEGX.B Dn */
|
|
uae_u32 REGPARAM2 op_4000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.B (An) */
|
|
uae_u32 REGPARAM2 op_4010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.B -(An) */
|
|
uae_u32 REGPARAM2 op_4020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEGX.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NEGX.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEGX.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* NEGX.W Dn */
|
|
uae_u32 REGPARAM2 op_4040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.W (An) */
|
|
uae_u32 REGPARAM2 op_4050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.W (An)+ */
|
|
uae_u32 REGPARAM2 op_4058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.W -(An) */
|
|
uae_u32 REGPARAM2 op_4060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_4068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEGX.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NEGX.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_4078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEGX.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_4079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* NEGX.L Dn */
|
|
uae_u32 REGPARAM2 op_4080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, srcreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.L (An) */
|
|
uae_u32 REGPARAM2 op_4090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.L (An)+ */
|
|
uae_u32 REGPARAM2 op_4098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.L -(An) */
|
|
uae_u32 REGPARAM2 op_40a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEGX.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_40a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEGX.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_40b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NEGX.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_40b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEGX.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_40b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVSR2.W Dn */
|
|
uae_u32 REGPARAM2 op_40c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W (An) */
|
|
uae_u32 REGPARAM2 op_40d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W (An)+ */
|
|
uae_u32 REGPARAM2 op_40d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W -(An) */
|
|
uae_u32 REGPARAM2 op_40e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
m68k_areg(regs, srcreg) = srca;
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_40e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVSR2.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_40f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MVSR2.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_40f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVSR2.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_40f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CHK.L Dn,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (An),Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (An)+,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L -(An),Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (d16,An),Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (d8,An,Xn),Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
#endif
|
|
/* CHK.L (xxx).W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (xxx).L,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(6);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (d16,PC),Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_413a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CHK.L (d8,PC,Xn),Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_413b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
#endif
|
|
/* CHK.L #<data>.L,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_413c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(6);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 2);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CHK.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_4180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CHK.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_4190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CHK.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_4198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CHK.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_41a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(2);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CHK.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_41a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CHK.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_41b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CHK.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_41b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CHK.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_41b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(6);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CHK.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_41ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CHK.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_41bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CHK.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_41bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LEA.L (An),An */
|
|
uae_u32 REGPARAM2 op_41d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LEA.L (d16,An),An */
|
|
uae_u32 REGPARAM2 op_41e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LEA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_41f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* LEA.L (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_41f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LEA.L (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_41f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* LEA.L (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_41fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LEA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_41fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CLR.B Dn */
|
|
uae_u32 REGPARAM2 op_4200_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B (An) */
|
|
uae_u32 REGPARAM2 op_4210_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4218_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B -(An) */
|
|
uae_u32 REGPARAM2 op_4220_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4228_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4230_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CLR.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4238_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4239_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CLR.W Dn */
|
|
uae_u32 REGPARAM2 op_4240_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W (An) */
|
|
uae_u32 REGPARAM2 op_4250_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W (An)+ */
|
|
uae_u32 REGPARAM2 op_4258_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W -(An) */
|
|
uae_u32 REGPARAM2 op_4260_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_4268_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4270_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CLR.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_4278_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_4279_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CLR.L Dn */
|
|
uae_u32 REGPARAM2 op_4280_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
m68k_dreg(regs, srcreg) = (0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L (An) */
|
|
uae_u32 REGPARAM2 op_4290_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L (An)+ */
|
|
uae_u32 REGPARAM2 op_4298_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L -(An) */
|
|
uae_u32 REGPARAM2 op_42a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_42a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_42b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CLR.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_42b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_42b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVSR2.B Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
MakeSR();
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B (An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B -(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
m68k_areg(regs, srcreg) = srca;
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B (d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B (d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B (xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MVSR2.B (xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* NEG.B Dn */
|
|
uae_u32 REGPARAM2 op_4400_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.B (An) */
|
|
uae_u32 REGPARAM2 op_4410_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4418_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.B -(An) */
|
|
uae_u32 REGPARAM2 op_4420_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4428_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEG.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4430_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NEG.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4438_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEG.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4439_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* NEG.W Dn */
|
|
uae_u32 REGPARAM2 op_4440_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.W (An) */
|
|
uae_u32 REGPARAM2 op_4450_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.W (An)+ */
|
|
uae_u32 REGPARAM2 op_4458_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.W -(An) */
|
|
uae_u32 REGPARAM2 op_4460_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_4468_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEG.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4470_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NEG.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_4478_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEG.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_4479_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* NEG.L Dn */
|
|
uae_u32 REGPARAM2 op_4480_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.L (An) */
|
|
uae_u32 REGPARAM2 op_4490_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.L (An)+ */
|
|
uae_u32 REGPARAM2 op_4498_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.L -(An) */
|
|
uae_u32 REGPARAM2 op_44a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NEG.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_44a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEG.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_44b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NEG.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_44b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NEG.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_44b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.B Dn */
|
|
uae_u32 REGPARAM2 op_44c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B (An) */
|
|
uae_u32 REGPARAM2 op_44d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B (An)+ */
|
|
uae_u32 REGPARAM2 op_44d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B -(An) */
|
|
uae_u32 REGPARAM2 op_44e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_44e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_44f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MV2SR.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_44f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_44f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.B (d16,PC) */
|
|
uae_u32 REGPARAM2 op_44fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.B (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_44fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MV2SR.B #<data>.B */
|
|
uae_u32 REGPARAM2 op_44fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.B Dn */
|
|
uae_u32 REGPARAM2 op_4600_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.B (An) */
|
|
uae_u32 REGPARAM2 op_4610_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4618_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.B -(An) */
|
|
uae_u32 REGPARAM2 op_4620_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4628_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4630_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NOT.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4638_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4639_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* NOT.W Dn */
|
|
uae_u32 REGPARAM2 op_4640_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.W (An) */
|
|
uae_u32 REGPARAM2 op_4650_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.W (An)+ */
|
|
uae_u32 REGPARAM2 op_4658_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.W -(An) */
|
|
uae_u32 REGPARAM2 op_4660_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_4668_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4670_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NOT.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_4678_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_4679_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* NOT.L Dn */
|
|
uae_u32 REGPARAM2 op_4680_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.L (An) */
|
|
uae_u32 REGPARAM2 op_4690_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.L (An)+ */
|
|
uae_u32 REGPARAM2 op_4698_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.L -(An) */
|
|
uae_u32 REGPARAM2 op_46a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOT.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_46a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_46b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NOT.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_46b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NOT.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_46b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.W Dn */
|
|
uae_u32 REGPARAM2 op_46c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W (An) */
|
|
uae_u32 REGPARAM2 op_46d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W (An)+ */
|
|
uae_u32 REGPARAM2 op_46d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W -(An) */
|
|
uae_u32 REGPARAM2 op_46e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_46e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_46f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MV2SR.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_46f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_46f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.W (d16,PC) */
|
|
uae_u32 REGPARAM2 op_46fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_46fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MV2SR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_46fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B Dn */
|
|
uae_u32 REGPARAM2 op_4800_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LINK.L An,#<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4808_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr olda;
|
|
olda = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = olda;
|
|
uae_s32 offs;
|
|
offs = get_dilong(2);
|
|
put_long(olda, src);
|
|
m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
|
|
m68k_areg(regs, 7) += offs;
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* NBCD.B (An) */
|
|
uae_u32 REGPARAM2 op_4810_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4818_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B -(An) */
|
|
uae_u32 REGPARAM2 op_4820_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4828_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4830_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NBCD.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4838_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4839_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(srca, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SWAP.W Dn */
|
|
uae_u32 REGPARAM2 op_4840_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BKPTQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4848_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
op_illg(opcode);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* PEA.L (An) */
|
|
uae_u32 REGPARAM2 op_4850_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* PEA.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4868_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* PEA.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4870_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* PEA.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4878_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* PEA.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4879_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* PEA.L (d16,PC) */
|
|
uae_u32 REGPARAM2 op_487a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* PEA.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_487b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
put_long(dsta, srca);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* EXT.W Dn */
|
|
uae_u32 REGPARAM2 op_4880_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u16 dst = (uae_s16)(uae_s8)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4890_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_48a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 0;
|
|
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
|
|
int type = 1;
|
|
while (amask) {
|
|
srca -= 2;
|
|
if (!type || movem_index2[amask] != dstreg) {
|
|
put_word(srca, m68k_areg(regs, movem_index2[amask]));
|
|
} else {
|
|
put_word(srca, m68k_areg(regs, movem_index2[amask]) - 2);
|
|
}
|
|
amask = movem_next[amask];
|
|
}
|
|
while (dmask) {
|
|
srca -= 2;
|
|
put_word(srca, m68k_dreg(regs, movem_index2[dmask]));
|
|
dmask = movem_next[dmask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_48a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_48b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_48b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_48b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EXT.L Dn */
|
|
uae_u32 REGPARAM2 op_48c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_48d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_48e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 0;
|
|
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
|
|
int type = 1;
|
|
while (amask) {
|
|
srca -= 4;
|
|
if (!type || movem_index2[amask] != dstreg) {
|
|
put_long(srca, m68k_areg(regs, movem_index2[amask]));
|
|
} else {
|
|
put_long(srca, m68k_areg(regs, movem_index2[amask]) - 4);
|
|
}
|
|
amask = movem_next[amask];
|
|
}
|
|
while (dmask) {
|
|
srca -= 4;
|
|
put_long(srca, m68k_dreg(regs, movem_index2[dmask]));
|
|
dmask = movem_next[dmask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_48e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_48f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_48f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_48f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EXT.B Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_49c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_u32 dst = (uae_s32)(uae_s8)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* TST.B Dn */
|
|
uae_u32 REGPARAM2 op_4a00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.B (An) */
|
|
uae_u32 REGPARAM2 op_4a10_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4a18_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.B -(An) */
|
|
uae_u32 REGPARAM2 op_4a20_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4a28_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TST.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4a30_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* TST.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4a38_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TST.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4a39_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TST.B (d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a3a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TST.B (d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a3b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
#endif
|
|
/* TST.B #<data>.B */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a3c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s8 src = get_dibyte(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TST.W Dn */
|
|
uae_u32 REGPARAM2 op_4a40_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.W An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a48_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* TST.W (An) */
|
|
uae_u32 REGPARAM2 op_4a50_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.W (An)+ */
|
|
uae_u32 REGPARAM2 op_4a58_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.W -(An) */
|
|
uae_u32 REGPARAM2 op_4a60_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_4a68_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TST.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4a70_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* TST.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_4a78_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TST.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_4a79_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TST.W (d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a7a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TST.W (d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a7b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
#endif
|
|
/* TST.W #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a7c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TST.L Dn */
|
|
uae_u32 REGPARAM2 op_4a80_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.L An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4a88_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* TST.L (An) */
|
|
uae_u32 REGPARAM2 op_4a90_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.L (An)+ */
|
|
uae_u32 REGPARAM2 op_4a98_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.L -(An) */
|
|
uae_u32 REGPARAM2 op_4aa0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TST.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4aa8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TST.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4ab0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* TST.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4ab8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TST.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4ab9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TST.L (d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4aba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TST.L (d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4abb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
#endif
|
|
/* TST.L #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4abc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TAS.B Dn */
|
|
uae_u32 REGPARAM2 op_4ac0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* HALT.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4ac8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
cpu_halt(CPU_HALT_68060_HALT);
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* PULSE.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4acc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* TAS.B (An) */
|
|
uae_u32 REGPARAM2 op_4ad0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4ad8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B -(An) */
|
|
uae_u32 REGPARAM2 op_4ae0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ae8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4af0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* TAS.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4af8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4af9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULL.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c10_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(4);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c18_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
m68k_incpc(4);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
cpu_restore_fixup();
|
|
}
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c20_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
m68k_incpc(4);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
cpu_restore_fixup();
|
|
}
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c28_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(6);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c30_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c38_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(6);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c39_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(8);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c3a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(6);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c3b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* MULL.L #<data>.W,#<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c3c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_s32 dst;
|
|
dst = get_dilong(4);
|
|
m68k_incpc(8);
|
|
int e = m68k_mull(opcode, dst, extra);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c40_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c50_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(4);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c58_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
m68k_incpc(4);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
cpu_restore_fixup();
|
|
}
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c60_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
m68k_incpc(4);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
cpu_restore_fixup();
|
|
}
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
mmufixup[0].reg = -1;
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c68_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(6);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c70_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c78_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(6);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c79_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(8);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c7a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_incpc(6);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c7b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* DIVL.L #<data>.W,#<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4c7c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 extra = get_diword(2);
|
|
uae_s32 dst;
|
|
dst = get_dilong(4);
|
|
m68k_incpc(8);
|
|
int e = m68k_divl(opcode, dst, extra, oldpc);
|
|
if (e <= 0) {
|
|
if (e < 0) {
|
|
op_unimpl(opcode);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MVMEL.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4c90_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_4c98_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_4ca8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4cb0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_4cb8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_4cb9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_4cba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 4;
|
|
srca += (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4cbb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4cd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_4cd8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_4ce8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4cf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_4cf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_4cf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_4cfa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 4;
|
|
srca += (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4cfb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* TRAPQ.L #<data> */
|
|
uae_u32 REGPARAM2 op_4e40_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 15);
|
|
uae_u32 src = srcreg;
|
|
m68k_incpc(2);
|
|
Exception_cpu(src + 32);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LINK.W An,#<data>.W */
|
|
uae_u32 REGPARAM2 op_4e50_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr olda;
|
|
olda = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = olda;
|
|
uae_s16 offs = get_diword(2);
|
|
put_long(olda, src);
|
|
m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
|
|
m68k_areg(regs, 7) += offs;
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* UNLK.L An */
|
|
uae_u32 REGPARAM2 op_4e58_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_u32 olda = src;
|
|
uae_s32 old = get_long(olda);
|
|
m68k_areg(regs, 7) = src + 4;
|
|
m68k_areg(regs, srcreg) = (old);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVR2USP.L An */
|
|
uae_u32 REGPARAM2 op_4e60_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
regs.usp = src;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVUSP2R.L An */
|
|
uae_u32 REGPARAM2 op_4e68_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_areg(regs, srcreg) = (regs.usp);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RESET.L */
|
|
uae_u32 REGPARAM2 op_4e70_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
bool r = cpureset();
|
|
if (r) {
|
|
return (128 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (132 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOP.L */
|
|
uae_u32 REGPARAM2 op_4e71_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* STOP.L #<data>.W */
|
|
uae_u32 REGPARAM2 op_4e72_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
if (!regs.stopped) {
|
|
uae_s16 src = get_diword(2);
|
|
regs.ir = src;
|
|
}
|
|
uae_u16 sr = regs.ir;
|
|
if (!(sr & 0x2000)) {
|
|
Exception(8);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr = sr;
|
|
checkint();
|
|
MakeFromSR_STOP();
|
|
do_cycles_stop(4);
|
|
m68k_setstopped(1);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
/* RTE.L */
|
|
uae_u32 REGPARAM2 op_4e73_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 oldsr = regs.sr, newsr;
|
|
uae_u32 newpc;
|
|
for (;;) {
|
|
uaecptr a = m68k_areg(regs, 7);
|
|
uae_u16 sr = get_word(a);
|
|
uae_u32 pc = get_long(a + 2);
|
|
uae_u16 format = get_word(a + 2 + 4);
|
|
int frame = format >> 12;
|
|
int offset = 8;
|
|
newsr = sr; newpc = pc;
|
|
if (frame == 0x0) {
|
|
m68k_areg(regs, 7) += offset; break; }
|
|
else if (frame == 0x1) {
|
|
m68k_areg(regs, 7) += offset; }
|
|
else if (frame == 0x2) {
|
|
m68k_areg(regs, 7) += offset + 4; break; }
|
|
else if (frame == 0x3) {
|
|
m68k_areg(regs, 7) += offset + 4; break; }
|
|
else if (frame == 0x4) {
|
|
m68k_areg(regs, 7) += offset + 8; break; }
|
|
else {
|
|
Exception_cpu(14);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr = newsr;
|
|
oldsr = newsr;
|
|
MakeFromSR_T0();
|
|
}
|
|
regs.sr = newsr;
|
|
MakeFromSR_T0();
|
|
if (newpc & 1) {
|
|
regs.sr = oldsr & 0xff00;
|
|
MakeFromSR();
|
|
SET_ZFLG(newsr == 0);
|
|
SET_NFLG(newsr & 0x8000);
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(newpc);
|
|
#ifdef DEBUGGER
|
|
branch_stack_pop_rte(oldpc);
|
|
#endif
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* RTD.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4e74_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
uae_s16 offs = get_diword(2);
|
|
m68k_areg(regs, 7) += offs;
|
|
if (pc & 1) {
|
|
m68k_areg(regs, 7) -= 4 + offs;
|
|
exception3_read_prefetch_only(opcode, pc);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(pc);
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
#endif
|
|
/* RTS.L */
|
|
uae_u32 REGPARAM2 op_4e75_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
m68k_do_rts();
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_pop_rts(oldpc);
|
|
}
|
|
#endif
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* TRAPV.L */
|
|
uae_u32 REGPARAM2 op_4e76_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (GET_VFLG()) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RTR.L */
|
|
uae_u32 REGPARAM2 op_4e77_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
MakeSR();
|
|
uaecptr sra;
|
|
sra = m68k_areg(regs, 7);
|
|
uae_s16 sr = get_word(sra);
|
|
m68k_areg(regs, 7) += 2;
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
if (pc & 1) {
|
|
m68k_areg(regs, 7) -= 6;
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
exception3_read_prefetch(opcode, pc);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
m68k_setpc_j(pc);
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* MOVEC2.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4e7a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
int regno = (src >> 12) & 15;
|
|
uae_u32 *regp = regs.regs + regno;
|
|
if (!m68k_movec2(src & 0xFFF, regp)) {
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVE2C.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4e7b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
int regno = (src >> 12) & 15;
|
|
uae_u32 *regp = regs.regs + regno;
|
|
if (!m68k_move2c(src & 0xFFF, regp)) {
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* JSR.L (An) */
|
|
uae_u32 REGPARAM2 op_4e90_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* JSR.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ea8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4eb0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 0;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 B */
|
|
|
|
/* JSR.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4eb8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4eb9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 6;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* JSR.L (d16,PC) */
|
|
uae_u32 REGPARAM2 op_4eba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4ebb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 0;
|
|
m68k_setpc_j(srca);
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7) - 4, nextpc);
|
|
m68k_areg(regs, 7) -= 4;
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 B */
|
|
|
|
/* JMP.L (An) */
|
|
uae_u32 REGPARAM2 op_4ed0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
if (srca & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* JMP.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ee8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JMP.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4ef0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 B */
|
|
|
|
/* JMP.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4ef8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JMP.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4ef9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
if (srca & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* JMP.L (d16,PC) */
|
|
uae_u32 REGPARAM2 op_4efa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JMP.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4efb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 B */
|
|
|
|
/* ADDQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.B #<data>,(An) */
|
|
uae_u32 REGPARAM2 op_5010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.B #<data>,(An)+ */
|
|
uae_u32 REGPARAM2 op_5018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.B #<data>,-(An) */
|
|
uae_u32 REGPARAM2 op_5020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.B #<data>,(d16,An) */
|
|
uae_u32 REGPARAM2 op_5028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDQ.B #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDQ.B #<data>,(xxx).W */
|
|
uae_u32 REGPARAM2 op_5038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDQ.B #<data>,(xxx).L */
|
|
uae_u32 REGPARAM2 op_5039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDAQ.W #<data>,An */
|
|
uae_u32 REGPARAM2 op_5048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.W #<data>,(An) */
|
|
uae_u32 REGPARAM2 op_5050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.W #<data>,(An)+ */
|
|
uae_u32 REGPARAM2 op_5058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.W #<data>,-(An) */
|
|
uae_u32 REGPARAM2 op_5060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.W #<data>,(d16,An) */
|
|
uae_u32 REGPARAM2 op_5068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDQ.W #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDQ.W #<data>,(xxx).W */
|
|
uae_u32 REGPARAM2 op_5078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDQ.W #<data>,(xxx).L */
|
|
uae_u32 REGPARAM2 op_5079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDAQ.L #<data>,An */
|
|
uae_u32 REGPARAM2 op_5088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.L #<data>,(An) */
|
|
uae_u32 REGPARAM2 op_5090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.L #<data>,(An)+ */
|
|
uae_u32 REGPARAM2 op_5098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.L #<data>,-(An) */
|
|
uae_u32 REGPARAM2 op_50a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDQ.L #<data>,(d16,An) */
|
|
uae_u32 REGPARAM2 op_50a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDQ.L #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_50b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDQ.L #<data>,(xxx).W */
|
|
uae_u32 REGPARAM2 op_50b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDQ.L #<data>,(xxx).L */
|
|
uae_u32 REGPARAM2 op_50b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (T) */
|
|
uae_u32 REGPARAM2 op_50c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_50c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(0)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (T) */
|
|
uae_u32 REGPARAM2 op_50d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (T) */
|
|
uae_u32 REGPARAM2 op_50d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (T) */
|
|
uae_u32 REGPARAM2 op_50e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (T) */
|
|
uae_u32 REGPARAM2 op_50e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (T) */
|
|
uae_u32 REGPARAM2 op_50f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (T) */
|
|
uae_u32 REGPARAM2 op_50f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (T) */
|
|
uae_u32 REGPARAM2 op_50f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (T) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_50fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(0)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (T) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_50fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(0)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (T) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_50fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(0)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* SUBQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.B #<data>,(An) */
|
|
uae_u32 REGPARAM2 op_5110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.B #<data>,(An)+ */
|
|
uae_u32 REGPARAM2 op_5118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.B #<data>,-(An) */
|
|
uae_u32 REGPARAM2 op_5120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.B #<data>,(d16,An) */
|
|
uae_u32 REGPARAM2 op_5128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBQ.B #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBQ.B #<data>,(xxx).W */
|
|
uae_u32 REGPARAM2 op_5138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBQ.B #<data>,(xxx).L */
|
|
uae_u32 REGPARAM2 op_5139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBAQ.W #<data>,An */
|
|
uae_u32 REGPARAM2 op_5148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.W #<data>,(An) */
|
|
uae_u32 REGPARAM2 op_5150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.W #<data>,(An)+ */
|
|
uae_u32 REGPARAM2 op_5158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.W #<data>,-(An) */
|
|
uae_u32 REGPARAM2 op_5160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.W #<data>,(d16,An) */
|
|
uae_u32 REGPARAM2 op_5168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBQ.W #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBQ.W #<data>,(xxx).W */
|
|
uae_u32 REGPARAM2 op_5178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBQ.W #<data>,(xxx).L */
|
|
uae_u32 REGPARAM2 op_5179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBAQ.L #<data>,An */
|
|
uae_u32 REGPARAM2 op_5188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.L #<data>,(An) */
|
|
uae_u32 REGPARAM2 op_5190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.L #<data>,(An)+ */
|
|
uae_u32 REGPARAM2 op_5198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.L #<data>,-(An) */
|
|
uae_u32 REGPARAM2 op_51a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBQ.L #<data>,(d16,An) */
|
|
uae_u32 REGPARAM2 op_51a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBQ.L #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_51b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBQ.L #<data>,(xxx).W */
|
|
uae_u32 REGPARAM2 op_51b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBQ.L #<data>,(xxx).L */
|
|
uae_u32 REGPARAM2 op_51b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (F) */
|
|
uae_u32 REGPARAM2 op_51c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (F) */
|
|
uae_u32 REGPARAM2 op_51c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(1)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (F) */
|
|
uae_u32 REGPARAM2 op_51d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (F) */
|
|
uae_u32 REGPARAM2 op_51d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (F) */
|
|
uae_u32 REGPARAM2 op_51e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (F) */
|
|
uae_u32 REGPARAM2 op_51e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (F) */
|
|
uae_u32 REGPARAM2 op_51f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (F) */
|
|
uae_u32 REGPARAM2 op_51f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (F) */
|
|
uae_u32 REGPARAM2 op_51f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (F) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_51fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(1)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (F) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_51fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(1)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (F) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_51fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(1)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (HI) */
|
|
uae_u32 REGPARAM2 op_52c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_52c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(2)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (HI) */
|
|
uae_u32 REGPARAM2 op_52d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (HI) */
|
|
uae_u32 REGPARAM2 op_52d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (HI) */
|
|
uae_u32 REGPARAM2 op_52e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (HI) */
|
|
uae_u32 REGPARAM2 op_52e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (HI) */
|
|
uae_u32 REGPARAM2 op_52f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (HI) */
|
|
uae_u32 REGPARAM2 op_52f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (HI) */
|
|
uae_u32 REGPARAM2 op_52f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (HI) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_52fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(2)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (HI) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_52fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(2)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (HI) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_52fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(2)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (LS) */
|
|
uae_u32 REGPARAM2 op_53c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_53c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(3)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (LS) */
|
|
uae_u32 REGPARAM2 op_53d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (LS) */
|
|
uae_u32 REGPARAM2 op_53d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (LS) */
|
|
uae_u32 REGPARAM2 op_53e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (LS) */
|
|
uae_u32 REGPARAM2 op_53e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (LS) */
|
|
uae_u32 REGPARAM2 op_53f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (LS) */
|
|
uae_u32 REGPARAM2 op_53f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (LS) */
|
|
uae_u32 REGPARAM2 op_53f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (LS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_53fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(3)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (LS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_53fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(3)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (LS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_53fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(3)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (CC) */
|
|
uae_u32 REGPARAM2 op_54c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_54c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(4)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (CC) */
|
|
uae_u32 REGPARAM2 op_54d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (CC) */
|
|
uae_u32 REGPARAM2 op_54d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (CC) */
|
|
uae_u32 REGPARAM2 op_54e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (CC) */
|
|
uae_u32 REGPARAM2 op_54e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (CC) */
|
|
uae_u32 REGPARAM2 op_54f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (CC) */
|
|
uae_u32 REGPARAM2 op_54f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (CC) */
|
|
uae_u32 REGPARAM2 op_54f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (CC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_54fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(4)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (CC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_54fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(4)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (CC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_54fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(4)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (CS) */
|
|
uae_u32 REGPARAM2 op_55c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_55c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(5)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (CS) */
|
|
uae_u32 REGPARAM2 op_55d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (CS) */
|
|
uae_u32 REGPARAM2 op_55d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (CS) */
|
|
uae_u32 REGPARAM2 op_55e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (CS) */
|
|
uae_u32 REGPARAM2 op_55e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (CS) */
|
|
uae_u32 REGPARAM2 op_55f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (CS) */
|
|
uae_u32 REGPARAM2 op_55f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (CS) */
|
|
uae_u32 REGPARAM2 op_55f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (CS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_55fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(5)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (CS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_55fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(5)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (CS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_55fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(5)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (NE) */
|
|
uae_u32 REGPARAM2 op_56c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_56c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(6)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (NE) */
|
|
uae_u32 REGPARAM2 op_56d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (NE) */
|
|
uae_u32 REGPARAM2 op_56d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (NE) */
|
|
uae_u32 REGPARAM2 op_56e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (NE) */
|
|
uae_u32 REGPARAM2 op_56e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (NE) */
|
|
uae_u32 REGPARAM2 op_56f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (NE) */
|
|
uae_u32 REGPARAM2 op_56f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (NE) */
|
|
uae_u32 REGPARAM2 op_56f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (NE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_56fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(6)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (NE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_56fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(6)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (NE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_56fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(6)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (EQ) */
|
|
uae_u32 REGPARAM2 op_57c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_57c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(7)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (EQ) */
|
|
uae_u32 REGPARAM2 op_57d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (EQ) */
|
|
uae_u32 REGPARAM2 op_57d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (EQ) */
|
|
uae_u32 REGPARAM2 op_57e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (EQ) */
|
|
uae_u32 REGPARAM2 op_57e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (EQ) */
|
|
uae_u32 REGPARAM2 op_57f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (EQ) */
|
|
uae_u32 REGPARAM2 op_57f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (EQ) */
|
|
uae_u32 REGPARAM2 op_57f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (EQ) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_57fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(7)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (EQ) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_57fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(7)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (EQ) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_57fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(7)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (VC) */
|
|
uae_u32 REGPARAM2 op_58c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_58c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(8)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (VC) */
|
|
uae_u32 REGPARAM2 op_58d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (VC) */
|
|
uae_u32 REGPARAM2 op_58d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (VC) */
|
|
uae_u32 REGPARAM2 op_58e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (VC) */
|
|
uae_u32 REGPARAM2 op_58e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (VC) */
|
|
uae_u32 REGPARAM2 op_58f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (VC) */
|
|
uae_u32 REGPARAM2 op_58f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (VC) */
|
|
uae_u32 REGPARAM2 op_58f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (VC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_58fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(8)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (VC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_58fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(8)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (VC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_58fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(8)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (VS) */
|
|
uae_u32 REGPARAM2 op_59c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_59c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(9)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (VS) */
|
|
uae_u32 REGPARAM2 op_59d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (VS) */
|
|
uae_u32 REGPARAM2 op_59d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (VS) */
|
|
uae_u32 REGPARAM2 op_59e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (VS) */
|
|
uae_u32 REGPARAM2 op_59e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (VS) */
|
|
uae_u32 REGPARAM2 op_59f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (VS) */
|
|
uae_u32 REGPARAM2 op_59f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (VS) */
|
|
uae_u32 REGPARAM2 op_59f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (VS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_59fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(9)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (VS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_59fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(9)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (VS) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_59fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(9)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (PL) */
|
|
uae_u32 REGPARAM2 op_5ac0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_5ac8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(10)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (PL) */
|
|
uae_u32 REGPARAM2 op_5ad0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (PL) */
|
|
uae_u32 REGPARAM2 op_5ad8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (PL) */
|
|
uae_u32 REGPARAM2 op_5ae0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (PL) */
|
|
uae_u32 REGPARAM2 op_5ae8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (PL) */
|
|
uae_u32 REGPARAM2 op_5af0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (PL) */
|
|
uae_u32 REGPARAM2 op_5af8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (PL) */
|
|
uae_u32 REGPARAM2 op_5af9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (PL) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5afa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(10)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (PL) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5afb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(10)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (PL) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5afc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(10)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (MI) */
|
|
uae_u32 REGPARAM2 op_5bc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_5bc8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(11)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (MI) */
|
|
uae_u32 REGPARAM2 op_5bd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (MI) */
|
|
uae_u32 REGPARAM2 op_5bd8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (MI) */
|
|
uae_u32 REGPARAM2 op_5be0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (MI) */
|
|
uae_u32 REGPARAM2 op_5be8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (MI) */
|
|
uae_u32 REGPARAM2 op_5bf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (MI) */
|
|
uae_u32 REGPARAM2 op_5bf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (MI) */
|
|
uae_u32 REGPARAM2 op_5bf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (MI) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5bfa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(11)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (MI) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5bfb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(11)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (MI) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5bfc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(11)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (GE) */
|
|
uae_u32 REGPARAM2 op_5cc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_5cc8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(12)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (GE) */
|
|
uae_u32 REGPARAM2 op_5cd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (GE) */
|
|
uae_u32 REGPARAM2 op_5cd8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (GE) */
|
|
uae_u32 REGPARAM2 op_5ce0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (GE) */
|
|
uae_u32 REGPARAM2 op_5ce8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (GE) */
|
|
uae_u32 REGPARAM2 op_5cf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (GE) */
|
|
uae_u32 REGPARAM2 op_5cf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (GE) */
|
|
uae_u32 REGPARAM2 op_5cf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (GE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5cfa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(12)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (GE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5cfb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(12)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (GE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5cfc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(12)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (LT) */
|
|
uae_u32 REGPARAM2 op_5dc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_5dc8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(13)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (LT) */
|
|
uae_u32 REGPARAM2 op_5dd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (LT) */
|
|
uae_u32 REGPARAM2 op_5dd8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (LT) */
|
|
uae_u32 REGPARAM2 op_5de0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (LT) */
|
|
uae_u32 REGPARAM2 op_5de8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (LT) */
|
|
uae_u32 REGPARAM2 op_5df0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (LT) */
|
|
uae_u32 REGPARAM2 op_5df8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (LT) */
|
|
uae_u32 REGPARAM2 op_5df9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (LT) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5dfa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(13)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (LT) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5dfb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(13)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (LT) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5dfc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(13)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (GT) */
|
|
uae_u32 REGPARAM2 op_5ec0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_5ec8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(14)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (GT) */
|
|
uae_u32 REGPARAM2 op_5ed0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (GT) */
|
|
uae_u32 REGPARAM2 op_5ed8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (GT) */
|
|
uae_u32 REGPARAM2 op_5ee0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (GT) */
|
|
uae_u32 REGPARAM2 op_5ee8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (GT) */
|
|
uae_u32 REGPARAM2 op_5ef0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (GT) */
|
|
uae_u32 REGPARAM2 op_5ef8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (GT) */
|
|
uae_u32 REGPARAM2 op_5ef9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (GT) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5efa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(14)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (GT) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5efb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(14)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (GT) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5efc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(14)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Scc.B Dn (LE) */
|
|
uae_u32 REGPARAM2 op_5fc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_5fc8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!cctrue(15)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (LE) */
|
|
uae_u32 REGPARAM2 op_5fd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (LE) */
|
|
uae_u32 REGPARAM2 op_5fd8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (LE) */
|
|
uae_u32 REGPARAM2 op_5fe0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (LE) */
|
|
uae_u32 REGPARAM2 op_5fe8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (LE) */
|
|
uae_u32 REGPARAM2 op_5ff0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* Scc.B (xxx).W (LE) */
|
|
uae_u32 REGPARAM2 op_5ff8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (LE) */
|
|
uae_u32 REGPARAM2 op_5ff9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* TRAPcc.L #<data>.W (LE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5ffa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 dummy = get_diword(2);
|
|
m68k_incpc(4);
|
|
if (cctrue(15)) {
|
|
Exception_cpu(7);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L #<data>.L (LE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5ffb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(2);
|
|
m68k_incpc(6);
|
|
if (cctrue(15)) {
|
|
Exception_cpu(7);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* TRAPcc.L (LE) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_5ffc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (cctrue(15)) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
#endif
|
|
/* Bcc.W #<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_6000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(0)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (T) */
|
|
uae_u32 REGPARAM2 op_6001_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(0)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (T) */
|
|
uae_u32 REGPARAM2 op_60ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(0)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* BSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_6100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_s16 src = get_diword(2);
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (s & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BSRQ.B #<data> */
|
|
uae_u32 REGPARAM2 op_6101_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uae_s32 s;
|
|
uae_u32 src = srcreg;
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (s & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* BSR.L #<data>.L */
|
|
uae_u32 REGPARAM2 op_61ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 6;
|
|
if (s & 1) {
|
|
exception3_read_prefetch(opcode, oldpc + s);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_6200_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(2)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (HI) */
|
|
uae_u32 REGPARAM2 op_6201_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(2)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (HI) */
|
|
uae_u32 REGPARAM2 op_62ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(2)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_6300_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(3)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LS) */
|
|
uae_u32 REGPARAM2 op_6301_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(3)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LS) */
|
|
uae_u32 REGPARAM2 op_63ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(3)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_6400_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(4)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (CC) */
|
|
uae_u32 REGPARAM2 op_6401_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(4)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (CC) */
|
|
uae_u32 REGPARAM2 op_64ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(4)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_6500_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(5)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (CS) */
|
|
uae_u32 REGPARAM2 op_6501_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(5)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (CS) */
|
|
uae_u32 REGPARAM2 op_65ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(5)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_6600_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(6)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (NE) */
|
|
uae_u32 REGPARAM2 op_6601_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(6)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (NE) */
|
|
uae_u32 REGPARAM2 op_66ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(6)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_6700_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(7)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (EQ) */
|
|
uae_u32 REGPARAM2 op_6701_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(7)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (EQ) */
|
|
uae_u32 REGPARAM2 op_67ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(7)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_6800_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(8)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (VC) */
|
|
uae_u32 REGPARAM2 op_6801_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(8)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (VC) */
|
|
uae_u32 REGPARAM2 op_68ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(8)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_6900_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(9)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (VS) */
|
|
uae_u32 REGPARAM2 op_6901_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(9)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (VS) */
|
|
uae_u32 REGPARAM2 op_69ff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(9)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_6a00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(10)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (PL) */
|
|
uae_u32 REGPARAM2 op_6a01_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(10)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (PL) */
|
|
uae_u32 REGPARAM2 op_6aff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(10)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_6b00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(11)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (MI) */
|
|
uae_u32 REGPARAM2 op_6b01_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(11)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (MI) */
|
|
uae_u32 REGPARAM2 op_6bff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(11)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_6c00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(12)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (GE) */
|
|
uae_u32 REGPARAM2 op_6c01_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(12)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (GE) */
|
|
uae_u32 REGPARAM2 op_6cff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(12)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_6d00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(13)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LT) */
|
|
uae_u32 REGPARAM2 op_6d01_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(13)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LT) */
|
|
uae_u32 REGPARAM2 op_6dff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(13)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_6e00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(14)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (GT) */
|
|
uae_u32 REGPARAM2 op_6e01_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(14)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (GT) */
|
|
uae_u32 REGPARAM2 op_6eff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(14)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_6f00_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(15)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LE) */
|
|
uae_u32 REGPARAM2 op_6f01_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(15)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LE) */
|
|
uae_u32 REGPARAM2 op_6fff_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (src & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + (uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (cctrue(15)) {
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* MOVEQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_7000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_u32 src = srcreg;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B (An),Dn */
|
|
uae_u32 REGPARAM2 op_8010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_8018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B -(An),Dn */
|
|
uae_u32 REGPARAM2 op_8020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_8028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_8030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.B (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_8038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.B (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_8039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* OR.B (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_803a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_803b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_803c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_8050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_8058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_8060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_8068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_8070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_8078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_8079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* OR.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_807a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_807b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_807c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_8090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_8098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_80a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_80a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_80b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_80b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* OR.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_80ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_80bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* DIVU.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_80c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_80d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_80d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_80e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_80e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVU.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(0);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* DIVU.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_80f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVU.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_80f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(6);
|
|
Exception_cpu(5);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* DIVU.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_80fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVU.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(0);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* DIVU.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_80fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SBCD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int bcd = 0;
|
|
newv = tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
|
|
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
|
|
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SBCD.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_8108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int bcd = 0;
|
|
newv = tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
|
|
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
|
|
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_8110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_8118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_8120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_8128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_8130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_8138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_8139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* PACK.L Dn,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_8140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_u16 val = m68k_dreg(regs, srcreg) + get_diword(2);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* PACK.L -(An),-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_8148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_u16 val;
|
|
m68k_areg(regs, srcreg) -= 2;
|
|
val = (uae_u16)(get_word(m68k_areg(regs, srcreg)));
|
|
val += get_diword(2);
|
|
m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
|
|
put_byte(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* OR.W Dn,(An) */
|
|
uae_u32 REGPARAM2 op_8150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_8158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_8160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_8168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_8170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.W Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_8178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_8179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* UNPK.L Dn,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_8180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_u16 val = m68k_dreg(regs, srcreg);
|
|
val = ((val << 4) & 0xf00) | (val & 0xf);
|
|
val += get_diword(2);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* UNPK.L -(An),-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_8188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_u16 val;
|
|
m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
|
|
val = (uae_u16)(get_byte(m68k_areg(regs, srcreg)) & 0xff);
|
|
val = (((val << 4) & 0xf00) | (val & 0xf)) + get_diword(2);
|
|
m68k_areg(regs, dstreg) -= 2;
|
|
put_word(m68k_areg(regs, dstreg), val);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* OR.L Dn,(An) */
|
|
uae_u32 REGPARAM2 op_8190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_8198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_81a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_81a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_81b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* OR.L Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_81b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_81b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* DIVS.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_81c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_81d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_81d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_81e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_81e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVS.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_81f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(0);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* DIVS.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_81f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVS.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_81f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(6);
|
|
Exception_cpu(5);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* DIVS.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_81fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVS.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_81fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(0);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* DIVS.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_81fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B (An),Dn */
|
|
uae_u32 REGPARAM2 op_9010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_9018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B -(An),Dn */
|
|
uae_u32 REGPARAM2 op_9020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_9028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_9030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.B (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_9038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_9039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.B (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_903a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_903b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_903c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W An,Dn */
|
|
uae_u32 REGPARAM2 op_9048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_9050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_9058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_9060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_9068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_9070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_9078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_9079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_907a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_907b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_907c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L An,Dn */
|
|
uae_u32 REGPARAM2 op_9088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_9090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_9098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_90a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_90a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_90b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_90b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_90b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_90ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_90bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_90bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBA.W Dn,An */
|
|
uae_u32 REGPARAM2 op_90c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.W An,An */
|
|
uae_u32 REGPARAM2 op_90c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.W (An),An */
|
|
uae_u32 REGPARAM2 op_90d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.W (An)+,An */
|
|
uae_u32 REGPARAM2 op_90d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.W -(An),An */
|
|
uae_u32 REGPARAM2 op_90e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.W (d16,An),An */
|
|
uae_u32 REGPARAM2 op_90e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_90f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBA.W (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_90f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBA.W (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_90f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBA.W (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_90fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_90fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBA.W #<data>.W,An */
|
|
uae_u32 REGPARAM2 op_90fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBX.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_9108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_9110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_9118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_9120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_9128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_9130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_9138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_9139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBX.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.W -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_9148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W Dn,(An) */
|
|
uae_u32 REGPARAM2 op_9150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_9158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_9160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_9168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_9170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.W Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_9178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.W Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_9179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBX.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.L -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_9188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L Dn,(An) */
|
|
uae_u32 REGPARAM2 op_9190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_9198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_91a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_91a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_91b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUB.L Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_91b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_91b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBA.L Dn,An */
|
|
uae_u32 REGPARAM2 op_91c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.L An,An */
|
|
uae_u32 REGPARAM2 op_91c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.L (An),An */
|
|
uae_u32 REGPARAM2 op_91d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.L (An)+,An */
|
|
uae_u32 REGPARAM2 op_91d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.L -(An),An */
|
|
uae_u32 REGPARAM2 op_91e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBA.L (d16,An),An */
|
|
uae_u32 REGPARAM2 op_91e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_91f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBA.L (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_91f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBA.L (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_91f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBA.L (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_91fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUBA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_91fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* SUBA.L #<data>.L,An */
|
|
uae_u32 REGPARAM2 op_91fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.B (An),Dn */
|
|
uae_u32 REGPARAM2 op_b010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.B (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_b018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.B -(An),Dn */
|
|
uae_u32 REGPARAM2 op_b020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.B (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_b028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMP.B (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_b038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_b039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.B (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_b03a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b03b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMP.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_b03c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.W An,Dn */
|
|
uae_u32 REGPARAM2 op_b048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_b050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_b058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_b060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_b068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMP.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_b078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_b079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_b07a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b07b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMP.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_b07c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.L An,Dn */
|
|
uae_u32 REGPARAM2 op_b088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_b090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_b098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_b0a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMP.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_b0a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b0b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMP.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_b0b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_b0b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMP.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_b0ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMP.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b0bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMP.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_b0bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMPA.W Dn,An */
|
|
uae_u32 REGPARAM2 op_b0c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.W An,An */
|
|
uae_u32 REGPARAM2 op_b0c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.W (An),An */
|
|
uae_u32 REGPARAM2 op_b0d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.W (An)+,An */
|
|
uae_u32 REGPARAM2 op_b0d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.W -(An),An */
|
|
uae_u32 REGPARAM2 op_b0e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.W (d16,An),An */
|
|
uae_u32 REGPARAM2 op_b0e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMPA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_b0f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMPA.W (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_b0f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMPA.W (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_b0f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMPA.W (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_b0fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMPA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_b0fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMPA.W #<data>.W,An */
|
|
uae_u32 REGPARAM2 op_b0fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPM.B (An)+,(An)+ */
|
|
uae_u32 REGPARAM2 op_b108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_b110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_b118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_b120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_b128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_b130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* EOR.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_b138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_b139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPM.W (An)+,(An)+ */
|
|
uae_u32 REGPARAM2 op_b148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.W Dn,(An) */
|
|
uae_u32 REGPARAM2 op_b150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.W Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_b158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.W Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_b160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_b168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_b170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* EOR.W Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_b178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_b179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EOR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPM.L (An)+,(An)+ */
|
|
uae_u32 REGPARAM2 op_b188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.L Dn,(An) */
|
|
uae_u32 REGPARAM2 op_b190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.L Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_b198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.L Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_b1a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_b1a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_b1b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* EOR.L Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_b1b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.L Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_b1b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMPA.L Dn,An */
|
|
uae_u32 REGPARAM2 op_b1c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.L An,An */
|
|
uae_u32 REGPARAM2 op_b1c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.L (An),An */
|
|
uae_u32 REGPARAM2 op_b1d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.L (An)+,An */
|
|
uae_u32 REGPARAM2 op_b1d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.L -(An),An */
|
|
uae_u32 REGPARAM2 op_b1e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CMPA.L (d16,An),An */
|
|
uae_u32 REGPARAM2 op_b1e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMPA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_b1f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMPA.L (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_b1f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMPA.L (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_b1f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CMPA.L (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_b1fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CMPA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_b1fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* CMPA.L #<data>.L,An */
|
|
uae_u32 REGPARAM2 op_b1fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B (An),Dn */
|
|
uae_u32 REGPARAM2 op_c010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.B (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.B (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c03a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c03b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_c03c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_c050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c07a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c07b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_c07c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_c090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c0a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c0a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c0b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c0b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c0ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_c0bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULU.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c0c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_c0d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c0d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c0e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c0e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULU.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MULU.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c0f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULU.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c0f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULU.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c0fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULU.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MULU.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_c0fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ABCD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int cflg;
|
|
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
|
|
cflg = (newv & 0x3F0) > 0x90;
|
|
if (cflg) newv += 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ABCD.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_c108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int cflg;
|
|
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
|
|
cflg = (newv & 0x3F0) > 0x90;
|
|
if (cflg) newv += 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_c110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_c118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_c120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_c128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_c130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_c138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_c139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EXG.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EXG.L An,An */
|
|
uae_u32 REGPARAM2 op_c148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, srcreg) = (dst);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W Dn,(An) */
|
|
uae_u32 REGPARAM2 op_c150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_c158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_c160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_c168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_c170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.W Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_c178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_c179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* EXG.L Dn,An */
|
|
uae_u32 REGPARAM2 op_c188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
m68k_dreg(regs, srcreg) = (dst);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L Dn,(An) */
|
|
uae_u32 REGPARAM2 op_c190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_c198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_c1a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_c1a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_c1b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* AND.L Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_c1b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_c1b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULS.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c1c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_c1d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c1d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c1e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c1e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULS.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c1f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MULS.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c1f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULS.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c1f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULS.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c1fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULS.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c1fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* MULS.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_c1fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B (An),Dn */
|
|
uae_u32 REGPARAM2 op_d010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_d018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B -(An),Dn */
|
|
uae_u32 REGPARAM2 op_d020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_d028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.B (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_d038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_d039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.B (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_d03a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d03b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.B #<data>.B,Dn */
|
|
uae_u32 REGPARAM2 op_d03c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W An,Dn */
|
|
uae_u32 REGPARAM2 op_d048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_d050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_d058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_d060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_d068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_d078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_d079_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_d07a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d07b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_d07c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L An,Dn */
|
|
uae_u32 REGPARAM2 op_d088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_d090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_d098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_d0a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_d0a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d0b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_d0b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_d0b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_d0ba_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d0bb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_d0bc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDA.W Dn,An */
|
|
uae_u32 REGPARAM2 op_d0c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.W An,An */
|
|
uae_u32 REGPARAM2 op_d0c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.W (An),An */
|
|
uae_u32 REGPARAM2 op_d0d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.W (An)+,An */
|
|
uae_u32 REGPARAM2 op_d0d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.W -(An),An */
|
|
uae_u32 REGPARAM2 op_d0e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.W (d16,An),An */
|
|
uae_u32 REGPARAM2 op_d0e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_d0f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDA.W (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_d0f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDA.W (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_d0f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDA.W (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_d0fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_d0fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDA.W #<data>.W,An */
|
|
uae_u32 REGPARAM2 op_d0fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDX.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_d108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_d110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_d118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_d120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_d128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_d130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_d138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_d139_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDX.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.W -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_d148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W Dn,(An) */
|
|
uae_u32 REGPARAM2 op_d150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_d158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_d160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_d168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_d170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.W Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_d178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.W Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_d179_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDX.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.L -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_d188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L Dn,(An) */
|
|
uae_u32 REGPARAM2 op_d190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_d198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_d1a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_d1a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_d1b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
m68k_incpc(2);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADD.L Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_d1b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_d1b9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDA.L Dn,An */
|
|
uae_u32 REGPARAM2 op_d1c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.L An,An */
|
|
uae_u32 REGPARAM2 op_d1c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.L (An),An */
|
|
uae_u32 REGPARAM2 op_d1d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.L (An)+,An */
|
|
uae_u32 REGPARAM2 op_d1d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.L -(An),An */
|
|
uae_u32 REGPARAM2 op_d1e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDA.L (d16,An),An */
|
|
uae_u32 REGPARAM2 op_d1e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_d1f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDA.L (xxx).W,An */
|
|
uae_u32 REGPARAM2 op_d1f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDA.L (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_d1f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDA.L (d16,PC),An */
|
|
uae_u32 REGPARAM2 op_d1fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADDA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_d1fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ADDA.L #<data>.L,An */
|
|
uae_u32 REGPARAM2 op_d1fc_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ASRQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80 & val) >> 7;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
val = 0xff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e008_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG((cnt == 8) & (val >> 7));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (7 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 hival;
|
|
cnt &= 7;
|
|
hival = val << (8 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xff;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80 & val) >> 7;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
val = 0xff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG((cnt == 8) & (val >> 7));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 36) cnt -= 36;
|
|
if (cnt >= 18) cnt -= 18;
|
|
if (cnt >= 9) cnt -= 9;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (7 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 hival;
|
|
cnt &= 7;
|
|
hival = val << (8 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xff;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e040_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x8000 & val) >> 15;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
val = 0xffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e048_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG((cnt == 16) & (val >> 15));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e050_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (15 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e058_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 hival;
|
|
cnt &= 15;
|
|
hival = val << (16 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffff;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e060_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x8000 & val) >> 15;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
val = 0xffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e068_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG((cnt == 16) & (val >> 15));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e070_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 34) cnt -= 34;
|
|
if (cnt >= 17) cnt -= 17;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (15 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e078_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 hival;
|
|
cnt &= 15;
|
|
hival = val << (16 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffff;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e080_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80000000 & val) >> 31;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
val = 0xffffffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e088_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG((cnt == 32) & (val >> 31));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e090_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (31 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e098_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 hival;
|
|
cnt &= 31;
|
|
hival = val << (32 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffffffff;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80000000 & val) >> 31;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
val = 0xffffffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG((cnt == 32) & (val >> 31));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 33) cnt -= 33;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (31 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 hival;
|
|
cnt &= 31;
|
|
hival = val << (32 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffffffff;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRW.W (An) */
|
|
uae_u32 REGPARAM2 op_e0d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e0d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e0e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e0e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ASRW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e0f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ASRW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e0f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ASRW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e0f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ASLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e100_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e108_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e110_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (7 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e118_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 loval;
|
|
cnt &= 7;
|
|
loval = val >> (8 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e120_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e128_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e130_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 36) cnt -= 36;
|
|
if (cnt >= 18) cnt -= 18;
|
|
if (cnt >= 9) cnt -= 9;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (7 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e138_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 loval;
|
|
cnt &= 7;
|
|
loval = val >> (8 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e140_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e148_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e150_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (15 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e158_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 loval;
|
|
cnt &= 15;
|
|
loval = val >> (16 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e160_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e168_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e170_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 34) cnt -= 34;
|
|
if (cnt >= 17) cnt -= 17;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (15 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e178_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 loval;
|
|
cnt &= 15;
|
|
loval = val >> (16 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e180_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e188_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e190_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (31 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e198_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 loval;
|
|
cnt &= 31;
|
|
loval = val >> (32 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffffffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1a0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1a8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1b0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 33) cnt -= 33;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (31 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1b8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 loval;
|
|
cnt &= 31;
|
|
loval = val >> (32 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffffffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLW.W (An) */
|
|
uae_u32 REGPARAM2 op_e1d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e1d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e1e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e1e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ASLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e1f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ASLW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e1f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ASLW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e1f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* LSRW.W (An) */
|
|
uae_u32 REGPARAM2 op_e2d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e2d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e2e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e2e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LSRW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e2f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* LSRW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e2f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LSRW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e2f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* LSLW.W (An) */
|
|
uae_u32 REGPARAM2 op_e3d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e3d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e3e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e3e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LSLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e3f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* LSLW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e3f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* LSLW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e3f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ROXRW.W (An) */
|
|
uae_u32 REGPARAM2 op_e4d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e4d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e4e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e4e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ROXRW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e4f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ROXRW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e4f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ROXRW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e4f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ROXLW.W (An) */
|
|
uae_u32 REGPARAM2 op_e5d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e5d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e5e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e5e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ROXLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e5f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ROXLW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e5f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ROXLW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e5f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* RORW.W (An) */
|
|
uae_u32 REGPARAM2 op_e6d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e6d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e6e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e6e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* RORW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e6f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* RORW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e6f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* RORW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e6f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ROLW.W (An) */
|
|
uae_u32 REGPARAM2 op_e7d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLW.W (An)+ */
|
|
uae_u32 REGPARAM2 op_e7d8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg);
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLW.W -(An) */
|
|
uae_u32 REGPARAM2 op_e7e0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 data = get_word(dataa);
|
|
m68k_areg(regs, srcreg) = dataa;
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLW.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_e7e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ROLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e7f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
m68k_incpc(2);
|
|
dataa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* ROLW.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_e7f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ROLW.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_e7f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr dataa;
|
|
dataa = get_dilong(2);
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BFTST.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFTST.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e8fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9d0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9e8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9f0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9f8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9f9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9fa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTU.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_e9fb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFCHG.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eac0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = tmp ^ (0xffffffffu >> (32 - width));
|
|
tmp = bdata[0] | (tmp << (32 - width));
|
|
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFCHG.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ead0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = tmp ^ (0xffffffffu >> (32 - width));
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFCHG.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eae8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = tmp ^ (0xffffffffu >> (32 - width));
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFCHG.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eaf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = tmp ^ (0xffffffffu >> (32 - width));
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFCHG.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eaf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = tmp ^ (0xffffffffu >> (32 - width));
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFCHG.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eaf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = tmp ^ (0xffffffffu >> (32 - width));
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebe8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebfa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFEXTS.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ebfb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp = (uae_s32)tmp >> (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFCLR.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ecc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0;
|
|
tmp = bdata[0] | (tmp << (32 - width));
|
|
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFCLR.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ecd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0;
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFCLR.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ece8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0;
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFCLR.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ecf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0;
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFCLR.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ecf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0;
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFCLR.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ecf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0;
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_ede8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edf0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edf8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edf9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edfa_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_getpc() + 4;
|
|
dsta += (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFFFO.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_edfb_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
dsta = get_disp_ea_020(tmppc, 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 offset2 = offset;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
{ uae_u32 mask = 1 << (width - 1);
|
|
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
|
|
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFSET.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eec0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0xffffffffu >> (32 - width);
|
|
tmp = bdata[0] | (tmp << (32 - width));
|
|
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFSET.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eed0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0xffffffffu >> (32 - width);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFSET.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eee8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0xffffffffu >> (32 - width);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFSET.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eef0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0xffffffffu >> (32 - width);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFSET.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eef8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0xffffffffu >> (32 - width);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFSET.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eef9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = 0xffffffffu >> (32 - width);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* BFINS.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_efc0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp = m68k_dreg(regs, dstreg);
|
|
offset &= 0x1f;
|
|
tmp = (tmp << offset) | (tmp >> (32 - offset));
|
|
bdata[0] = tmp & ((1 << (32 - width)) - 1);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = m68k_dreg(regs, (extra >> 12) & 7);
|
|
tmp = tmp & (0xffffffffu >> (32 - width));
|
|
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
|
|
SET_ZFLG(tmp == 0);
|
|
tmp = bdata[0] | (tmp << (32 - width));
|
|
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFINS.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_efd0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = m68k_dreg(regs, (extra >> 12) & 7);
|
|
tmp = tmp & (0xffffffffu >> (32 - width));
|
|
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
|
|
SET_ZFLG(tmp == 0);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* BFINS.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_efe8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = m68k_dreg(regs, (extra >> 12) & 7);
|
|
tmp = tmp & (0xffffffffu >> (32 - width));
|
|
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
|
|
SET_ZFLG(tmp == 0);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFINS.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eff0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = m68k_dreg(regs, (extra >> 12) & 7);
|
|
tmp = tmp & (0xffffffffu >> (32 - width));
|
|
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
|
|
SET_ZFLG(tmp == 0);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* BFINS.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eff8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = m68k_dreg(regs, (extra >> 12) & 7);
|
|
tmp = tmp & (0xffffffffu >> (32 - width));
|
|
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
|
|
SET_ZFLG(tmp == 0);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* BFINS.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_eff9_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 extra = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_u32 bdata[2];
|
|
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
|
|
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
|
|
uae_u32 tmp;
|
|
dsta += offset >> 3;
|
|
tmp = get_bitfield(dsta, bdata, offset, width);
|
|
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
|
|
tmp >>= (32 - width);
|
|
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
|
|
tmp = m68k_dreg(regs, (extra >> 12) & 7);
|
|
tmp = tmp & (0xffffffffu >> (32 - width));
|
|
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
|
|
SET_ZFLG(tmp == 0);
|
|
put_bitfield(dsta, bdata, tmp, offset, width);
|
|
m68k_incpc(8);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MMUOP030.L Dn,#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f000_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uae_u16 extraa = 0;
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L An,#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f008_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uae_u16 extraa = 0;
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L (An),#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f010_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = m68k_areg(regs, srcreg);
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L (An)+,#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f018_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L -(An),#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f020_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = m68k_areg(regs, srcreg) - 4;
|
|
m68k_areg(regs, srcreg) = extraa;
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L (d16,An),#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f028_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(0);
|
|
m68k_incpc(2);
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L (d8,An,Xn),#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f030_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L (xxx).W,#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f038_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = (uae_s32)(uae_s16)get_diword(0);
|
|
m68k_incpc(2);
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MMUOP030.L (xxx).L,#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f039_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr pc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
uaecptr extraa;
|
|
extraa = get_dilong(0);
|
|
m68k_incpc(4);
|
|
mmu_op30(pc, opcode, extra, extraa);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f200_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f208_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f210_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f218_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f220_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f228_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f230_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f238_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f239_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f23a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,(d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f23b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FPP.L #<data>.W,#<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f23c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_arithmetic(opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f240_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FDBcc.L #<data>.W,Dn */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f248_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_dbcc (opcode, extra);
|
|
if (regs.fp_branch) {
|
|
regs.fp_branch = false;
|
|
if(regs.t0) check_t0_trace();
|
|
}
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f250_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f258_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f260_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f268_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f270_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f278_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FScc.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f279_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uae_s16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_scc (opcode, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FTRAPcc.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f27a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
uae_s16 dummy = get_diword(4);
|
|
m68k_incpc(6);
|
|
fpuop_trapcc (opcode, oldpc, extra);
|
|
|
|
#endif
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FTRAPcc.L #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f27b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
uae_s32 dummy;
|
|
dummy = get_dilong(4);
|
|
m68k_incpc(8);
|
|
fpuop_trapcc (opcode, oldpc, extra);
|
|
|
|
#endif
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FTRAPcc.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f27c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
|
|
#ifdef FPUEMU
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 extra = get_diword(2);
|
|
m68k_incpc(4);
|
|
fpuop_trapcc (opcode, oldpc, extra);
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FBccQ.L #<data>,#<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f280_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 63);
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
uaecptr pc = m68k_getpc();
|
|
uae_s16 extra = get_diword(0);
|
|
m68k_incpc(2);
|
|
fpuop_bcc (opcode, pc,extra);
|
|
if (regs.fp_branch) {
|
|
regs.fp_branch = false;
|
|
if(regs.t0) check_t0_trace();
|
|
}
|
|
|
|
#endif
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FBccQ.L #<data>,#<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f2c0_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 63);
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
uaecptr pc = m68k_getpc();
|
|
uae_s32 extra;
|
|
extra = get_dilong(0);
|
|
m68k_incpc(4);
|
|
fpuop_bcc (opcode, pc,extra);
|
|
if (regs.fp_branch) {
|
|
regs.fp_branch = false;
|
|
if(regs.t0) check_t0_trace();
|
|
}
|
|
|
|
#endif
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FSAVE.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f310_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_save (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FSAVE.L -(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f320_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_save (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FSAVE.L (d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f328_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_save (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FSAVE.L (d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f330_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_save (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FSAVE.L (xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f338_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_save (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FSAVE.L (xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f339_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_save (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f350_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f358_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f368_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f370_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f378_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f379_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (d16,PC) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f37a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* FRESTORE.L (d8,PC,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f37b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef FPUEMU
|
|
m68k_incpc(2);
|
|
fpuop_restore (opcode);
|
|
|
|
#endif
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVLQ.L #<data>,An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f408_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVPQ.L #<data>,An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f410_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f418_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f419_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f41a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f41b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f41c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f41d_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f41e_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CINVAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f41f_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHLQ.L #<data>,An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f428_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHPQ.L #<data>,An */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f430_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f438_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f439_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f43a_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f43b_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f43c_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f43d_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f43e_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* CPUSHAQ.L #<data> */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f43f_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 6) & 3);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
flush_cpu_caches_040(opcode);
|
|
if (opcode & 0x80) {
|
|
flush_icache((opcode >> 6) & 3);
|
|
}
|
|
check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSHN.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f500_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSH.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f508_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSHAN.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f510_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSHA.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f518_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PTESTW.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f548_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PTESTR.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f568_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PLPAW.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f588_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PLPAR.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f5c8_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MOVE16.L (An)+,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f600_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr memsa;
|
|
memsa = m68k_areg(regs, srcreg);
|
|
uaecptr memda;
|
|
memda = get_dilong(2);
|
|
memsa &= ~15;
|
|
memda &= ~15;
|
|
uae_u32 v[4];
|
|
v[0] = get_long(memsa);
|
|
v[1] = get_long(memsa + 4);
|
|
v[2] = get_long(memsa + 8);
|
|
v[3] = get_long(memsa + 12);
|
|
put_long(memda , v[0]);
|
|
put_long(memda + 4, v[1]);
|
|
put_long(memda + 8, v[2]);
|
|
put_long(memda + 12, v[3]);
|
|
m68k_areg(regs, srcreg) += 16;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MOVE16.L (xxx).L,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f608_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr memsa;
|
|
memsa = get_dilong(2);
|
|
uaecptr memda;
|
|
memda = m68k_areg(regs, dstreg);
|
|
memsa &= ~15;
|
|
memda &= ~15;
|
|
uae_u32 v[4];
|
|
v[0] = get_long(memsa);
|
|
v[1] = get_long(memsa + 4);
|
|
v[2] = get_long(memsa + 8);
|
|
v[3] = get_long(memsa + 12);
|
|
put_long(memda , v[0]);
|
|
put_long(memda + 4, v[1]);
|
|
put_long(memda + 8, v[2]);
|
|
put_long(memda + 12, v[3]);
|
|
m68k_areg(regs, dstreg) += 16;
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MOVE16.L (An),(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f610_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr memsa;
|
|
memsa = m68k_areg(regs, srcreg);
|
|
uaecptr memda;
|
|
memda = get_dilong(2);
|
|
memsa &= ~15;
|
|
memda &= ~15;
|
|
uae_u32 v[4];
|
|
v[0] = get_long(memsa);
|
|
v[1] = get_long(memsa + 4);
|
|
v[2] = get_long(memsa + 8);
|
|
v[3] = get_long(memsa + 12);
|
|
put_long(memda , v[0]);
|
|
put_long(memda + 4, v[1]);
|
|
put_long(memda + 8, v[2]);
|
|
put_long(memda + 12, v[3]);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MOVE16.L (xxx).L,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f618_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uaecptr memsa;
|
|
memsa = get_dilong(2);
|
|
uaecptr memda;
|
|
memda = m68k_areg(regs, dstreg);
|
|
memsa &= ~15;
|
|
memda &= ~15;
|
|
uae_u32 v[4];
|
|
v[0] = get_long(memsa);
|
|
v[1] = get_long(memsa + 4);
|
|
v[2] = get_long(memsa + 8);
|
|
v[3] = get_long(memsa + 12);
|
|
put_long(memda , v[0]);
|
|
put_long(memda + 4, v[1]);
|
|
put_long(memda + 8, v[2]);
|
|
put_long(memda + 12, v[3]);
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* MOVE16.L (An)+,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f620_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = 0;
|
|
uaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;
|
|
dstreg = (get_diword(2) >> 12) & 7;
|
|
memd = m68k_areg(regs, dstreg) & ~15;
|
|
uae_u32 v[4];
|
|
v[0] = get_long(mems);
|
|
v[1] = get_long(mems + 4);
|
|
v[2] = get_long(mems + 8);
|
|
v[3] = get_long(mems + 12);
|
|
put_long(memd , v[0]);
|
|
put_long(memd + 4, v[1]);
|
|
put_long(memd + 8, v[2]);
|
|
put_long(memd + 12, v[3]);
|
|
if (srcreg != dstreg)
|
|
m68k_areg(regs, srcreg) += 16;
|
|
m68k_areg(regs, dstreg) += 16;
|
|
m68k_incpc(4);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* LPSTOP.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f800_0_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 sw = get_diword(2);
|
|
if (sw != 0x01c0) {
|
|
Exception(11);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (!(regs.sr & 0x2000)) {
|
|
Exception(8);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u16 newsr = get_diword(4);
|
|
if (!(newsr & 0x2000)) {
|
|
Exception(8);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr = newsr;
|
|
checkint();
|
|
MakeFromSR_STOP();
|
|
m68k_setstopped(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* ORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_003c_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr |= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_007c_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr |= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_023c_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
src |= 0xff00;
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_027c_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr &= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a3c_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a7c_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr ^= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CAS.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ad0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ad8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ae0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ae8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af9_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_byte(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(8);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cd0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cd8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ce0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ce8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf9_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_word(dsta, dst);
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(8);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS2.W #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cfc_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 extra;
|
|
extra = get_dilong(2);
|
|
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
|
|
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
|
|
uae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);
|
|
uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
|
|
int flgo = ((uae_s16)(dst1)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg(regs, extra & 7)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, extra & 7))) < 0;
|
|
int flgo = ((uae_s16)(dst2)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, extra & 7))) > ((uae_u16)(dst2)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(rn2, m68k_dreg(regs, (extra >> 6) & 7));
|
|
put_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));
|
|
}
|
|
}
|
|
if (!GET_ZFLG()) {
|
|
m68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);
|
|
m68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e10_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e18_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e20_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e28_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e30_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e38_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e39_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e50_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e58_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e60_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e68_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e70_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_word(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e78_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e79_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e90_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e98_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ea0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ea8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_long(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb9_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ed0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ed8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ee0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
mmufixup[0].reg = dstreg | 0x0;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ee8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef0_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef8_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (36 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef9_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
put_long(dsta, dst);
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(8);
|
|
return (40 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS2.L #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0efc_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 extra;
|
|
extra = get_dilong(2);
|
|
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
|
|
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
|
|
uae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);
|
|
uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
|
|
int flgo = ((uae_s32)(dst1)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg(regs, extra & 7)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, extra & 7))) < 0;
|
|
int flgo = ((uae_s32)(dst2)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, extra & 7))) > ((uae_u32)(dst2)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(rn2, m68k_dreg(regs, (extra >> 6) & 7));
|
|
put_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));
|
|
}
|
|
}
|
|
if (!GET_ZFLG()) {
|
|
m68k_dreg(regs, (extra >> 16) & 7) = dst1;
|
|
m68k_dreg(regs, (extra >> 0) & 7) = dst2;
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* LINK.L An,#<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4808_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr olda;
|
|
olda = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = olda;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 offs;
|
|
offs = get_dilong(2);
|
|
put_long(olda, src);
|
|
m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
|
|
m68k_areg(regs, 7) += offs;
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* LINK.W An,#<data>.W */
|
|
uae_u32 REGPARAM2 op_4e50_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr olda;
|
|
olda = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = olda;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
put_long(olda, src);
|
|
m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
|
|
m68k_areg(regs, 7) += offs;
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVR2USP.L An */
|
|
uae_u32 REGPARAM2 op_4e60_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
regs.usp = src;
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOP.L */
|
|
uae_u32 REGPARAM2 op_4e71_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* STOP.L #<data>.W */
|
|
uae_u32 REGPARAM2 op_4e72_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
if (!regs.stopped) {
|
|
uae_s16 src = get_diword(2);
|
|
regs.ir = src;
|
|
}
|
|
uae_u16 sr = regs.ir;
|
|
regs.sr = sr;
|
|
checkint();
|
|
MakeFromSR_STOP();
|
|
do_cycles_stop(4);
|
|
m68k_setstopped(1);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
/* RTE.L */
|
|
uae_u32 REGPARAM2 op_4e73_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 oldsr = regs.sr, newsr;
|
|
uae_u32 newpc;
|
|
for (;;) {
|
|
uaecptr a = m68k_areg(regs, 7);
|
|
uae_u16 sr = get_word(a);
|
|
uae_u32 pc = get_long(a + 2);
|
|
uae_u16 format = get_word(a + 2 + 4);
|
|
int frame = format >> 12;
|
|
int offset = 8;
|
|
newsr = sr; newpc = pc;
|
|
if (frame == 0x0) {
|
|
m68k_areg(regs, 7) += offset; break; }
|
|
else if (frame == 0x1) {
|
|
m68k_areg(regs, 7) += offset; }
|
|
else if (frame == 0x2) {
|
|
m68k_areg(regs, 7) += offset + 4; break; }
|
|
else if (frame == 0x3) {
|
|
m68k_areg(regs, 7) += offset + 4; break; }
|
|
else if (frame == 0x4) {
|
|
m68k_areg(regs, 7) += offset + 8; break; }
|
|
else if (frame == 0x7) {
|
|
m68k_areg(regs, 7) += offset + 52; break; }
|
|
else {
|
|
Exception_cpu(14);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr = newsr;
|
|
oldsr = newsr;
|
|
MakeFromSR_T0();
|
|
}
|
|
regs.sr = newsr;
|
|
MakeFromSR_T0();
|
|
if (newpc & 1) {
|
|
MakeFromSR();
|
|
exception3_read_prefetch_68040bug(opcode, newpc, oldsr);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(newpc);
|
|
#ifdef DEBUGGER
|
|
branch_stack_pop_rte(oldpc);
|
|
#endif
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* RTR.L */
|
|
uae_u32 REGPARAM2 op_4e77_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
MakeSR();
|
|
uaecptr sra;
|
|
sra = m68k_areg(regs, 7);
|
|
uae_s16 sr = get_word(sra);
|
|
m68k_areg(regs, 7) += 2;
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
if (pc & 1) {
|
|
m68k_areg(regs, 7) -= 6;
|
|
uae_u16 oldsr = regs.sr;
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
exception3_read_prefetch_68040bug(opcode, pc, oldsr);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
m68k_setpc_j(pc);
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* MOVE2C.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4e7b_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
int regno = (src >> 12) & 15;
|
|
uae_u32 *regp = regs.regs + regno;
|
|
if (!m68k_move2c(src & 0xFFF, regp)) {
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* PFLUSHN.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f500_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
if(regs.t0) check_t0_trace();
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSH.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f508_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
if(regs.t0) check_t0_trace();
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSHAN.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f510_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
if(regs.t0) check_t0_trace();
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PFLUSHA.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f518_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
if(regs.t0) check_t0_trace();
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PTESTW.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f548_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
if(regs.t0) check_t0_trace();
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* PTESTR.L (An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_f568_1_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_incpc(2);
|
|
mmu_op(opcode, 0);
|
|
if(regs.t0) check_t0_trace();
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
#endif
|
|
/* ORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_003c_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr |= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_007c_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr |= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_023c_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
src |= 0xff00;
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_027c_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr &= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a3c_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a7c_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr ^= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CAS.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ad0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ad8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x100;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ae0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
mmufixup[0].reg = dstreg | 0x200;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ae8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0af9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_byte(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
|
|
}
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cd0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cd8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x500;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ce0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
mmufixup[0].reg = dstreg | 0x600;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ce8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cf9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s16 dst = get_word(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
|
|
}
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS2.W #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0cfc_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 extra;
|
|
extra = get_dilong(2);
|
|
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
|
|
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
|
|
uae_u16 dst1 = get_word(rn1), dst2 = get_word(rn2);
|
|
uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
|
|
int flgo = ((uae_s16)(dst1)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg(regs, extra & 7)));
|
|
int flgs = ((uae_s16)(m68k_dreg(regs, extra & 7))) < 0;
|
|
int flgo = ((uae_s16)(dst2)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(m68k_dreg(regs, extra & 7))) > ((uae_u16)(dst2)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_word(rn2, m68k_dreg(regs, (extra >> 6) & 7));
|
|
put_word(rn1, m68k_dreg(regs, (extra >> 22) & 7));
|
|
}
|
|
}
|
|
if (!GET_ZFLG()) {
|
|
m68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);
|
|
m68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e10_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e18_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e20_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e28_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e30_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e38_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.B #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e39_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e50_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e58_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e60_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e68_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e70_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_word(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e78_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e79_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e90_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e98_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ea0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
m68k_areg(regs, dstreg) = srca;
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(4);
|
|
}
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ea8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
dfc_nommu_put_long(dsta, src);
|
|
} else {
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 1);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,2 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(8);
|
|
}
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ed0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(An)+ */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ed8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
mmufixup[0].reg = dstreg | 0x900;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,-(An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ee0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
mmufixup[0].reg = dstreg | 0xa00;
|
|
mmufixup[0].value = m68k_areg(regs, dstreg);
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(4);
|
|
mmufixup[0].reg = -1;
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(d16,An) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ee8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
m68k_incpc(4);
|
|
dsta = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(xxx).W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* CAS.L #<data>.W,(xxx).L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0ef9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s32 dst = get_long(dsta);
|
|
int ru = (src >> 6) & 7;
|
|
int rc = src & 7;
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(dsta, (m68k_dreg(regs, ru)));
|
|
} else {
|
|
m68k_dreg(regs, rc) = dst;
|
|
}
|
|
m68k_incpc(8);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
#endif
|
|
/* CAS2.L #<data>.L */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0efc_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 extra;
|
|
extra = get_dilong(2);
|
|
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
|
|
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
|
|
uae_u32 dst1 = get_long(rn1), dst2 = get_long(rn2);
|
|
uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
|
|
int flgo = ((uae_s32)(dst1)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg(regs, extra & 7)));
|
|
int flgs = ((uae_s32)(m68k_dreg(regs, extra & 7))) < 0;
|
|
int flgo = ((uae_s32)(dst2)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(m68k_dreg(regs, extra & 7))) > ((uae_u32)(dst2)));
|
|
SET_NFLG(flgn != 0);
|
|
if (GET_ZFLG()) {
|
|
put_long(rn2, m68k_dreg(regs, (extra >> 6) & 7));
|
|
put_long(rn1, m68k_dreg(regs, (extra >> 22) & 7));
|
|
}
|
|
}
|
|
if (!GET_ZFLG()) {
|
|
m68k_dreg(regs, (extra >> 0) & 7) = dst2;
|
|
m68k_dreg(regs, (extra >> 16) & 7) = dst1;
|
|
}
|
|
m68k_incpc(6);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
#endif
|
|
/* NBCD.B Dn */
|
|
uae_u32 REGPARAM2 op_4800_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (An) */
|
|
uae_u32 REGPARAM2 op_4810_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4818_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B -(An) */
|
|
uae_u32 REGPARAM2 op_4820_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4828_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4830_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 */
|
|
|
|
/* NBCD.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4838_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4839_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4890_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_48a0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 0;
|
|
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
|
|
int type = 1;
|
|
while (amask) {
|
|
srca -= 2;
|
|
if (!type || movem_index2[amask] != dstreg) {
|
|
put_word(srca, m68k_areg(regs, movem_index2[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
} else {
|
|
put_word(srca, m68k_areg(regs, movem_index2[amask]) - 2);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
}
|
|
amask = movem_next[amask];
|
|
}
|
|
while (dmask) {
|
|
srca -= 2;
|
|
put_word(srca, m68k_dreg(regs, movem_index2[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_48a8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_48b0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_48b8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_48b9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_48d0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_48e0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 0;
|
|
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
|
|
int type = 1;
|
|
while (amask) {
|
|
srca -= 4;
|
|
if (!type || movem_index2[amask] != dstreg) {
|
|
put_long(srca, m68k_areg(regs, movem_index2[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
} else {
|
|
put_long(srca, m68k_areg(regs, movem_index2[amask]) - 4);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
}
|
|
amask = movem_next[amask];
|
|
}
|
|
while (dmask) {
|
|
srca -= 4;
|
|
put_long(srca, m68k_dreg(regs, movem_index2[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_48e8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_48f0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_48f8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_48f9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4c90_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_4c98_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_4ca8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4cb0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_4cb8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_4cb9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_4cba_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 4;
|
|
srca += (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4cbb_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4cd0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_4cd8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_4ce8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4cf0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
srca = get_disp_ea_020(m68k_areg(regs, dstreg), 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_4cf8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_4cf9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_4cfa_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 4;
|
|
srca += (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4cfb_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
m68k_incpc(4);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 2,0 */
|
|
|
|
/* MVR2USP.L An */
|
|
uae_u32 REGPARAM2 op_4e60_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
regs.usp = src;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NOP.L */
|
|
uae_u32 REGPARAM2 op_4e71_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* STOP.L #<data>.W */
|
|
uae_u32 REGPARAM2 op_4e72_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
if (!regs.stopped) {
|
|
uae_s16 src = get_diword(2);
|
|
regs.ir = src;
|
|
}
|
|
uae_u16 sr = regs.ir;
|
|
regs.sr = sr;
|
|
checkint();
|
|
MakeFromSR_STOP();
|
|
do_cycles_stop(4);
|
|
m68k_setstopped(1);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
/* RTE.L */
|
|
uae_u32 REGPARAM2 op_4e73_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 oldsr = regs.sr, newsr;
|
|
uae_u32 newpc;
|
|
for (;;) {
|
|
uaecptr a = m68k_areg(regs, 7);
|
|
uae_u16 sr = get_word(a);
|
|
uae_u32 pc = get_long(a + 2);
|
|
uae_u16 format = get_word(a + 2 + 4);
|
|
int frame = format >> 12;
|
|
int offset = 8;
|
|
newsr = sr; newpc = pc;
|
|
if (frame == 0x0) {
|
|
m68k_areg(regs, 7) += offset; break; }
|
|
else if (frame == 0x1) {
|
|
m68k_areg(regs, 7) += offset; }
|
|
else if (frame == 0x2) {
|
|
m68k_areg(regs, 7) += offset + 4; break; }
|
|
else if (frame == 0x9) {
|
|
m68k_areg(regs, 7) += offset + 12; break; }
|
|
else if (frame == 0xa) {
|
|
m68k_areg(regs, 7) += offset + 24; break; }
|
|
else if (frame == 0xb) {
|
|
m68k_areg(regs, 7) += offset + 84; break; }
|
|
else {
|
|
regs.t1 = regs.t0 = 0;
|
|
Exception_cpu(14);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr = newsr;
|
|
oldsr = newsr;
|
|
MakeFromSR_T0();
|
|
}
|
|
regs.sr = newsr;
|
|
MakeFromSR_T0();
|
|
if (newpc & 1) {
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(newpc);
|
|
#ifdef DEBUGGER
|
|
branch_stack_pop_rte(oldpc);
|
|
#endif
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* RTD.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4e74_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
uae_s16 offs = get_diword(2);
|
|
m68k_areg(regs, 7) += offs;
|
|
if (pc & 1) {
|
|
exception3_read_prefetch_only(opcode, pc);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(pc);
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
#endif
|
|
/* RTS.L */
|
|
uae_u32 REGPARAM2 op_4e75_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
m68k_do_rts();
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_pop_rts(oldpc);
|
|
}
|
|
#endif
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc);
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* RTR.L */
|
|
uae_u32 REGPARAM2 op_4e77_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
MakeSR();
|
|
uaecptr sra;
|
|
sra = m68k_areg(regs, 7);
|
|
uae_s16 sr = get_word(sra);
|
|
m68k_areg(regs, 7) += 2;
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
m68k_setpc_j(pc);
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc + 2);
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* MOVE2C.L #<data>.W */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_4e7b_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
int regno = (src >> 12) & 15;
|
|
uae_u32 *regp = regs.regs + regno;
|
|
if (!m68k_move2c(src & 0xFFF, regp)) {
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
#endif
|
|
/* JSR.L (An) */
|
|
uae_u32 REGPARAM2 op_4e90_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* JSR.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ea8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4eb0_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
srca = get_disp_ea_020(m68k_areg(regs, srcreg), 0);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 0;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 B */
|
|
|
|
/* JSR.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4eb8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4eb9_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 6;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* JSR.L (d16,PC) */
|
|
uae_u32 REGPARAM2 op_4eba_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4ebb_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
m68k_incpc(2);
|
|
uaecptr tmppc = m68k_getpc();
|
|
srca = get_disp_ea_020(tmppc, 0);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 0;
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_getpc() & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 2,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_50c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(0)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (F) */
|
|
uae_u32 REGPARAM2 op_51c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(1)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_52c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(2)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_53c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(3)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_54c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(4)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_55c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(5)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_56c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(6)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_57c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(7)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_58c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(8)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_59c8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(9)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_5ac8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(10)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_5bc8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(11)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_5cc8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(12)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_5dc8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(13)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_5ec8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(14)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_5fc8_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(15)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_6000_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(0)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (T) */
|
|
uae_u32 REGPARAM2 op_6001_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(0)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (T) */
|
|
uae_u32 REGPARAM2 op_60ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(0)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* BSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_6100_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_s16 src = get_diword(2);
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (s & 1) {
|
|
m68k_areg(regs, 7) -= 4;
|
|
exception3_read_prefetch(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BSRQ.B #<data> */
|
|
uae_u32 REGPARAM2 op_6101_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uae_s32 s;
|
|
uae_u32 src = srcreg;
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (s & 1) {
|
|
m68k_areg(regs, 7) -= 4;
|
|
exception3_read_prefetch(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* BSR.L #<data>.L */
|
|
uae_u32 REGPARAM2 op_61ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 6;
|
|
if (s & 1) {
|
|
m68k_areg(regs, 7) -= 4;
|
|
exception3_read_prefetch(opcode, oldpc + s);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
if(regs.t0) check_t0_trace();
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_6200_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(2)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (HI) */
|
|
uae_u32 REGPARAM2 op_6201_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(2)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (HI) */
|
|
uae_u32 REGPARAM2 op_62ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(2)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_6300_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(3)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LS) */
|
|
uae_u32 REGPARAM2 op_6301_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(3)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LS) */
|
|
uae_u32 REGPARAM2 op_63ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(3)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_6400_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(4)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (CC) */
|
|
uae_u32 REGPARAM2 op_6401_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(4)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (CC) */
|
|
uae_u32 REGPARAM2 op_64ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(4)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_6500_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(5)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (CS) */
|
|
uae_u32 REGPARAM2 op_6501_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(5)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (CS) */
|
|
uae_u32 REGPARAM2 op_65ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(5)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_6600_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(6)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (NE) */
|
|
uae_u32 REGPARAM2 op_6601_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(6)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (NE) */
|
|
uae_u32 REGPARAM2 op_66ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(6)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_6700_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(7)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (EQ) */
|
|
uae_u32 REGPARAM2 op_6701_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(7)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (EQ) */
|
|
uae_u32 REGPARAM2 op_67ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(7)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_6800_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(8)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (VC) */
|
|
uae_u32 REGPARAM2 op_6801_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(8)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (VC) */
|
|
uae_u32 REGPARAM2 op_68ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(8)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_6900_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(9)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (VS) */
|
|
uae_u32 REGPARAM2 op_6901_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(9)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (VS) */
|
|
uae_u32 REGPARAM2 op_69ff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(9)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_6a00_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(10)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (PL) */
|
|
uae_u32 REGPARAM2 op_6a01_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(10)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (PL) */
|
|
uae_u32 REGPARAM2 op_6aff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(10)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_6b00_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(11)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (MI) */
|
|
uae_u32 REGPARAM2 op_6b01_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(11)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (MI) */
|
|
uae_u32 REGPARAM2 op_6bff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(11)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_6c00_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(12)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (GE) */
|
|
uae_u32 REGPARAM2 op_6c01_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(12)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (GE) */
|
|
uae_u32 REGPARAM2 op_6cff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(12)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_6d00_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(13)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LT) */
|
|
uae_u32 REGPARAM2 op_6d01_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(13)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LT) */
|
|
uae_u32 REGPARAM2 op_6dff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(13)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_6e00_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(14)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (GT) */
|
|
uae_u32 REGPARAM2 op_6e01_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(14)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (GT) */
|
|
uae_u32 REGPARAM2 op_6eff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(14)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_6f00_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(15)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LE) */
|
|
uae_u32 REGPARAM2 op_6f01_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(15)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LE) */
|
|
uae_u32 REGPARAM2 op_6fff_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
if (cctrue(15)) {
|
|
if (src & 1) {
|
|
uaecptr addr = m68k_getpc() + (uae_s32)src + 2;
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
if(regs.t0) check_t0_trace();
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* SBCD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8100_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int bcd = 0;
|
|
newv = tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
|
|
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
|
|
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SBCD.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_8108_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int bcd = 0;
|
|
newv = tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
|
|
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
|
|
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ABCD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c100_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int cflg;
|
|
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
|
|
cflg = (newv & 0x3F0) > 0x90;
|
|
if (cflg) newv += 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ABCD.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_c108_2_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int cflg;
|
|
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
|
|
cflg = (newv & 0x3F0) > 0x90;
|
|
if (cflg) newv += 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG(0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_003c_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr |= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_007c_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr |= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_023c_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
src |= 0xff00;
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_027c_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr &= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a3c_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a7c_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
if(regs.t0) check_t0_trace();
|
|
regs.sr ^= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* STOP.L #<data>.W */
|
|
uae_u32 REGPARAM2 op_4e72_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
if (!regs.stopped) {
|
|
uae_s16 src = get_diword(2);
|
|
regs.ir = src;
|
|
}
|
|
uae_u16 sr = regs.ir;
|
|
regs.sr = sr;
|
|
checkint();
|
|
MakeFromSR_STOP();
|
|
do_cycles_stop(4);
|
|
m68k_setstopped(1);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
/* RTE.L */
|
|
uae_u32 REGPARAM2 op_4e73_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 oldsr = regs.sr, newsr;
|
|
uae_u32 newpc;
|
|
for (;;) {
|
|
uaecptr a = m68k_areg(regs, 7);
|
|
uae_u16 sr = get_word(a);
|
|
uae_u32 pc = get_long(a + 2);
|
|
uae_u16 format = get_word(a + 2 + 4);
|
|
int frame = format >> 12;
|
|
int offset = 8;
|
|
newsr = sr; newpc = pc;
|
|
if (frame == 0x0) {
|
|
m68k_areg(regs, 7) += offset; break; }
|
|
else if (frame == 0x1) {
|
|
m68k_areg(regs, 7) += offset; }
|
|
else if (frame == 0x2) {
|
|
m68k_areg(regs, 7) += offset + 4; break; }
|
|
else if (frame == 0x9) {
|
|
m68k_areg(regs, 7) += offset + 12; break; }
|
|
else if (frame == 0xa) {
|
|
m68k_areg(regs, 7) += offset + 24; break; }
|
|
else if (frame == 0xb) {
|
|
m68k_areg(regs, 7) += offset + 84; break; }
|
|
else {
|
|
Exception_cpu(14);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
regs.sr = newsr;
|
|
oldsr = newsr;
|
|
MakeFromSR_T0();
|
|
}
|
|
regs.sr = newsr;
|
|
MakeFromSR_T0();
|
|
if (newpc & 1) {
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(newpc);
|
|
#ifdef DEBUGGER
|
|
branch_stack_pop_rte(oldpc);
|
|
#endif
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* RTR.L */
|
|
uae_u32 REGPARAM2 op_4e77_3_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
MakeSR();
|
|
uaecptr sra;
|
|
sra = m68k_areg(regs, 7);
|
|
uae_s16 sr = get_word(sra);
|
|
m68k_areg(regs, 7) += 2;
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
m68k_setpc_j(pc);
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc + 2);
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if(regs.t0) check_t0_trace();
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* OR.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* ORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_003c_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr |= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* ORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_007c_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
regs.sr |= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_00b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* BTST.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* BTST.B Dn,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_013b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = 3;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
dsta = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* BCHG.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_0140_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
if (src > 15) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
}
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCHG.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* BCLR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_0180_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
if (src > 15) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
}
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_01b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* BSET.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_01c0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
if (src > 15) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
}
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BSET.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_01f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0230_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* ANDSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_023c_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
src |= 0xff00;
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0270_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* ANDSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_027c_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
regs.sr &= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_02b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* SUB.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0430_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* SUB.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0470_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* SUB.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_04b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* ADD.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0630_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* ADD.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0670_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* ADD.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_06b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* BTST.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0830_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* BTST.B #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_083b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
uaecptr tmppc = m68k_getpc() + 4;
|
|
dsta = get_disp_ea_000(tmppc, get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* BCHG.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0840_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
if (src > 15) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
}
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCHG.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0870_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
dst ^= (1 << src);
|
|
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* BCLR.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_0880_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
if (src > 15) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
}
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_08b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* BSET.L #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_08c0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= 31;
|
|
if (src > 15) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
}
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
m68k_dreg(regs, dstreg) = (dst);
|
|
m68k_incpc(4);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BSET.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_08f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst |= (1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* EOR.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0a30_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* EORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a3c_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0a70_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* EORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a7c_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
uae_s16 src = get_diword(2);
|
|
regs.sr ^= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0ab0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* CMP.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0c30_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* CMP.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0c70_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* CMP.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_0cb0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* MOVES.B #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e30_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
dfc_nommu_put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 src = sfc_nommu_get_byte(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,4 */
|
|
|
|
#endif
|
|
/* MOVES.W #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0e70_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
dfc_nommu_put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s16 src = sfc_nommu_get_word(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,4 */
|
|
|
|
#endif
|
|
/* MOVES.L #<data>.W,(d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_0eb0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 extra = get_diword(2);
|
|
if (extra & 0x800) {
|
|
uae_u32 src = regs.regs[(extra >> 12) & 15];
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
src = regs.regs[(extra >> 12) & 15];
|
|
dfc_nommu_put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
} else {
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s32 src = sfc_nommu_get_long(srca);
|
|
if (extra & 0x8000) {
|
|
m68k_areg(regs, (extra >> 12) & 7) = src;
|
|
} else {
|
|
m68k_dreg(regs, (extra >> 12) & 7) = (src);
|
|
}
|
|
m68k_incpc(6);
|
|
}
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,4 */
|
|
|
|
#endif
|
|
/* MOVE.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_1030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_103b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_10b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_10bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_10f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_10fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_1130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_113b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_1170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_117b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_1180_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_1190_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (An)+,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_1198_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B -(An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11a0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.B (d16,An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11a8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,4 */
|
|
|
|
/* MOVE.B (xxx).W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11b8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.B (xxx).L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11b9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* MOVE.B (d16,PC),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11ba_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,4 */
|
|
|
|
/* MOVE.B #<data>.B,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_11bc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = get_dibyte(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_11fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.B (d8,An,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 8,0 */
|
|
|
|
/* MOVE.B (d8,PC,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_13fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 8,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_2030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_203b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVEA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_2070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVEA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_207b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_20b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_20bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_20f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_20fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_2130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_213b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_2170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_217b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2180_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L An,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2188_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2190_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (An)+,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_2198_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L -(An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21a0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.L (d16,An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21a8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,4 */
|
|
|
|
/* MOVE.L (xxx).W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21b8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.L (xxx).L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21b9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* MOVE.L (d16,PC),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21ba_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (32 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,4 */
|
|
|
|
/* MOVE.L #<data>.L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_21bc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_21fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(6);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.L (d8,An,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 8,0 */
|
|
|
|
/* MOVE.L (d8,PC,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_23fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(8);
|
|
return (34 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 8,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_3030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_303b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVEA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_3070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVEA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_307b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
src = (uae_s32)(uae_s16)src;
|
|
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_30b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(An) */
|
|
uae_u32 REGPARAM2 op_30bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_30f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(An)+ */
|
|
uae_u32 REGPARAM2 op_30fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
m68k_areg(regs, dstreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_3130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),-(An) */
|
|
uae_u32 REGPARAM2 op_313b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_3170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(d16,An) */
|
|
uae_u32 REGPARAM2 op_317b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3180_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W An,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3188_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_areg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3190_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (An)+,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_3198_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W -(An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31a0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MOVE.W (d16,An),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31a8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,4 */
|
|
|
|
/* MOVE.W (xxx).W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31b8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.W (xxx).L,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31b9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(6));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 4,0 */
|
|
|
|
/* MOVE.W (d16,PC),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31ba_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,4 */
|
|
|
|
/* MOVE.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_31bc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(xxx).W */
|
|
uae_u32 REGPARAM2 op_31fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 6,0 */
|
|
|
|
/* MOVE.W (d8,An,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 8,0 */
|
|
|
|
/* MOVE.W (d8,PC,Xn),(xxx).L */
|
|
uae_u32 REGPARAM2 op_33fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(8);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 8,0 */
|
|
|
|
/* NEGX.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NEGX.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(srca, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NEGX.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_40b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(srca, newv);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MVSR2.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_40f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
MakeSR();
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CHK.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_41b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CHK.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_41bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
m68k_incpc(4);
|
|
if (dst > src) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if ((uae_s32)dst < 0) {
|
|
setchkundefinedflags(src, dst, 1);
|
|
Exception_cpu(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
setchkundefinedflags(src, dst, 1);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* LEA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_41f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* LEA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_41fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CLR.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4230_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CLR.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4270_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CLR.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_42b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
struct flag_struct oldflags;
|
|
oldflags.cznv = regflags.cznv;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MVSR2.B (d8,An,Xn) */
|
|
#ifndef CPUEMU_68000_ONLY
|
|
uae_u32 REGPARAM2 op_42f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
MakeSR();
|
|
put_word(srca, regs.sr & 0xff);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
#endif
|
|
/* NEG.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4430_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(0)) < 0;
|
|
int flgn = ((uae_s8)(dst)) < 0;
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NEG.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4470_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(0)) < 0;
|
|
int flgn = ((uae_s16)(dst)) < 0;
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NEG.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_44b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(0)) < 0;
|
|
int flgn = ((uae_s32)(dst)) < 0;
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_44f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.B (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_44fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NOT.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4630_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(dst)) == 0);
|
|
SET_NFLG(((uae_s8)(dst)) < 0);
|
|
put_byte(srca, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NOT.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4670_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(dst)) == 0);
|
|
SET_NFLG(((uae_s16)(dst)) < 0);
|
|
put_word(srca, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NOT.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_46b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_u32 dst = ~src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(dst)) == 0);
|
|
SET_NFLG(((uae_s32)(dst)) < 0);
|
|
put_long(srca, dst);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_46f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.W (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_46fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NBCD.B Dn */
|
|
uae_u32 REGPARAM2 op_4800_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (An) */
|
|
uae_u32 REGPARAM2 op_4810_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4818_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B -(An) */
|
|
uae_u32 REGPARAM2 op_4820_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* NBCD.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4828_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4830_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* NBCD.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4838_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* NBCD.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4839_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = - (src & 0xF0);
|
|
uae_u16 newv;
|
|
int cflg, tmp_newv;
|
|
tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo > 9) newv_lo -= 6;
|
|
newv = newv_hi + newv_lo;
|
|
cflg = (newv & 0x1F0) > 0x90;
|
|
if (cflg) newv -= 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(srca, newv);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* PEA.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4870_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u16 old_opcode = opcode;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
if (dsta & 1) {
|
|
regs.ir = old_opcode;
|
|
m68k_incpc(2);
|
|
exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(dsta, srca);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* PEA.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_487b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 old_opcode = opcode;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, 7) - 4;
|
|
m68k_areg(regs, 7) = dsta;
|
|
if (dsta & 1) {
|
|
regs.ir = old_opcode;
|
|
m68k_incpc(2);
|
|
exception3_write_access(old_opcode, dsta, sz_word, srca >> 16, 1);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(dsta, srca);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4890_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_48a0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 0;
|
|
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
|
|
int type = 0;
|
|
while (amask) {
|
|
srca -= 2;
|
|
if (!type || movem_index2[amask] != dstreg) {
|
|
put_word(srca, m68k_areg(regs, movem_index2[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
} else {
|
|
put_word(srca, m68k_areg(regs, movem_index2[amask]) - 2);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
}
|
|
amask = movem_next[amask];
|
|
}
|
|
while (dmask) {
|
|
srca -= 2;
|
|
put_word(srca, m68k_dreg(regs, movem_index2[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_48a8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_48b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_48b8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_48b9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_word(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_word(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_48d0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_48e0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) - 0;
|
|
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
|
|
int type = 0;
|
|
while (amask) {
|
|
srca -= 4;
|
|
if (!type || movem_index2[amask] != dstreg) {
|
|
put_long(srca, m68k_areg(regs, movem_index2[amask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
} else {
|
|
put_long(srca, m68k_areg(regs, movem_index2[amask]) - 4);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
}
|
|
amask = movem_next[amask];
|
|
}
|
|
while (dmask) {
|
|
srca -= 4;
|
|
put_long(srca, m68k_dreg(regs, movem_index2[dmask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_48e8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_48f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_48f8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMLE.L #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_48f9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
while (dmask) {
|
|
put_long(srca, m68k_dreg(regs, movem_index1[dmask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
put_long(srca, m68k_areg(regs, movem_index1[amask]));
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_incpc(8);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* TST.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4a30_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* TST.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4a70_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* TST.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4ab0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* TAS.B Dn */
|
|
uae_u32 REGPARAM2 op_4ac0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (An) */
|
|
uae_u32 REGPARAM2 op_4ad0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4ad8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B -(An) */
|
|
uae_u32 REGPARAM2 op_4ae0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ae8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4af0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* TAS.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4af8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4af9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_u8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4c90_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_4c98_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
get_word(srca);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_4ca8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4cb0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_4cb8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_4cb9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = get_dilong(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(8);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d16,PC) */
|
|
uae_u32 REGPARAM2 op_4cba_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 2;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 4;
|
|
srca += (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.W #<data>.W,(d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4cbb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 dstreg = 3;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 4;
|
|
srca = get_disp_ea_000(tmppc, get_diword(4));
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word(srca);
|
|
count_cycles += 4 * CYCLE_UNIT / 2;
|
|
srca += 2;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(6);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_4cd0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_4cd8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
m68k_areg(regs, dstreg) = srca;
|
|
get_word(srca);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_4ce8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u16 mask = get_diword(2);
|
|
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
while (dmask) {
|
|
m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
dmask = movem_next[dmask];
|
|
}
|
|
while (amask) {
|
|
m68k_areg(regs, movem_index1[amask]) = get_long(srca);
|
|
count_cycles += 8 * CYCLE_UNIT / 2;
|
|
srca += 4;
|
|
amask = movem_next[amask];
|
|
}
|
|
get_word(srca);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVMEL.L #<data>.W,(d8,An,Xn) */
|
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uae_u32 REGPARAM2 op_4cf0_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 dstreg = real_opcode & 7;
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uae_u16 mask = get_diword(2);
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uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
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uaecptr srca;
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srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
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while (dmask) {
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m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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dmask = movem_next[dmask];
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}
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while (amask) {
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m68k_areg(regs, movem_index1[amask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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amask = movem_next[amask];
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}
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get_word(srca);
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m68k_incpc(6);
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return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 4,0 */
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/* MVMEL.L #<data>.W,(xxx).W */
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uae_u32 REGPARAM2 op_4cf8_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u16 mask = get_diword(2);
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uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
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uaecptr srca;
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srca = (uae_s32)(uae_s16)get_diword(4);
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while (dmask) {
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m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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dmask = movem_next[dmask];
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}
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while (amask) {
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m68k_areg(regs, movem_index1[amask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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amask = movem_next[amask];
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}
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get_word(srca);
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m68k_incpc(6);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* MVMEL.L #<data>.W,(xxx).L */
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uae_u32 REGPARAM2 op_4cf9_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u16 mask = get_diword(2);
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uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
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uaecptr srca;
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srca = get_dilong(4);
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while (dmask) {
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m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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dmask = movem_next[dmask];
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}
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while (amask) {
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m68k_areg(regs, movem_index1[amask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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amask = movem_next[amask];
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}
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get_word(srca);
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m68k_incpc(8);
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return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 8 0,0 */
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/* MVMEL.L #<data>.W,(d16,PC) */
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uae_u32 REGPARAM2 op_4cfa_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 dstreg = 2;
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uae_u16 mask = get_diword(2);
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uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
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uaecptr srca;
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srca = m68k_getpc() + 4;
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srca += (uae_s32)(uae_s16)get_diword(4);
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while (dmask) {
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m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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dmask = movem_next[dmask];
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}
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while (amask) {
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m68k_areg(regs, movem_index1[amask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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amask = movem_next[amask];
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}
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get_word(srca);
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m68k_incpc(6);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 0,0 */
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/* MVMEL.L #<data>.W,(d8,PC,Xn) */
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uae_u32 REGPARAM2 op_4cfb_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 dstreg = 3;
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uae_u16 mask = get_diword(2);
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uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
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uaecptr srca;
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uaecptr tmppc = m68k_getpc() + 4;
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srca = get_disp_ea_000(tmppc, get_diword(4));
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while (dmask) {
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m68k_dreg(regs, movem_index1[dmask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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dmask = movem_next[dmask];
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}
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while (amask) {
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m68k_areg(regs, movem_index1[amask]) = get_long(srca);
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count_cycles += 8 * CYCLE_UNIT / 2;
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srca += 4;
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amask = movem_next[amask];
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}
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get_word(srca);
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m68k_incpc(6);
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return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 6 4,0 */
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/* LINK.W An,#<data>.W */
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uae_u32 REGPARAM2 op_4e50_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uae_u32 real_opcode = opcode;
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uae_u32 srcreg = (real_opcode & 7);
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uae_s32 src = m68k_areg(regs, srcreg);
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uaecptr olda;
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olda = m68k_areg(regs, 7) - 4;
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m68k_areg(regs, 7) = olda;
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uae_s16 offs = get_diword(2);
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if (olda & 1) {
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m68k_areg(regs, 7) += 4;
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m68k_areg(regs, srcreg) = olda;
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m68k_incpc(6);
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exception3_write_access(opcode, olda, sz_word, src >> 16, 1);
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return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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put_long(olda, src);
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m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
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m68k_areg(regs, 7) += offs;
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m68k_incpc(4);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 4 0,0 */
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/* STOP.L #<data>.W */
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uae_u32 REGPARAM2 op_4e72_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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if (!regs.s) {
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Exception(8);
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return 0;
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}
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if (!regs.stopped) {
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uae_s16 src = get_diword(2);
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regs.irc = src;
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}
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uae_u16 sr = regs.irc;
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checkint();
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regs.sr = sr;
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MakeFromSR_STOP();
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do_cycles_stop(4);
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m68k_setstopped(1);
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return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* RTE.L */
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uae_u32 REGPARAM2 op_4e73_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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if (!regs.s) {
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Exception(8);
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return 0;
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}
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if (m68k_areg(regs, 7) & 1) {
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exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
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return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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uaecptr oldpc = m68k_getpc();
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uae_u16 oldsr = regs.sr, newsr;
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uae_u32 newpc;
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for (;;) {
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uaecptr a = m68k_areg(regs, 7);
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uae_u16 sr = get_word(a);
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uae_u32 pc = get_long(a + 2);
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uae_u16 format = get_word(a + 2 + 4);
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int frame = format >> 12;
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int offset = 8;
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newsr = sr; newpc = pc;
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if (frame == 0x0) {
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m68k_areg(regs, 7) += offset; break; }
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else if (frame == 0x8) {
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m68k_areg(regs, 7) += offset + 50; break; }
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else {
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SET_NFLG(((uae_s16)format) < 0);
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SET_ZFLG(format == 0);
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SET_VFLG(0);
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Exception_cpu(14);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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regs.sr = newsr;
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oldsr = newsr;
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MakeFromSR_T0();
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}
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regs.sr = newsr;
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MakeFromSR_T0();
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if (newpc & 1) {
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exception3_read_prefetch(opcode, newpc);
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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m68k_setpc_j(newpc);
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#ifdef DEBUGGER
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branch_stack_pop_rte(oldpc);
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#endif
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return (24 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 2 0,0 B */
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/* RTS.L */
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uae_u32 REGPARAM2 op_4e75_4_ff(uae_u32 opcode)
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{
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int count_cycles = 0;
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uaecptr oldpc = m68k_getpc();
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if (m68k_areg(regs, 7) & 1) {
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m68k_incpc(2);
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exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
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return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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m68k_do_rts();
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#ifdef DEBUGGER
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if (debugmem_trace) {
|
|
branch_stack_pop_rts(oldpc);
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}
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#endif
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if (m68k_getpc() & 1) {
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uaecptr faultpc = m68k_getpc();
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m68k_setpc_j(oldpc);
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m68k_incpc(2);
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exception3_read_prefetch_only(opcode, faultpc);
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return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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/* 2 0,0 B */
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/* RTR.L */
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uae_u32 REGPARAM2 op_4e77_4_ff(uae_u32 opcode)
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{
|
|
int count_cycles = 0;
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if (m68k_areg(regs, 7) & 1) {
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m68k_incpc(2);
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exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
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return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
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}
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uaecptr oldpc = m68k_getpc();
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MakeSR();
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uaecptr sra;
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sra = m68k_areg(regs, 7);
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|
uae_s16 sr = get_word(sra);
|
|
m68k_areg(regs, 7) += 2;
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uaecptr pca;
|
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pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
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|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
m68k_setpc_j(pc);
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|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc + 2);
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
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/* JSR.L (d8,An,Xn) */
|
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uae_u32 REGPARAM2 op_4eb0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* JSR.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4ebb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, oldpc >> 16, 1);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* JMP.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4ef0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* JMP.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4efb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* ADDQ.B #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADDQ.W #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADDQ.L #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_50b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_50c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(0)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(0)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (T) */
|
|
uae_u32 REGPARAM2 op_50f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBQ.B #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBQ.W #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_5170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBQ.L #<data>,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_51b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (F) */
|
|
uae_u32 REGPARAM2 op_51c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(1)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(1)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (F) */
|
|
uae_u32 REGPARAM2 op_51f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_52c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(2)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(2)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (HI) */
|
|
uae_u32 REGPARAM2 op_52f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_53c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(3)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(3)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (LS) */
|
|
uae_u32 REGPARAM2 op_53f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_54c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(4)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(4)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (CC) */
|
|
uae_u32 REGPARAM2 op_54f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_55c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(5)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(5)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (CS) */
|
|
uae_u32 REGPARAM2 op_55f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_56c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(6)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(6)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (NE) */
|
|
uae_u32 REGPARAM2 op_56f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_57c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(7)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(7)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (EQ) */
|
|
uae_u32 REGPARAM2 op_57f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_58c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(8)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(8)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (VC) */
|
|
uae_u32 REGPARAM2 op_58f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_59c8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(9)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(9)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (VS) */
|
|
uae_u32 REGPARAM2 op_59f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_5ac8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(10)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(10)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (PL) */
|
|
uae_u32 REGPARAM2 op_5af0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_5bc8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(11)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(11)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (MI) */
|
|
uae_u32 REGPARAM2 op_5bf0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_5cc8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(12)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(12)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (GE) */
|
|
uae_u32 REGPARAM2 op_5cf0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_5dc8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(13)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(13)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (LT) */
|
|
uae_u32 REGPARAM2 op_5df0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_5ec8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(14)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(14)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (GT) */
|
|
uae_u32 REGPARAM2 op_5ef0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_5fc8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(15)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(15)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (d8,An,Xn) (LE) */
|
|
uae_u32 REGPARAM2 op_5ff0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Bcc.W #<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_6000_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(0)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (T) */
|
|
uae_u32 REGPARAM2 op_6001_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(0)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (T) */
|
|
uae_u32 REGPARAM2 op_60ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(0)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_6100_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_s16 src = get_diword(2);
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (s & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BSRQ.B #<data> */
|
|
uae_u32 REGPARAM2 op_6101_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uae_s32 s;
|
|
uae_u32 src = srcreg;
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (s & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* BSR.L #<data>.L */
|
|
uae_u32 REGPARAM2 op_61ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_u32 src = 0xffffffff;
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, oldpc + s, sz_word, oldpc, 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (s & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, oldpc + s);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.W #<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_6200_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(2)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (HI) */
|
|
uae_u32 REGPARAM2 op_6201_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(2)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (HI) */
|
|
uae_u32 REGPARAM2 op_62ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(2)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_6300_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(3)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LS) */
|
|
uae_u32 REGPARAM2 op_6301_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(3)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LS) */
|
|
uae_u32 REGPARAM2 op_63ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(3)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_6400_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(4)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (CC) */
|
|
uae_u32 REGPARAM2 op_6401_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(4)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (CC) */
|
|
uae_u32 REGPARAM2 op_64ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(4)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_6500_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(5)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (CS) */
|
|
uae_u32 REGPARAM2 op_6501_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(5)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (CS) */
|
|
uae_u32 REGPARAM2 op_65ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(5)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_6600_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(6)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (NE) */
|
|
uae_u32 REGPARAM2 op_6601_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(6)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (NE) */
|
|
uae_u32 REGPARAM2 op_66ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(6)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_6700_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(7)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (EQ) */
|
|
uae_u32 REGPARAM2 op_6701_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(7)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (EQ) */
|
|
uae_u32 REGPARAM2 op_67ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(7)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_6800_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(8)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (VC) */
|
|
uae_u32 REGPARAM2 op_6801_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(8)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (VC) */
|
|
uae_u32 REGPARAM2 op_68ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(8)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_6900_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(9)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (VS) */
|
|
uae_u32 REGPARAM2 op_6901_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(9)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (VS) */
|
|
uae_u32 REGPARAM2 op_69ff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(9)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_6a00_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(10)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (PL) */
|
|
uae_u32 REGPARAM2 op_6a01_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(10)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (PL) */
|
|
uae_u32 REGPARAM2 op_6aff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(10)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_6b00_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(11)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (MI) */
|
|
uae_u32 REGPARAM2 op_6b01_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(11)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (MI) */
|
|
uae_u32 REGPARAM2 op_6bff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(11)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_6c00_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(12)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (GE) */
|
|
uae_u32 REGPARAM2 op_6c01_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(12)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (GE) */
|
|
uae_u32 REGPARAM2 op_6cff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(12)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_6d00_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(13)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LT) */
|
|
uae_u32 REGPARAM2 op_6d01_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(13)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LT) */
|
|
uae_u32 REGPARAM2 op_6dff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(13)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_6e00_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(14)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (GT) */
|
|
uae_u32 REGPARAM2 op_6e01_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(14)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (GT) */
|
|
uae_u32 REGPARAM2 op_6eff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(14)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Bcc.W #<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_6f00_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_s16 src = get_diword(2);
|
|
if (cctrue(15)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BccQ.B #<data> (LE) */
|
|
uae_u32 REGPARAM2 op_6f01_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u32 src = srcreg;
|
|
if (cctrue(15)) {
|
|
if (src & 1) {
|
|
uaecptr oldpc = m68k_getpc();
|
|
uae_u16 rb = regs.irc;
|
|
m68k_incpc(((uae_s32)src + 2) & ~1);
|
|
uaecptr newpc = m68k_getpc() + (uae_s32)src + 2;
|
|
m68k_incpc(2);
|
|
regs.read_buffer = rb;
|
|
exception3_read_prefetch(opcode, newpc);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc((uae_s32)src + 2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* Bcc.L #<data>.L (LE) */
|
|
uae_u32 REGPARAM2 op_6fff_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (cctrue(15)) {
|
|
exception3_read_prefetch(opcode, m68k_getpc() + 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_8030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_803b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_8070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_807b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DIVU.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_80c0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_80d0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_80d8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_80e0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVU.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_80e8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVU.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DIVU.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_80f8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVU.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_80f9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(6);
|
|
Exception_cpu(5);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* DIVU.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_80fa_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVU.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DIVU.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_80fc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(0, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
|
|
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
|
|
count_cycles += (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) * CYCLE_UNIT / 2;
|
|
if (newv > 0xffff) {
|
|
setdivuflags((uae_u32)dst, (uae_u16)src);
|
|
} else {
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SBCD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8100_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int bcd = 0;
|
|
newv = tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
|
|
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
|
|
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SBCD.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_8108_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int bcd = 0;
|
|
newv = tmp_newv = newv_hi + newv_lo;
|
|
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
|
|
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
|
|
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_8130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_8170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_81b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DIVS.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_81c0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_81d0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_81d8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_81e0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(2);
|
|
Exception_cpu(5);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DIVS.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_81e8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVS.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_81f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DIVS.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_81f8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVS.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_81f9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(6);
|
|
Exception_cpu(5);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* DIVS.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_81fa_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* DIVS.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_81fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* DIVS.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_81fc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
if (src == 0) {
|
|
divbyzero_special(1, dst);
|
|
m68k_incpc(4);
|
|
Exception_cpu(5);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
int extra = 0;
|
|
count_cycles += (getDivs68kCycles((uae_s32)dst, (uae_s16)src, &extra)) * CYCLE_UNIT / 2;
|
|
if (dst == 0x80000000 && src == -1) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
|
|
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
|
|
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
|
|
setdivsflags((uae_s32)dst, (uae_s16)src);
|
|
} else {
|
|
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
}
|
|
}
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_9030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_903b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_9070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_907b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_90b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_90bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_90f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_90fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_9130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_9170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_91b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_91f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUBA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_91fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst - src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMP.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMP.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b03b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMP.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMP.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b07b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMP.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b0b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMP.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_b0bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMPA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_b0f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMPA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_b0fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* EOR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_b130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* EOR.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_b170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* EOR.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_b1b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMPA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_b1f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CMPA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_b1fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs != flgo) && (flgn != flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
SET_NFLG(flgn != 0);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c03b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c07b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MULU.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c0c0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_c0d0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c0d8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c0e0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULU.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c0e8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULU.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MULU.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c0f8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULU.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c0f9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULU.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c0fa_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULU.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MULU.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_c0fc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMulu68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ABCD.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c100_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int cflg;
|
|
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
|
|
cflg = (newv & 0x3F0) > 0x90;
|
|
if (cflg) newv += 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ABCD.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_c108_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
|
|
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
|
|
uae_u16 newv, tmp_newv;
|
|
int cflg;
|
|
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
|
|
cflg = (newv & 0x3F0) > 0x90;
|
|
if (cflg) newv += 0x60;
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
SET_VFLG((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_c130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
put_byte(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_c170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(src)) == 0);
|
|
SET_NFLG(((uae_s16)(src)) < 0);
|
|
put_word(dsta, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_c1b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
put_long(dsta, src);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MULS.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c1c0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W (An),Dn */
|
|
uae_u32 REGPARAM2 op_c1d0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c1d8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c1e0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MULS.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c1e8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULS.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c1f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MULS.W (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c1f8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULS.W (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c1f9_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MULS.W (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c1fa_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MULS.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c1fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MULS.W #<data>.W,Dn */
|
|
uae_u32 REGPARAM2 op_c1fc_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
count_cycles += (getMuls68kCycles(src)) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.B (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.B (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d03b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.W (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.W (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d07b_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d0b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d0bb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADDA.W (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_d0f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADDA.W (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_d0fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_d130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_ZFLG(((uae_s8)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.W Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_d170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s16 dst = get_word(dsta);
|
|
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_ZFLG(((uae_s16)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.L Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_d1b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s32 dst = get_long(dsta);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADDA.L (d8,An,Xn),An */
|
|
uae_u32 REGPARAM2 op_d1f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADDA.L (d8,PC,Xn),An */
|
|
uae_u32 REGPARAM2 op_d1fb_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_areg(regs, dstreg);
|
|
uae_u32 newv = dst + src;
|
|
m68k_areg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ASRQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e000_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80 & val) >> 7;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
val = 0xff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e008_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG((cnt == 8) & (val >> 7));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e010_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (7 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e018_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 hival;
|
|
cnt &= 7;
|
|
hival = val << (8 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xff;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e020_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80 & val) >> 7;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
val = 0xff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e028_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG((cnt == 8) & (val >> 7));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e030_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 36) cnt -= 36;
|
|
if (cnt >= 18) cnt -= 18;
|
|
if (cnt >= 9) cnt -= 9;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (7 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROR.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e038_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 hival;
|
|
cnt &= 7;
|
|
hival = val << (8 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xff;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e040_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x8000 & val) >> 15;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
val = 0xffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e048_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG((cnt == 16) & (val >> 15));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e050_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (15 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e058_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 hival;
|
|
cnt &= 15;
|
|
hival = val << (16 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffff;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e060_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x8000 & val) >> 15;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
val = 0xffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e068_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG((cnt == 16) & (val >> 15));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e070_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 34) cnt -= 34;
|
|
if (cnt >= 17) cnt -= 17;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (15 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROR.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e078_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 hival;
|
|
cnt &= 15;
|
|
hival = val << (16 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffff;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e080_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80000000 & val) >> 31;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
val = 0xffffffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSRQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e088_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG((cnt == 32) & (val >> 31));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXRQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e090_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (31 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RORQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e098_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 hival;
|
|
cnt &= 31;
|
|
hival = val << (32 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffffffff;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0a0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
uae_u32 sign = (0x80000000 & val) >> 31;
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
val = 0xffffffff & (uae_u32)(0 - sign);
|
|
SET_CFLG(sign);
|
|
COPY_CARRY();
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0a8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG((cnt == 32) & (val >> 31));
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val >>= cnt - 1;
|
|
SET_CFLG(val & 1);
|
|
COPY_CARRY();
|
|
val >>= 1;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 33) cnt -= 33;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 hival = (val << 1) | GET_XFLG();
|
|
hival <<= (31 - cnt);
|
|
val >>= cnt;
|
|
carry = val & 1;
|
|
val >>= 1;
|
|
val |= hival;
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e0b8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 hival;
|
|
cnt &= 31;
|
|
hival = val << (32 - cnt);
|
|
val >>= cnt;
|
|
val |= hival;
|
|
val &= 0xffffffff;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASRW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e0f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 cflg = val & 1;
|
|
val = (val >> 1) | sign;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(cflg);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ASLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e100_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e108_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e110_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (7 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLQ.B #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e118_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 loval;
|
|
cnt &= 7;
|
|
loval = val >> (8 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e120_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e128_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 8) {
|
|
SET_CFLG(cnt == 8 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80) >> 7);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xff;
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e130_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 36) cnt -= 36;
|
|
if (cnt >= 18) cnt -= 18;
|
|
if (cnt >= 9) cnt -= 9;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (7 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROL.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e138_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s8 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u8)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 loval;
|
|
cnt &= 7;
|
|
loval = val >> (8 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s8)(val)) == 0);
|
|
SET_NFLG(((uae_s8)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e140_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e148_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e150_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (15 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLQ.W #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e158_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 loval;
|
|
cnt &= 15;
|
|
loval = val >> (16 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e160_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e168_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 16) {
|
|
SET_CFLG(cnt == 16 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x8000) >> 15);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffff;
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e170_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 34) cnt -= 34;
|
|
if (cnt >= 17) cnt -= 17;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (15 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROL.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e178_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s16 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = (uae_u16)data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 loval;
|
|
cnt &= 15;
|
|
loval = val >> (16 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e180_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e188_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e190_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (31 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROLQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_e198_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 cnt = srcreg;
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
{
|
|
uae_u32 loval;
|
|
cnt &= 31;
|
|
loval = val >> (32 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffffffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1a0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_VFLG(val != 0);
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
|
|
SET_VFLG((val & mask) != mask && (val & mask) != 0);
|
|
val <<= cnt - 1;
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* LSL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1a8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 32) {
|
|
SET_CFLG(cnt == 32 ? val & 1 : 0);
|
|
COPY_CARRY();
|
|
val = 0;
|
|
} else if (cnt > 0) {
|
|
val <<= (cnt - 1);
|
|
SET_CFLG((val & 0x80000000) >> 31);
|
|
COPY_CARRY();
|
|
val <<= 1;
|
|
val &= 0xffffffff;
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROXL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1b0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt >= 33) cnt -= 33;
|
|
if (cnt > 0) {
|
|
cnt--;
|
|
{
|
|
uae_u32 carry;
|
|
uae_u32 loval = val >> (31 - cnt);
|
|
carry = loval & 1;
|
|
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
|
|
SET_XFLG(carry);
|
|
val &= 0xffffffff;
|
|
}
|
|
}
|
|
SET_CFLG(GET_XFLG());
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ROL.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_e1b8_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 cnt = m68k_dreg(regs, srcreg);
|
|
uae_s32 data = m68k_dreg(regs, dstreg);
|
|
uae_u32 val = data;
|
|
CLEAR_CZNV();
|
|
int ccnt = cnt & 63;
|
|
cnt &= 63;
|
|
if (cnt > 0) {
|
|
uae_u32 loval;
|
|
cnt &= 31;
|
|
loval = val >> (32 - cnt);
|
|
val <<= cnt;
|
|
val |= loval;
|
|
val &= 0xffffffff;
|
|
SET_CFLG(val & 1);
|
|
}
|
|
SET_ZFLG(((uae_s32)(val)) == 0);
|
|
SET_NFLG(((uae_s32)(val)) < 0);
|
|
count_cycles += (2 * ccnt) * CYCLE_UNIT / 2;
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ASLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e1f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 sign = 0x8000 & val;
|
|
uae_u32 sign2;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
sign2 = 0x8000 & val;
|
|
SET_CFLG(sign != 0);
|
|
COPY_CARRY();
|
|
SET_VFLG(GET_VFLG() | (sign2 != sign));
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* LSRW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e2f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u32 val = (uae_u16)data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* LSLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e3f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ROXRW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e4f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (GET_XFLG()) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ROXLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e5f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (GET_XFLG()) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
COPY_CARRY();
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* RORW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e6f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 1;
|
|
val >>= 1;
|
|
if (carry) val |= 0x8000;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry);
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ROLW.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_e7f0_4_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr dataa;
|
|
dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 data = get_word(dataa);
|
|
uae_u16 val = data;
|
|
uae_u32 carry = val & 0x8000;
|
|
val <<= 1;
|
|
if (carry) val |= 1;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(val)) == 0);
|
|
SET_NFLG(((uae_s16)(val)) < 0);
|
|
SET_CFLG(carry >> 15);
|
|
put_word(dataa, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_003c_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
int t1 = regs.t1;
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr |= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_007c_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
int t1 = regs.t1;
|
|
uae_s16 src = get_diword(2);
|
|
regs.sr |= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0080_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVPMR.W (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_0108_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_u16 val = (get_byte(mempa) & 0xff) << 8;
|
|
val |= (get_byte(mempa + 2) & 0xff);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVPMR.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_0148_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_u32 val = (get_byte(mempa) & 0xff) << 24;
|
|
val |= (get_byte(mempa + 2) & 0xff) << 16;
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;
|
|
val |= (get_byte(mempa + 4) & 0xff) << 8;
|
|
val |= (get_byte(mempa + 6) & 0xff);
|
|
m68k_dreg(regs, dstreg) = (val);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((4 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVPRM.W Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_0188_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
put_byte(mempa, src >> 8);
|
|
put_byte(mempa + 2, src);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B Dn,(An) */
|
|
uae_u32 REGPARAM2 op_0190_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,(An)+ */
|
|
uae_u32 REGPARAM2 op_0198_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,-(An) */
|
|
uae_u32 REGPARAM2 op_01a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* BCLR.B Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_01a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B Dn,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_01b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(2));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* BCLR.B Dn,(xxx).W */
|
|
uae_u32 REGPARAM2 op_01b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B Dn,(xxx).L */
|
|
uae_u32 REGPARAM2 op_01b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(2);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVPRM.L Dn,(d16,An) */
|
|
uae_u32 REGPARAM2 op_01c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
put_byte(mempa, src >> 24);
|
|
put_byte(mempa + 2, src >> 16);
|
|
put_byte(mempa + 4, src >> 8);
|
|
put_byte(mempa + 6, src);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((4 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_023c_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
int t1 = regs.t1;
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
src |= 0xff00;
|
|
regs.sr &= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ANDSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_027c_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
int t1 = regs.t1;
|
|
uae_s16 src = get_diword(2);
|
|
regs.sr &= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0280_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0480_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0680_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(An) */
|
|
uae_u32 REGPARAM2 op_0890_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(An)+ */
|
|
uae_u32 REGPARAM2 op_0898_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg);
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,-(An) */
|
|
uae_u32 REGPARAM2 op_08a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(d16,An) */
|
|
uae_u32 REGPARAM2 op_08a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_08b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_diword(4));
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 4,0 */
|
|
|
|
/* BCLR.B #<data>.W,(xxx).W */
|
|
uae_u32 REGPARAM2 op_08b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = (uae_s32)(uae_s16)get_diword(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BCLR.B #<data>.W,(xxx).L */
|
|
uae_u32 REGPARAM2 op_08b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
uaecptr dsta;
|
|
dsta = get_dilong(4);
|
|
uae_s8 dst = get_byte(dsta);
|
|
src &= 7;
|
|
SET_ZFLG(1 ^ ((dst >> src) & 1));
|
|
dst &= ~(1 << src);
|
|
put_byte(dsta, dst);
|
|
m68k_incpc(8);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 8 0,0 */
|
|
|
|
/* EORSR.B #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a3c_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
MakeSR();
|
|
int t1 = regs.t1;
|
|
uae_s16 src = get_diword(2);
|
|
src &= 0xFF;
|
|
regs.sr ^= src;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EORSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_0a7c_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
MakeSR();
|
|
int t1 = regs.t1;
|
|
uae_s16 src = get_diword(2);
|
|
regs.sr ^= src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* EOR.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_0a80_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVSR2.W Dn */
|
|
uae_u32 REGPARAM2 op_40c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
MakeSR();
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W (An) */
|
|
uae_u32 REGPARAM2 op_40d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W (An)+ */
|
|
uae_u32 REGPARAM2 op_40d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W -(An) */
|
|
uae_u32 REGPARAM2 op_40e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
m68k_areg(regs, srcreg) = srca;
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVSR2.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_40e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVSR2.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_40f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MVSR2.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_40f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MVSR2.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_40f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
MakeSR();
|
|
get_word(srca);
|
|
put_word(srca, regs.sr);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* LEA.L (xxx).L,An */
|
|
uae_u32 REGPARAM2 op_41f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
m68k_areg(regs, dstreg) = (srca);
|
|
m68k_incpc(6);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CLR.B Dn */
|
|
uae_u32 REGPARAM2 op_4200_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B (An) */
|
|
uae_u32 REGPARAM2 op_4210_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4218_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B -(An) */
|
|
uae_u32 REGPARAM2 op_4220_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4228_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4230_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CLR.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4238_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4239_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(0)) == 0);
|
|
SET_NFLG(((uae_s8)(0)) < 0);
|
|
put_byte(srca, 0);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CLR.W Dn */
|
|
uae_u32 REGPARAM2 op_4240_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W (An) */
|
|
uae_u32 REGPARAM2 op_4250_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W (An)+ */
|
|
uae_u32 REGPARAM2 op_4258_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W -(An) */
|
|
uae_u32 REGPARAM2 op_4260_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_4268_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4270_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CLR.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_4278_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_4279_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s16)(0)) == 0);
|
|
SET_NFLG(((uae_s16)(0)) < 0);
|
|
put_word(srca, 0);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* CLR.L Dn */
|
|
uae_u32 REGPARAM2 op_4280_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
m68k_dreg(regs, srcreg) = (0);
|
|
m68k_incpc(2);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L (An) */
|
|
uae_u32 REGPARAM2 op_4290_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L (An)+ */
|
|
uae_u32 REGPARAM2 op_4298_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(2);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L -(An) */
|
|
uae_u32 REGPARAM2 op_42a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(2);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* CLR.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_42a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_42b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(4);
|
|
return (26 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* CLR.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_42b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(4);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* CLR.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_42b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(0)) == 0);
|
|
SET_NFLG(((uae_s32)(0)) < 0);
|
|
put_long(srca, 0);
|
|
m68k_incpc(6);
|
|
return (28 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.B Dn */
|
|
uae_u32 REGPARAM2 op_44c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B (An) */
|
|
uae_u32 REGPARAM2 op_44d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B (An)+ */
|
|
uae_u32 REGPARAM2 op_44d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B -(An) */
|
|
uae_u32 REGPARAM2 op_44e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_44e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_44f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_44f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_44f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.B (d16,PC) */
|
|
uae_u32 REGPARAM2 op_44fa_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.B (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_44fb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.B #<data>.B */
|
|
uae_u32 REGPARAM2 op_44fc_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s16 src = get_diword(2);
|
|
int t1 = regs.t1;
|
|
MakeSR();
|
|
regs.sr &= 0xFF00;
|
|
regs.sr |= src & 0xFF;
|
|
MakeFromSR();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W Dn */
|
|
uae_u32 REGPARAM2 op_46c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W (An) */
|
|
uae_u32 REGPARAM2 op_46d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W (An)+ */
|
|
uae_u32 REGPARAM2 op_46d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) += 2;
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W -(An) */
|
|
uae_u32 REGPARAM2 op_46e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MV2SR.W (d16,An) */
|
|
uae_u32 REGPARAM2 op_46e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_46f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.W (xxx).W */
|
|
uae_u32 REGPARAM2 op_46f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W (xxx).L */
|
|
uae_u32 REGPARAM2 op_46f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(6);
|
|
return (24 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MV2SR.W (d16,PC) */
|
|
uae_u32 REGPARAM2 op_46fa_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* MV2SR.W (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_46fb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s16 src = get_word(srca);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* MV2SR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_46fc_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s16 src = get_diword(2);
|
|
int t1 = regs.t1;
|
|
regs.sr = src;
|
|
MakeFromSR_T0();
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B Dn */
|
|
uae_u32 REGPARAM2 op_4ac0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (An) */
|
|
uae_u32 REGPARAM2 op_4ad0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (An)+ */
|
|
uae_u32 REGPARAM2 op_4ad8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B -(An) */
|
|
uae_u32 REGPARAM2 op_4ae0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* TAS.B (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ae8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4af0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* TAS.B (xxx).W */
|
|
uae_u32 REGPARAM2 op_4af8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* TAS.B (xxx).L */
|
|
uae_u32 REGPARAM2 op_4af9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s8)(src)) == 0);
|
|
SET_NFLG(((uae_s8)(src)) < 0);
|
|
uae_u8 old_src = src;
|
|
src |= 0x80;
|
|
put_byte(srca, src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* MVR2USP.L An */
|
|
uae_u32 REGPARAM2 op_4e60_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
regs.usp = src;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* MVUSP2R.L An */
|
|
uae_u32 REGPARAM2 op_4e68_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
m68k_areg(regs, srcreg) = (regs.usp);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* STOP.L #<data>.W */
|
|
uae_u32 REGPARAM2 op_4e72_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
if (!regs.stopped) {
|
|
uae_s16 src = get_diword(2);
|
|
regs.irc = src;
|
|
}
|
|
uae_u16 sr = regs.irc;
|
|
checkint();
|
|
regs.sr = sr;
|
|
MakeFromSR_STOP();
|
|
do_cycles_stop(4);
|
|
m68k_setstopped(1);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
|
|
/* RTE.L */
|
|
uae_u32 REGPARAM2 op_4e73_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (!regs.s) {
|
|
Exception(8);
|
|
return 0;
|
|
}
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr a = m68k_areg(regs, 7);
|
|
uae_u16 sr = get_word(a);
|
|
m68k_areg(regs, 7) += 6;
|
|
uae_u32 pc = get_word(a + 2) << 16;
|
|
pc |= get_word(a + 2 + 2);
|
|
uae_u16 oldt1 = regs.t1;
|
|
regs.sr = sr;
|
|
MakeFromSR();
|
|
if (pc & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_access(opcode | 0x20000, pc, 1, 2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(pc);
|
|
#ifdef DEBUGGER
|
|
branch_stack_pop_rte(oldpc);
|
|
#endif
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* RTS.L */
|
|
uae_u32 REGPARAM2 op_4e75_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_rts();
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_pop_rts(oldpc);
|
|
}
|
|
#endif
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* TRAPV.L */
|
|
uae_u32 REGPARAM2 op_4e76_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
m68k_incpc(2);
|
|
if (GET_VFLG()) {
|
|
Exception_cpu(7);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* RTR.L */
|
|
uae_u32 REGPARAM2 op_4e77_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_access(opcode, m68k_areg(regs, 7), 1, 1);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
uaecptr oldpc = m68k_getpc();
|
|
MakeSR();
|
|
uaecptr sra;
|
|
sra = m68k_areg(regs, 7);
|
|
uae_s16 sr = get_word(sra);
|
|
m68k_areg(regs, 7) += 2;
|
|
uaecptr pca;
|
|
pca = m68k_areg(regs, 7);
|
|
uae_s32 pc = get_long(pca);
|
|
m68k_areg(regs, 7) += 4;
|
|
regs.sr &= 0xFF00; sr &= 0xFF;
|
|
regs.sr |= sr;
|
|
MakeFromSR();
|
|
m68k_setpc_j(pc);
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr faultpc = m68k_getpc();
|
|
m68k_setpc_j(oldpc + 2);
|
|
exception3_read_prefetch_only(opcode, faultpc);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* JSR.L (An) */
|
|
uae_u32 REGPARAM2 op_4e90_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (srca & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* JSR.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ea8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4eb0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* JSR.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4eb8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(4);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4eb9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 6;
|
|
if (srca & 1) {
|
|
m68k_incpc(6);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(6);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* JSR.L (d16,PC) */
|
|
uae_u32 REGPARAM2 op_4eba_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (6 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JSR.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4ebb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
m68k_areg(regs, 7) -= 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_setpc_j(oldpc);
|
|
m68k_incpc(4);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
put_long(m68k_areg(regs, 7), nextpc);
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* JMP.L (An) */
|
|
uae_u32 REGPARAM2 op_4ed0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
if (srca & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* JMP.L (d16,An) */
|
|
uae_u32 REGPARAM2 op_4ee8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JMP.L (d8,An,Xn) */
|
|
uae_u32 REGPARAM2 op_4ef0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* JMP.L (xxx).W */
|
|
uae_u32 REGPARAM2 op_4ef8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JMP.L (xxx).L */
|
|
uae_u32 REGPARAM2 op_4ef9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
if (srca & 1) {
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 B */
|
|
|
|
/* JMP.L (d16,PC) */
|
|
uae_u32 REGPARAM2 op_4efa_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
if (srca & 1) {
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* JMP.L (d8,PC,Xn) */
|
|
uae_u32 REGPARAM2 op_4efb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
if (srca & 1) {
|
|
count_cycles += 6 * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
exception3_read_prefetch_only(opcode, srca);
|
|
return (0 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_setpc_j(srca);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 B */
|
|
|
|
/* ADDQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5080_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B Dn (T) */
|
|
uae_u32 REGPARAM2 op_50c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (T) */
|
|
uae_u32 REGPARAM2 op_50c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(0)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(0)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (T) */
|
|
uae_u32 REGPARAM2 op_50d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (T) */
|
|
uae_u32 REGPARAM2 op_50d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (T) */
|
|
uae_u32 REGPARAM2 op_50e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (T) */
|
|
uae_u32 REGPARAM2 op_50e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (T) */
|
|
uae_u32 REGPARAM2 op_50f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (T) */
|
|
uae_u32 REGPARAM2 op_50f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (T) */
|
|
uae_u32 REGPARAM2 op_50f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(0) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBQ.L #<data>,Dn */
|
|
uae_u32 REGPARAM2 op_5180_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_u32 src = srcreg;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B Dn (F) */
|
|
uae_u32 REGPARAM2 op_51c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (F) */
|
|
uae_u32 REGPARAM2 op_51c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(1)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(1)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (F) */
|
|
uae_u32 REGPARAM2 op_51d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (F) */
|
|
uae_u32 REGPARAM2 op_51d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (F) */
|
|
uae_u32 REGPARAM2 op_51e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (F) */
|
|
uae_u32 REGPARAM2 op_51e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (F) */
|
|
uae_u32 REGPARAM2 op_51f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (F) */
|
|
uae_u32 REGPARAM2 op_51f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (F) */
|
|
uae_u32 REGPARAM2 op_51f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(1) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (HI) */
|
|
uae_u32 REGPARAM2 op_52c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (HI) */
|
|
uae_u32 REGPARAM2 op_52c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(2)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(2)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (HI) */
|
|
uae_u32 REGPARAM2 op_52d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (HI) */
|
|
uae_u32 REGPARAM2 op_52d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (HI) */
|
|
uae_u32 REGPARAM2 op_52e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (HI) */
|
|
uae_u32 REGPARAM2 op_52e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (HI) */
|
|
uae_u32 REGPARAM2 op_52f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (HI) */
|
|
uae_u32 REGPARAM2 op_52f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (HI) */
|
|
uae_u32 REGPARAM2 op_52f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(2) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (LS) */
|
|
uae_u32 REGPARAM2 op_53c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LS) */
|
|
uae_u32 REGPARAM2 op_53c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(3)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(3)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (LS) */
|
|
uae_u32 REGPARAM2 op_53d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (LS) */
|
|
uae_u32 REGPARAM2 op_53d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (LS) */
|
|
uae_u32 REGPARAM2 op_53e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (LS) */
|
|
uae_u32 REGPARAM2 op_53e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (LS) */
|
|
uae_u32 REGPARAM2 op_53f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (LS) */
|
|
uae_u32 REGPARAM2 op_53f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (LS) */
|
|
uae_u32 REGPARAM2 op_53f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(3) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (CC) */
|
|
uae_u32 REGPARAM2 op_54c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CC) */
|
|
uae_u32 REGPARAM2 op_54c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(4)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(4)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (CC) */
|
|
uae_u32 REGPARAM2 op_54d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (CC) */
|
|
uae_u32 REGPARAM2 op_54d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (CC) */
|
|
uae_u32 REGPARAM2 op_54e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (CC) */
|
|
uae_u32 REGPARAM2 op_54e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (CC) */
|
|
uae_u32 REGPARAM2 op_54f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (CC) */
|
|
uae_u32 REGPARAM2 op_54f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (CC) */
|
|
uae_u32 REGPARAM2 op_54f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(4) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (CS) */
|
|
uae_u32 REGPARAM2 op_55c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (CS) */
|
|
uae_u32 REGPARAM2 op_55c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(5)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(5)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (CS) */
|
|
uae_u32 REGPARAM2 op_55d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (CS) */
|
|
uae_u32 REGPARAM2 op_55d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (CS) */
|
|
uae_u32 REGPARAM2 op_55e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (CS) */
|
|
uae_u32 REGPARAM2 op_55e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (CS) */
|
|
uae_u32 REGPARAM2 op_55f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (CS) */
|
|
uae_u32 REGPARAM2 op_55f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (CS) */
|
|
uae_u32 REGPARAM2 op_55f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(5) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (NE) */
|
|
uae_u32 REGPARAM2 op_56c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (NE) */
|
|
uae_u32 REGPARAM2 op_56c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(6)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(6)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (NE) */
|
|
uae_u32 REGPARAM2 op_56d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (NE) */
|
|
uae_u32 REGPARAM2 op_56d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (NE) */
|
|
uae_u32 REGPARAM2 op_56e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (NE) */
|
|
uae_u32 REGPARAM2 op_56e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (NE) */
|
|
uae_u32 REGPARAM2 op_56f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (NE) */
|
|
uae_u32 REGPARAM2 op_56f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (NE) */
|
|
uae_u32 REGPARAM2 op_56f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(6) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (EQ) */
|
|
uae_u32 REGPARAM2 op_57c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (EQ) */
|
|
uae_u32 REGPARAM2 op_57c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(7)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(7)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (EQ) */
|
|
uae_u32 REGPARAM2 op_57d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (EQ) */
|
|
uae_u32 REGPARAM2 op_57d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (EQ) */
|
|
uae_u32 REGPARAM2 op_57e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (EQ) */
|
|
uae_u32 REGPARAM2 op_57e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (EQ) */
|
|
uae_u32 REGPARAM2 op_57f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (EQ) */
|
|
uae_u32 REGPARAM2 op_57f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (EQ) */
|
|
uae_u32 REGPARAM2 op_57f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(7) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (VC) */
|
|
uae_u32 REGPARAM2 op_58c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VC) */
|
|
uae_u32 REGPARAM2 op_58c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(8)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(8)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (VC) */
|
|
uae_u32 REGPARAM2 op_58d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (VC) */
|
|
uae_u32 REGPARAM2 op_58d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (VC) */
|
|
uae_u32 REGPARAM2 op_58e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (VC) */
|
|
uae_u32 REGPARAM2 op_58e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (VC) */
|
|
uae_u32 REGPARAM2 op_58f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (VC) */
|
|
uae_u32 REGPARAM2 op_58f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (VC) */
|
|
uae_u32 REGPARAM2 op_58f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(8) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (VS) */
|
|
uae_u32 REGPARAM2 op_59c0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (VS) */
|
|
uae_u32 REGPARAM2 op_59c8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(9)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(9)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (VS) */
|
|
uae_u32 REGPARAM2 op_59d0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (VS) */
|
|
uae_u32 REGPARAM2 op_59d8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (VS) */
|
|
uae_u32 REGPARAM2 op_59e0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (VS) */
|
|
uae_u32 REGPARAM2 op_59e8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (VS) */
|
|
uae_u32 REGPARAM2 op_59f0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (VS) */
|
|
uae_u32 REGPARAM2 op_59f8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (VS) */
|
|
uae_u32 REGPARAM2 op_59f9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(9) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (PL) */
|
|
uae_u32 REGPARAM2 op_5ac0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (PL) */
|
|
uae_u32 REGPARAM2 op_5ac8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(10)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(10)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (PL) */
|
|
uae_u32 REGPARAM2 op_5ad0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (PL) */
|
|
uae_u32 REGPARAM2 op_5ad8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (PL) */
|
|
uae_u32 REGPARAM2 op_5ae0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (PL) */
|
|
uae_u32 REGPARAM2 op_5ae8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (PL) */
|
|
uae_u32 REGPARAM2 op_5af0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (PL) */
|
|
uae_u32 REGPARAM2 op_5af8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (PL) */
|
|
uae_u32 REGPARAM2 op_5af9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(10) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (MI) */
|
|
uae_u32 REGPARAM2 op_5bc0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (MI) */
|
|
uae_u32 REGPARAM2 op_5bc8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(11)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(11)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (MI) */
|
|
uae_u32 REGPARAM2 op_5bd0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (MI) */
|
|
uae_u32 REGPARAM2 op_5bd8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (MI) */
|
|
uae_u32 REGPARAM2 op_5be0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (MI) */
|
|
uae_u32 REGPARAM2 op_5be8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (MI) */
|
|
uae_u32 REGPARAM2 op_5bf0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (MI) */
|
|
uae_u32 REGPARAM2 op_5bf8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (MI) */
|
|
uae_u32 REGPARAM2 op_5bf9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(11) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (GE) */
|
|
uae_u32 REGPARAM2 op_5cc0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GE) */
|
|
uae_u32 REGPARAM2 op_5cc8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(12)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(12)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (GE) */
|
|
uae_u32 REGPARAM2 op_5cd0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (GE) */
|
|
uae_u32 REGPARAM2 op_5cd8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (GE) */
|
|
uae_u32 REGPARAM2 op_5ce0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (GE) */
|
|
uae_u32 REGPARAM2 op_5ce8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (GE) */
|
|
uae_u32 REGPARAM2 op_5cf0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (GE) */
|
|
uae_u32 REGPARAM2 op_5cf8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (GE) */
|
|
uae_u32 REGPARAM2 op_5cf9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(12) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (LT) */
|
|
uae_u32 REGPARAM2 op_5dc0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LT) */
|
|
uae_u32 REGPARAM2 op_5dc8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(13)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(13)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (LT) */
|
|
uae_u32 REGPARAM2 op_5dd0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (LT) */
|
|
uae_u32 REGPARAM2 op_5dd8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (LT) */
|
|
uae_u32 REGPARAM2 op_5de0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (LT) */
|
|
uae_u32 REGPARAM2 op_5de8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (LT) */
|
|
uae_u32 REGPARAM2 op_5df0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (LT) */
|
|
uae_u32 REGPARAM2 op_5df8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (LT) */
|
|
uae_u32 REGPARAM2 op_5df9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(13) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (GT) */
|
|
uae_u32 REGPARAM2 op_5ec0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (GT) */
|
|
uae_u32 REGPARAM2 op_5ec8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(14)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(14)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (GT) */
|
|
uae_u32 REGPARAM2 op_5ed0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (GT) */
|
|
uae_u32 REGPARAM2 op_5ed8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (GT) */
|
|
uae_u32 REGPARAM2 op_5ee0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (GT) */
|
|
uae_u32 REGPARAM2 op_5ee8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (GT) */
|
|
uae_u32 REGPARAM2 op_5ef0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (GT) */
|
|
uae_u32 REGPARAM2 op_5ef8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (GT) */
|
|
uae_u32 REGPARAM2 op_5ef9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(14) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* Scc.B Dn (LE) */
|
|
uae_u32 REGPARAM2 op_5fc0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
if (!val) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
}
|
|
opcode |= 0x20000;
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
|
|
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* DBcc.W Dn,#<data>.W (LE) */
|
|
uae_u32 REGPARAM2 op_5fc8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
int pcadjust = -2;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 offs = get_diword(2);
|
|
uaecptr oldpc = m68k_getpc();
|
|
if (!cctrue(15)) {
|
|
m68k_incpc((uae_s32)offs + 2);
|
|
if (offs & 1) {
|
|
exception3_read_prefetch(opcode, m68k_getpc());
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
if (src) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
count_cycles += 2 * CYCLE_UNIT / 2;
|
|
pcadjust = 0;
|
|
}
|
|
m68k_setpc_j(oldpc + 4);
|
|
if (!cctrue(15)) {
|
|
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
|
|
}
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* Scc.B (An) (LE) */
|
|
uae_u32 REGPARAM2 op_5fd0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (An)+ (LE) */
|
|
uae_u32 REGPARAM2 op_5fd8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (12 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B -(An) (LE) */
|
|
uae_u32 REGPARAM2 op_5fe0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* Scc.B (d16,An) (LE) */
|
|
uae_u32 REGPARAM2 op_5fe8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (d8,An,Xn) (LE) */
|
|
uae_u32 REGPARAM2 op_5ff0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* Scc.B (xxx).W (LE) */
|
|
uae_u32 REGPARAM2 op_5ff8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(4);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* Scc.B (xxx).L (LE) */
|
|
uae_u32 REGPARAM2 op_5ff9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s8 src = get_byte(srca);
|
|
int val = cctrue(15) ? 0xff : 0x00;
|
|
put_byte(srca, val);
|
|
m68k_incpc(6);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* BSR.W #<data>.W */
|
|
uae_u32 REGPARAM2 op_6100_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_s16 src = get_diword(2);
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 4;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_areg(regs, 7) -= 4;
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr addr = m68k_getpc();
|
|
m68k_incpc(-2);
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 B */
|
|
|
|
/* BSRQ.B #<data> */
|
|
uae_u32 REGPARAM2 op_6101_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
|
|
uae_s32 s;
|
|
uae_u32 src = srcreg;
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_areg(regs, 7) -= 4;
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr addr = m68k_getpc();
|
|
m68k_incpc(-2);
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* BSR.L #<data>.L */
|
|
uae_u32 REGPARAM2 op_61ff_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_s32 s;
|
|
uae_u32 src = 0xffffffff;
|
|
s = (uae_s32)src + 2;
|
|
uaecptr oldpc = m68k_getpc();
|
|
uaecptr nextpc = oldpc + 2;
|
|
if (m68k_areg(regs, 7) & 1) {
|
|
m68k_areg(regs, 7) -= 4;
|
|
m68k_incpc(2);
|
|
exception3_write_access(opcode, m68k_areg(regs, 7), sz_word, oldpc, 1);
|
|
return (2 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
m68k_do_bsr(nextpc, s);
|
|
if (m68k_getpc() & 1) {
|
|
uaecptr addr = m68k_getpc();
|
|
m68k_incpc(-2);
|
|
exception3_read_prefetch(opcode, addr);
|
|
return (10 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
#ifdef DEBUGGER
|
|
if (debugmem_trace) {
|
|
branch_stack_push(oldpc, nextpc);
|
|
}
|
|
#endif
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 B */
|
|
|
|
/* OR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_8080_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_8090_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_8098_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_80a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* OR.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_80a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_80b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_80b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* OR.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_80ba_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* OR.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_80bb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* OR.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_80bc_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src |= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9080_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L An,Dn */
|
|
uae_u32 REGPARAM2 op_9088_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_9090_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_9098_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_90a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUB.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_90a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_90b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_90b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_90b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUB.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_90ba_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* SUB.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_90bb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* SUB.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_90bc_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
|
|
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* SUBX.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9100_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_9108_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9140_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.W -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_9148_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_9180_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int oldz = GET_ZFLG();
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* SUBX.L -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_9188_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
|
|
int oldz = GET_ZFLG();
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* EOR.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_b180_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = ((real_opcode >> 9) & 7);
|
|
uae_u32 dstreg = real_opcode & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src ^= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_c080_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_c090_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_c098_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_c0a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* AND.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_c0a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_c0b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_c0b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* AND.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_c0ba_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* AND.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_c0bb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* AND.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_c0bc_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
src &= dst;
|
|
CLEAR_CZNV();
|
|
SET_ZFLG(((uae_s32)(src)) == 0);
|
|
SET_NFLG(((uae_s32)(src)) < 0);
|
|
m68k_dreg(regs, dstreg) = (src);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d080_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L An,Dn */
|
|
uae_u32 REGPARAM2 op_d088_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_areg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L (An),Dn */
|
|
uae_u32 REGPARAM2 op_d090_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L (An)+,Dn */
|
|
uae_u32 REGPARAM2 op_d098_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg);
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) += 4;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (14 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L -(An),Dn */
|
|
uae_u32 REGPARAM2 op_d0a0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADD.L (d16,An),Dn */
|
|
uae_u32 REGPARAM2 op_d0a8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L (d8,An,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d0b0_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.L (xxx).W,Dn */
|
|
uae_u32 REGPARAM2 op_d0b8_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L (xxx).L,Dn */
|
|
uae_u32 REGPARAM2 op_d0b9_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = get_dilong(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (22 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADD.L (d16,PC),Dn */
|
|
uae_u32 REGPARAM2 op_d0ba_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_getpc() + 2;
|
|
srca += (uae_s32)(uae_s16)get_diword(2);
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 0,0 */
|
|
|
|
/* ADD.L (d8,PC,Xn),Dn */
|
|
uae_u32 REGPARAM2 op_d0bb_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
uaecptr tmppc = m68k_getpc() + 2;
|
|
srca = get_disp_ea_000(tmppc, get_diword(2));
|
|
uae_s32 src = get_long(srca);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(4);
|
|
return (20 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 4 4,0 */
|
|
|
|
/* ADD.L #<data>.L,Dn */
|
|
uae_u32 REGPARAM2 op_d0bc_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src;
|
|
src = get_dilong(2);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_ZFLG(((uae_s32)(newv)) == 0);
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
|
|
COPY_CARRY();
|
|
SET_NFLG(flgn != 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(6);
|
|
return (16 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 6 0,0 */
|
|
|
|
/* ADDX.B Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d100_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s8 src = m68k_dreg(regs, srcreg);
|
|
uae_s8 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.B -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_d108_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
|
|
uae_s8 src = get_byte(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
|
|
uae_s8 dst = get_byte(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s8)(src)) < 0;
|
|
int flgo = ((uae_s8)(dst)) < 0;
|
|
int flgn = ((uae_s8)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
|
|
SET_NFLG(((uae_s8)(newv)) < 0);
|
|
put_byte(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.W Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d140_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s16 src = m68k_dreg(regs, srcreg);
|
|
uae_s16 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
|
|
m68k_incpc(2);
|
|
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.W -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_d148_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 2;
|
|
uae_s16 src = get_word(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 2;
|
|
uae_s16 dst = get_word(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int flgs = ((uae_s16)(src)) < 0;
|
|
int flgo = ((uae_s16)(dst)) < 0;
|
|
int flgn = ((uae_s16)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
|
|
SET_NFLG(((uae_s16)(newv)) < 0);
|
|
put_word(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (18 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.L Dn,Dn */
|
|
uae_u32 REGPARAM2 op_d180_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uae_s32 src = m68k_dreg(regs, srcreg);
|
|
uae_s32 dst = m68k_dreg(regs, dstreg);
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int oldz = GET_ZFLG();
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
m68k_dreg(regs, dstreg) = (newv);
|
|
m68k_incpc(2);
|
|
return (8 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|
|
/* ADDX.L -(An),-(An) */
|
|
uae_u32 REGPARAM2 op_d188_5_ff(uae_u32 opcode)
|
|
{
|
|
int count_cycles = 0;
|
|
uae_u32 real_opcode = opcode;
|
|
uae_u32 srcreg = (real_opcode & 7);
|
|
uae_u32 dstreg = (real_opcode >> 9) & 7;
|
|
uaecptr srca;
|
|
srca = m68k_areg(regs, srcreg) - 4;
|
|
uae_s32 src = get_long(srca);
|
|
m68k_areg(regs, srcreg) = srca;
|
|
uaecptr dsta;
|
|
dsta = m68k_areg(regs, dstreg) - 4;
|
|
uae_s32 dst = get_long(dsta);
|
|
m68k_areg(regs, dstreg) = dsta;
|
|
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
|
|
int oldz = GET_ZFLG();
|
|
int flgs = ((uae_s32)(src)) < 0;
|
|
int flgo = ((uae_s32)(dst)) < 0;
|
|
int flgn = ((uae_s32)(newv)) < 0;
|
|
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
|
|
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
|
|
COPY_CARRY();
|
|
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
|
|
SET_NFLG(((uae_s32)(newv)) < 0);
|
|
put_long(dsta, newv);
|
|
m68k_incpc(2);
|
|
return (30 * CYCLE_UNIT / 2 + count_cycles) | (((3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
|
|
}
|
|
/* 2 0,0 */
|
|
|