mirror of
https://github.com/LIV2/WinUAE.git
synced 2025-12-06 00:12:52 +00:00
859 lines
24 KiB
C
859 lines
24 KiB
C
/*
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* UAE - The Un*x Amiga Emulator
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*
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* MC68000 emulation
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*
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* Copyright 1995 Bernd Schmidt
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*/
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#ifndef UAE_NEWCPU_H
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#define UAE_NEWCPU_H
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#include "uae/types.h"
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#include "readcpu.h"
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#include "machdep/m68k.h"
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#include "events.h"
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#include <softfloat/softfloat.h>
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#ifndef SET_CFLG
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#define SET_CFLG(x) (CFLG() = (x))
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#define SET_NFLG(x) (NFLG() = (x))
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#define SET_VFLG(x) (VFLG() = (x))
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#define SET_ZFLG(x) (ZFLG() = (x))
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#define SET_XFLG(x) (XFLG() = (x))
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#define GET_CFLG() CFLG()
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#define GET_NFLG() NFLG()
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#define GET_VFLG() VFLG()
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#define GET_ZFLG() ZFLG()
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#define GET_XFLG() XFLG()
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#define CLEAR_CZNV() do { \
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SET_CFLG (0); \
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SET_ZFLG (0); \
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SET_NFLG (0); \
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SET_VFLG (0); \
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} while (0)
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#define COPY_CARRY() (SET_XFLG (GET_CFLG ()))
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#endif
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extern const int areg_byteinc[];
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extern const int imm8_table[];
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extern int movem_index1[256];
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extern int movem_index2[256];
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extern int movem_next[256];
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#ifdef FPUEMU
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extern int fpp_movem_index1[256];
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extern int fpp_movem_index2[256];
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extern int fpp_movem_next[256];
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#endif
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extern int hardware_bus_error;
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typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
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typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
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struct cputbl {
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cpuop_func *handler_ff;
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cpuop_func *handler_nf;
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uae_u16 opcode;
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uae_s8 length;
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uae_s8 disp020[2];
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uae_s8 branch;
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uae_u16 specific;
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};
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#ifdef JIT
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#define MIN_JIT_CACHE 128
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#define MAX_JIT_CACHE 16384
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typedef uae_u32 REGPARAM3 compop_func (uae_u32) REGPARAM;
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#define COMP_OPCODE_ISJUMP 0x0001
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#define COMP_OPCODE_LONG_OPCODE 0x0002
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#define COMP_OPCODE_CMOV 0x0004
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#define COMP_OPCODE_ISADDX 0x0008
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#define COMP_OPCODE_ISCJUMP 0x0010
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#define COMP_OPCODE_USES_FPU 0x0020
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struct comptbl {
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compop_func *handler;
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uae_u32 opcode;
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int specific;
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};
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#endif
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extern cpuop_func *loop_mode_table[];
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extern uae_u32 REGPARAM3 op_illg (uae_u32) REGPARAM;
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extern void REGPARAM3 op_unimpl (uae_u32) REGPARAM;
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typedef uae_u8 flagtype;
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#ifdef FPUEMU
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#ifdef USE_LONG_DOUBLE
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typedef long double fptype;
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#else
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typedef double fptype;
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#endif
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#endif
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#define MAX68020CYCLES 4
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#define CPU_PIPELINE_MAX 4
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#define CPU000_MEM_CYCLE 4
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#define CPU000_CLOCK_MULT 2
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#define CPU020_MEM_CYCLE 3
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#define CPU020_CLOCK_MULT 4
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#define CACHELINES020 64
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struct cache020
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{
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uae_u32 data;
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uae_u32 tag;
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bool valid;
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};
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#define CACHELINES030 16
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struct cache030
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{
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uae_u32 data[4];
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bool valid[4];
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uae_u32 tag;
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uae_u8 fc;
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};
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#define CACHESETS040 64
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#define CACHESETS060 128
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#define CACHELINES040 4
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struct cache040
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{
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uae_u32 data[CACHELINES040][4];
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bool dirty[CACHELINES040][4];
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bool gdirty[CACHELINES040];
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bool valid[CACHELINES040];
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uae_u32 tag[CACHELINES040];
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};
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struct mmufixup
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{
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int reg;
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uae_u32 value;
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};
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extern struct mmufixup mmufixup[2];
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#ifdef MSVC_LONG_DOUBLE
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typedef struct {
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uae_u64 m;
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uae_u16 e;
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uae_u16 dummy;
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} fprawtype;
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#endif
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typedef struct
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{
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floatx80 fpx;
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#ifdef MSVC_LONG_DOUBLE
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union {
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fptype fp;
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fprawtype rfp;
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};
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#else
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fptype fp;
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#endif
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} fpdata;
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struct regstruct
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{
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uae_u32 regs[16];
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uae_u32 pc;
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uae_u8 *pc_p;
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uae_u8 *pc_oldp;
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uae_u16 opcode;
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uae_u32 instruction_pc;
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uae_u32 instruction_pc_user_exception;
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uae_u32 trace_pc;
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uae_u16 irc, ir, ird;
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volatile uae_atomic spcflags;
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uae_u32 last_prefetch;
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uae_u32 chipset_latch_rw;
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uae_u32 chipset_latch_read;
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uae_u32 chipset_latch_write;
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uae_u16 db, write_buffer, read_buffer;
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int loop_mode;
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int instruction_cnt;
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uaecptr usp, isp, msp;
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uae_u16 sr;
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flagtype t1;
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flagtype t0;
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flagtype s;
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flagtype m;
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flagtype stopped;
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int halted;
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int exception;
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int intmask;
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int ipl, ipl_pin;
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uae_u32 vbr, sfc, dfc;
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#ifdef FPUEMU
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fpdata fp[8];
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#ifdef JIT
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fpdata fp_result;
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#endif
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uae_u32 fpcr, fpsr, fpiar;
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uae_u32 fpu_state;
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uae_u32 fpu_exp_state;
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uae_u16 fp_opword;
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uaecptr fp_ea;
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bool fp_ea_set;
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uae_u32 fp_exp_pend, fp_unimp_pend;
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bool fpu_exp_pre;
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bool fp_unimp_ins;
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bool fp_exception;
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bool fp_branch;
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#endif
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#ifndef CPUEMU_68000_ONLY
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uae_u32 cacr, caar;
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uae_u32 itt0, itt1, dtt0, dtt1;
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uae_u32 tcr, mmusr, urp, srp, buscr;
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uae_u32 mmu_fslw;
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uae_u32 mmu_fault_addr, mmu_effective_addr;
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uae_u16 mmu_ssw;
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uae_u32 wb2_address;
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uae_u32 wb3_data;
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uae_u8 wb3_status, wb2_status;
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int mmu_enabled;
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int mmu_page_size;
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#endif
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uae_u32 pcr;
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uae_u32 address_space_mask;
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uae_u16 prefetch020[CPU_PIPELINE_MAX];
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uae_u8 prefetch020_valid[CPU_PIPELINE_MAX];
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uae_u32 prefetch020addr;
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uae_u32 cacheholdingdata020;
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uae_u32 cacheholdingaddr020;
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uae_u8 cacheholdingdata_valid;
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int pipeline_pos;
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int pipeline_r8[2];
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int pipeline_stop;
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uae_u8 fc030;
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uae_u32 prefetch040[CPU_PIPELINE_MAX];
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int ce020endcycle;
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int ce020startcycle;
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int ce020prefetchendcycle;
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int ce020extracycles;
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bool ce020memcycle_data;
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int ce020_tail;
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frame_time_t ce020_tail_cycles;
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int memory_waitstate_cycles;
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};
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extern struct regstruct regs;
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#define MAX_CPUTRACESIZE 128
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struct cputracememory
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{
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uae_u32 addr;
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uae_u32 data;
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int mode;
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};
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struct cputracestruct
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{
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uae_u32 regs[16];
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uae_u32 usp, isp, pc;
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uae_u16 ir, irc, ird, sr, opcode;
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int intmask, stopped, state;
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uae_u32 msp, vbr;
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uae_u32 cacr, caar;
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uae_u16 prefetch020[CPU_PIPELINE_MAX];
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uae_u8 prefetch020_valid[CPU_PIPELINE_MAX];
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uae_u32 prefetch020addr;
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uae_u32 cacheholdingdata020;
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uae_u32 cacheholdingaddr020;
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struct cache020 caches020[CACHELINES020];
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int pipeline_pos;
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int pipeline_r8[2];
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int pipeline_stop;
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uae_u16 read_buffer, write_buffer;
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uae_u32 startcycles;
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int needendcycles;
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int memoryoffset;
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int cyclecounter, cyclecounter_pre, cyclecounter_post;
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int readcounter, writecounter;
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struct cputracememory ctm[MAX_CPUTRACESIZE];
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};
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STATIC_INLINE uae_u32 munge24 (uae_u32 x)
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{
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return x & regs.address_space_mask;
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}
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extern int mmu_enabled, mmu_triggered;
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extern int cpu_cycles;
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extern int cpucycleunit;
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extern int m68k_pc_indirect;
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extern void safe_interrupt_set(int, int, bool);
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STATIC_INLINE void set_special_exter(uae_u32 x)
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{
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atomic_or(®s.spcflags, x);
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}
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STATIC_INLINE void set_special (uae_u32 x)
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{
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atomic_or(®s.spcflags, x);
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cycles_do_special ();
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}
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STATIC_INLINE void unset_special (uae_u32 x)
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{
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atomic_and(®s.spcflags, ~x);
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}
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#define m68k_dreg(r,num) ((r).regs[(num)])
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#define m68k_areg(r,num) (((r).regs + 8)[(num)])
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// JIT only
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#ifdef HAVE_GET_WORD_UNSWAPPED
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#define GET_OPCODE (do_get_mem_word_unswapped((uae_u16*)(pc + pc_offset)));
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#else
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#define GET_OPCODE (do_get_mem_word((uae_u16*)(pc + pc_offset)));
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#endif
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extern uae_u32(*x_prefetch)(int);
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extern uae_u32(*x_get_byte)(uaecptr addr);
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extern uae_u32(*x_get_word)(uaecptr addr);
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extern uae_u32(*x_get_long)(uaecptr addr);
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extern void(*x_put_byte)(uaecptr addr, uae_u32 v);
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extern void(*x_put_word)(uaecptr addr, uae_u32 v);
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extern void(*x_put_long)(uaecptr addr, uae_u32 v);
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extern uae_u32(*x_next_iword)(void);
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extern uae_u32(*x_next_ilong)(void);
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extern uae_u32(*x_get_ilong)(int);
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extern uae_u32(*x_get_iword)(int);
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extern uae_u32(*x_get_ibyte)(int);
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extern uae_u32(*x_cp_get_byte)(uaecptr addr);
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extern uae_u32(*x_cp_get_word)(uaecptr addr);
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extern uae_u32(*x_cp_get_long)(uaecptr addr);
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extern void(*x_cp_put_byte)(uaecptr addr, uae_u32 v);
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extern void(*x_cp_put_word)(uaecptr addr, uae_u32 v);
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extern void(*x_cp_put_long)(uaecptr addr, uae_u32 v);
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extern uae_u32(*x_cp_next_iword)(void);
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extern uae_u32(*x_cp_next_ilong)(void);
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void mem_access_delay_long_write_ce020 (uaecptr addr, uae_u32 v);
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void mem_access_delay_word_write_ce020 (uaecptr addr, uae_u32 v);
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void mem_access_delay_byte_write_ce020 (uaecptr addr, uae_u32 v);
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uae_u32 mem_access_delay_byte_read_ce020 (uaecptr addr);
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uae_u32 mem_access_delay_word_read_ce020 (uaecptr addr);
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uae_u32 mem_access_delay_long_read_ce020 (uaecptr addr);
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uae_u32 mem_access_delay_longi_read_ce020 (uaecptr addr);
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uae_u32 mem_access_delay_wordi_read_ce020 (uaecptr addr);
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void mem_access_delay_long_write_c040 (uaecptr addr, uae_u32 v);
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void mem_access_delay_word_write_c040 (uaecptr addr, uae_u32 v);
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void mem_access_delay_byte_write_c040 (uaecptr addr, uae_u32 v);
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uae_u32 mem_access_delay_byte_read_c040 (uaecptr addr);
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uae_u32 mem_access_delay_word_read_c040 (uaecptr addr);
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uae_u32 mem_access_delay_long_read_c040 (uaecptr addr);
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uae_u32 mem_access_delay_longi_read_c040 (uaecptr addr);
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extern uae_u32(REGPARAM3 *x_cp_get_disp_ea_020)(uae_u32 base, int idx) REGPARAM;
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extern bool debugmem_trace;
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extern void branch_stack_push(uaecptr, uaecptr);
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extern void branch_stack_pop_rte(uaecptr);
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extern void branch_stack_pop_rts(uaecptr);
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/* direct (regs.pc_p) access */
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STATIC_INLINE void m68k_setpc(uaecptr newpc)
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{
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regs.pc_p = regs.pc_oldp = get_real_address(newpc);
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regs.instruction_pc = regs.pc = newpc;
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}
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STATIC_INLINE void m68k_setpc_j(uaecptr newpc)
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{
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regs.pc_p = regs.pc_oldp = get_real_address(newpc);
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regs.pc = newpc;
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}
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STATIC_INLINE uaecptr m68k_getpc(void)
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{
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return (uaecptr)(regs.pc + ((uae_u8*)regs.pc_p - (uae_u8*)regs.pc_oldp));
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}
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#define M68K_GETPC m68k_getpc()
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STATIC_INLINE uaecptr m68k_getpc_p(uae_u8 *p)
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{
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return (uaecptr)(regs.pc + ((uae_u8*)p - (uae_u8*)regs.pc_oldp));
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}
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STATIC_INLINE void m68k_incpc(int o)
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{
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regs.pc_p += o;
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}
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STATIC_INLINE uae_u32 get_dibyte(int o)
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{
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return do_get_mem_byte((uae_u8 *)((regs).pc_p + (o) + 1));
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}
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STATIC_INLINE uae_u32 get_diword(int o)
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{
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return do_get_mem_word((uae_u16 *)((regs).pc_p + (o)));
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}
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STATIC_INLINE uae_u32 get_dilong(int o)
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{
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return do_get_mem_long((uae_u32 *)((regs).pc_p + (o)));
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}
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STATIC_INLINE uae_u32 next_diword(void)
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{
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uae_u32 r = do_get_mem_word((uae_u16 *)((regs).pc_p));
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m68k_incpc(2);
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return r;
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}
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STATIC_INLINE uae_u32 next_dilong(void)
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{
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uae_u32 r = do_get_mem_long((uae_u32 *)((regs).pc_p));
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m68k_incpc(4);
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return r;
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}
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STATIC_INLINE void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
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{
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m68k_areg(regs, 7) -= 4;
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put_long(m68k_areg(regs, 7), oldpc);
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m68k_incpc(offset);
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}
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STATIC_INLINE void m68k_do_rts(void)
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{
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uae_u32 newpc = get_long(m68k_areg(regs, 7));
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m68k_setpc(newpc);
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m68k_areg(regs, 7) += 4;
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}
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/* indirect (regs.pc) access */
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STATIC_INLINE void m68k_setpci(uaecptr newpc)
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{
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regs.instruction_pc = regs.pc = newpc;
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}
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STATIC_INLINE void m68k_setpci_j(uaecptr newpc)
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{
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regs.pc = newpc;
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}
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STATIC_INLINE uaecptr m68k_getpci(void)
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{
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return regs.pc;
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}
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STATIC_INLINE void m68k_incpci(int o)
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{
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regs.pc += o;
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}
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STATIC_INLINE uae_u32 get_iibyte(int o)
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{
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return get_wordi(m68k_getpci() + (o)) & 0xff;
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}
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STATIC_INLINE uae_u32 get_iiword(int o)
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{
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return get_wordi(m68k_getpci() + (o));
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}
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STATIC_INLINE uae_u32 get_iilong(int o)
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{
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return get_longi(m68k_getpci () + (o));
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}
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STATIC_INLINE uae_u32 next_iibyte (void)
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{
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uae_u32 r = get_iibyte (0);
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m68k_incpci (2);
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return r;
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}
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STATIC_INLINE uae_u32 next_iiword (void)
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{
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uae_u32 r = get_iiword (0);
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m68k_incpci (2);
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return r;
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}
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STATIC_INLINE uae_u32 next_iiwordi (void)
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{
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uae_u32 r = get_wordi(m68k_getpci());
|
|
m68k_incpci (2);
|
|
return r;
|
|
}
|
|
STATIC_INLINE uae_u32 next_iilong (void)
|
|
{
|
|
uae_u32 r = get_iilong(0);
|
|
m68k_incpci (4);
|
|
return r;
|
|
}
|
|
STATIC_INLINE uae_u32 next_iilongi (void)
|
|
{
|
|
uae_u32 r = get_longi (m68k_getpci ());
|
|
m68k_incpci (4);
|
|
return r;
|
|
}
|
|
|
|
STATIC_INLINE void m68k_do_bsri(uaecptr oldpc, uae_s32 offset)
|
|
{
|
|
m68k_areg(regs, 7) -= 4;
|
|
x_put_long(m68k_areg(regs, 7), oldpc);
|
|
m68k_incpci(offset);
|
|
}
|
|
STATIC_INLINE void m68k_do_rtsi(void)
|
|
{
|
|
uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
|
|
m68k_setpci(newpc);
|
|
m68k_areg(regs, 7) += 4;
|
|
}
|
|
|
|
/* indirect jit friendly versions */
|
|
|
|
STATIC_INLINE uae_u32 get_iibyte_jit(int o)
|
|
{
|
|
return get_wordi(m68k_getpc() + (o)) & 0xff;
|
|
}
|
|
STATIC_INLINE uae_u32 get_iiword_jit(int o)
|
|
{
|
|
return get_wordi(m68k_getpc() + (o));
|
|
}
|
|
STATIC_INLINE uae_u32 get_iilong_jit(int o)
|
|
{
|
|
return get_longi(m68k_getpc() + (o));
|
|
}
|
|
STATIC_INLINE uae_u32 next_iiword_jit(void)
|
|
{
|
|
uae_u32 r = get_wordi(m68k_getpc());
|
|
m68k_incpc(2);
|
|
return r;
|
|
}
|
|
STATIC_INLINE uae_u32 next_iilong_jit(void)
|
|
{
|
|
uae_u32 r = get_longi(m68k_getpc());
|
|
m68k_incpc(4);
|
|
return r;
|
|
}
|
|
STATIC_INLINE void m68k_do_bsri_jit(uaecptr oldpc, uae_s32 offset)
|
|
{
|
|
m68k_areg(regs, 7) -= 4;
|
|
x_put_long(m68k_areg(regs, 7), oldpc);
|
|
m68k_incpc(offset);
|
|
}
|
|
STATIC_INLINE void m68k_do_rtsi_jit(void)
|
|
{
|
|
uae_u32 newpc = x_get_long(m68k_areg(regs, 7));
|
|
m68k_setpc(newpc);
|
|
m68k_areg(regs, 7) += 4;
|
|
}
|
|
|
|
/* common access */
|
|
|
|
STATIC_INLINE void m68k_incpc_normal(int o)
|
|
{
|
|
if (m68k_pc_indirect > 0)
|
|
m68k_incpci(o);
|
|
else
|
|
m68k_incpc(o);
|
|
}
|
|
|
|
STATIC_INLINE void m68k_setpc_normal(uaecptr pc)
|
|
{
|
|
if (m68k_pc_indirect > 0) {
|
|
regs.pc_p = regs.pc_oldp = 0;
|
|
m68k_setpci(pc);
|
|
} else {
|
|
m68k_setpc(pc);
|
|
}
|
|
}
|
|
|
|
extern void cpu_invalidate_cache(uaecptr, int);
|
|
|
|
extern bool(*is_super_access)(bool);
|
|
|
|
extern uae_u32(*read_data_030_bget)(uaecptr);
|
|
extern uae_u32(*read_data_030_wget)(uaecptr);
|
|
extern uae_u32(*read_data_030_lget)(uaecptr);
|
|
extern void(*write_data_030_bput)(uaecptr,uae_u32);
|
|
extern void(*write_data_030_wput)(uaecptr,uae_u32);
|
|
extern void(*write_data_030_lput)(uaecptr,uae_u32);
|
|
|
|
extern uae_u32(*read_data_030_fc_bget)(uaecptr, uae_u32);
|
|
extern uae_u32(*read_data_030_fc_wget)(uaecptr, uae_u32);
|
|
extern uae_u32(*read_data_030_fc_lget)(uaecptr, uae_u32);
|
|
extern void(*write_data_030_fc_bput)(uaecptr, uae_u32, uae_u32);
|
|
extern void(*write_data_030_fc_wput)(uaecptr, uae_u32, uae_u32);
|
|
extern void(*write_data_030_fc_lput)(uaecptr, uae_u32, uae_u32);
|
|
|
|
extern void write_dcache030_bput(uaecptr, uae_u32, uae_u32);
|
|
extern void write_dcache030_wput(uaecptr, uae_u32, uae_u32);
|
|
extern void write_dcache030_lput(uaecptr, uae_u32, uae_u32);
|
|
extern void write_dcache030_retry(uaecptr addr, uae_u32 v, uae_u32 fc, int size, int flags);
|
|
extern uae_u32 read_dcache030_bget(uaecptr, uae_u32);
|
|
extern uae_u32 read_dcache030_wget(uaecptr, uae_u32);
|
|
extern uae_u32 read_dcache030_lget(uaecptr, uae_u32);
|
|
extern uae_u32 read_dcache030_retry(uaecptr addr, uae_u32 fc, int size, int flags);
|
|
|
|
extern void write_dcache030_mmu_bput(uaecptr, uae_u32);
|
|
extern void write_dcache030_mmu_wput(uaecptr, uae_u32);
|
|
extern void write_dcache030_mmu_lput(uaecptr, uae_u32);
|
|
extern uae_u32 read_dcache030_mmu_bget(uaecptr);
|
|
extern uae_u32 read_dcache030_mmu_wget(uaecptr);
|
|
extern uae_u32 read_dcache030_mmu_lget(uaecptr);
|
|
extern void write_dcache030_lrmw_mmu(uaecptr, uae_u32, uae_u32);
|
|
extern void write_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, uae_u32, int);
|
|
extern uae_u32 read_dcache030_lrmw_mmu(uaecptr, uae_u32);
|
|
extern uae_u32 read_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, int);
|
|
|
|
extern void check_t0_trace(void);
|
|
extern uae_u32 get_word_icache030(uaecptr addr);
|
|
extern uae_u32 get_long_icache030(uaecptr addr);
|
|
|
|
uae_u32 fill_icache040(uae_u32 addr);
|
|
extern void put_long_cache_040(uaecptr, uae_u32);
|
|
extern void put_word_cache_040(uaecptr, uae_u32);
|
|
extern void put_byte_cache_040(uaecptr, uae_u32);
|
|
extern uae_u32 get_ilong_cache_040(int);
|
|
extern uae_u32 get_iword_cache_040(int);
|
|
extern uae_u32 get_long_cache_040(uaecptr);
|
|
extern uae_u32 get_word_cache_040(uaecptr);
|
|
extern uae_u32 get_byte_cache_040(uaecptr);
|
|
extern uae_u32 next_iword_cache040(void);
|
|
extern uae_u32 next_ilong_cache040(void);
|
|
extern uae_u32 get_word_icache040(uaecptr addr);
|
|
extern uae_u32 get_long_icache040(uaecptr addr);
|
|
|
|
extern uae_u32 sfc_nommu_get_byte(uaecptr);
|
|
extern uae_u32 sfc_nommu_get_word(uaecptr);
|
|
extern uae_u32 sfc_nommu_get_long(uaecptr);
|
|
extern void dfc_nommu_put_byte(uaecptr, uae_u32);
|
|
extern void dfc_nommu_put_word(uaecptr, uae_u32);
|
|
extern void dfc_nommu_put_long(uaecptr, uae_u32);
|
|
|
|
extern void (*x_do_cycles)(unsigned long);
|
|
extern void (*x_do_cycles_pre)(unsigned long);
|
|
extern void (*x_do_cycles_post)(unsigned long, uae_u32);
|
|
|
|
extern uae_u32 REGPARAM3 x_get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
|
|
extern uae_u32 REGPARAM3 x_get_disp_ea_ce020 (uae_u32 base, int idx) REGPARAM;
|
|
extern uae_u32 REGPARAM3 x_get_disp_ea_ce030 (uae_u32 base, int idx) REGPARAM;
|
|
extern uae_u32 REGPARAM3 x_get_disp_ea_040(uae_u32 base, int idx) REGPARAM;
|
|
extern uae_u32 REGPARAM3 x_get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
|
|
extern void REGPARAM3 x_put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
|
|
|
|
extern void m68k_setstopped (void);
|
|
extern void m68k_resumestopped (void);
|
|
extern void m68k_cancel_idle(void);
|
|
|
|
extern uae_u32 REGPARAM3 get_disp_ea_020 (uae_u32 base, int idx) REGPARAM;
|
|
extern uae_u32 REGPARAM3 get_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
|
|
extern void REGPARAM3 put_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;
|
|
|
|
extern void m68k_disasm_ea (uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, uaecptr lastpc);
|
|
extern void m68k_disasm (uaecptr addr, uaecptr *nextpc, uaecptr lastpc, int cnt);
|
|
extern uae_u32 m68k_disasm_2 (TCHAR *buf, int bufsize, uaecptr addr, uaecptr *nextpc, int cnt, uae_u32 *seaddr, uae_u32 *deaddr, uaecptr lastpc, int safemode);
|
|
extern void sm68k_disasm (TCHAR*, TCHAR*, uaecptr addr, uaecptr *nextpc, uaecptr lastpc);
|
|
extern int m68k_asm(TCHAR *buf, uae_u16 *out, uaecptr pc);
|
|
extern uaecptr ShowEA(void *f, uaecptr pc, uae_u16 opcode, int reg, amodes mode, wordsizes size, TCHAR *buf, uae_u32 *eaddr, int *actualea, int safemode);
|
|
extern int get_cpu_model (void);
|
|
|
|
extern void set_cpu_caches (bool flush);
|
|
extern void flush_cpu_caches(bool flush);
|
|
extern void flush_cpu_caches_040(uae_u16 opcode);
|
|
extern void REGPARAM3 MakeSR (void) REGPARAM;
|
|
extern void REGPARAM3 MakeFromSR(void) REGPARAM;
|
|
extern void REGPARAM3 MakeFromSR_T0(void) REGPARAM;
|
|
extern void REGPARAM3 MakeFromSR_intmask(uae_u16 oldsr, uae_u16 newsr) REGPARAM;
|
|
extern void REGPARAM3 Exception (int) REGPARAM;
|
|
extern void REGPARAM3 Exception_cpu(int) REGPARAM;
|
|
extern void REGPARAM3 Exception_cpu_oldpc(int, uaecptr) REGPARAM;
|
|
extern void REGPARAM3 ExceptionL (int, uaecptr) REGPARAM;
|
|
extern void NMI (void);
|
|
extern void NMI_delayed (void);
|
|
extern void prepare_interrupt (uae_u32);
|
|
extern void doint (void);
|
|
extern void dump_counts (void);
|
|
extern int m68k_move2c (int, uae_u32 *);
|
|
extern int m68k_movec2 (int, uae_u32 *);
|
|
extern int m68k_divl (uae_u32, uae_u32, uae_u16, uaecptr);
|
|
extern int m68k_mull (uae_u32, uae_u32, uae_u16);
|
|
extern void init_m68k (void);
|
|
extern void m68k_go (int);
|
|
extern void m68k_dumpstate(uaecptr *, uaecptr);
|
|
extern void m68k_dumpcache (bool);
|
|
extern int getMulu68kCycles(uae_u16 src);
|
|
extern int getMuls68kCycles(uae_u16 src);
|
|
extern int getDivu68kCycles (uae_u32 dividend, uae_u16 divisor);
|
|
extern int getDivs68kCycles (uae_s32 dividend, uae_s16 divisor);
|
|
extern void divbyzero_special(bool issigned, uae_s32 dst);
|
|
extern void setdivuflags(uae_u32 dividend, uae_u16 divisor);
|
|
extern void setdivsflags(uae_s32 dividend, uae_s16 divisor);
|
|
extern void setchkundefinedflags(uae_s32 src, uae_s32 dst, int size);
|
|
extern void setchk2undefinedflags(uae_s32 lower, uae_s32 upper, uae_s32 val, int size);
|
|
extern void protect_roms (bool);
|
|
extern void unprotect_maprom (void);
|
|
extern bool is_hardreset(void);
|
|
extern bool is_keyboardreset(void);
|
|
extern void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr);
|
|
extern void Exception_build_stack_frame(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr, int format);
|
|
extern void Exception_build_68000_address_error_stack_frame(uae_u16 mode, uae_u16 opcode, uaecptr fault_addr, uaecptr pc);
|
|
extern uae_u32 exception_pc(int nr);
|
|
extern void cpu_restore_fixup(void);
|
|
extern bool privileged_copro_instruction(uae_u16 opcode);
|
|
extern bool generates_group1_exception(uae_u16 opcode);
|
|
|
|
void ccr_68000_long_move_ae_LZN(uae_s32 src);
|
|
void ccr_68000_long_move_ae_LN(uae_s32 src);
|
|
void ccr_68000_long_move_ae_HNZ(uae_s32 src);
|
|
void ccr_68000_long_move_ae_normal(uae_s32 src);
|
|
void ccr_68000_word_move_ae_normal(uae_s16 src);
|
|
void dreg_68000_long_replace_low(int reg, uae_u16 v);
|
|
void areg_68000_long_replace_low(int reg, uae_u16 v);
|
|
|
|
extern void mmu_op (uae_u32, uae_u32);
|
|
extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
|
|
|
|
extern void fpuop_arithmetic(uae_u32, uae_u16);
|
|
extern void fpuop_dbcc(uae_u32, uae_u16);
|
|
extern void fpuop_scc(uae_u32, uae_u16);
|
|
extern void fpuop_trapcc(uae_u32, uaecptr, uae_u16);
|
|
extern void fpuop_bcc(uae_u32, uaecptr, uae_u32);
|
|
extern void fpuop_save(uae_u32);
|
|
extern void fpuop_restore(uae_u32);
|
|
extern uae_u32 fpp_get_fpsr (void);
|
|
extern void fpu_reset (void);
|
|
extern void fpux_save (int*);
|
|
extern void fpux_restore (int*);
|
|
extern bool fpu_get_constant(fpdata *fp, int cr);
|
|
extern int fpp_cond(int condition);
|
|
|
|
extern void exception3_read(uae_u32 opcode, uaecptr addr, int size, int fc);
|
|
extern void exception3_write(uae_u32 opcode, uaecptr addr, int size, uae_u32 val, int fc);
|
|
extern void exception3_read_access(uae_u32 opcode, uaecptr addr, int size, int fc);
|
|
extern void exception3_read_access2(uae_u32 opcode, uaecptr addr, int size, int fc);
|
|
extern void exception3_write_access(uae_u32 opcode, uaecptr addr, int size, uae_u32 val, int fc);
|
|
extern void exception3_read_prefetch(uae_u32 opcode, uaecptr addr);
|
|
extern void exception3_read_prefetch_68040bug(uae_u32 opcode, uaecptr addr, uae_u16 secondarysr);
|
|
extern void exception3_read_prefetch_only(uae_u32 opcode, uaecptr addr);
|
|
extern void exception3_notinstruction(uae_u32 opcode, uaecptr addr);
|
|
extern void hardware_exception2(uaecptr addr, uae_u32 v, bool read, bool ins, int size);
|
|
extern void exception2_setup(uae_u32 opcode, uaecptr addr, bool read, int size, uae_u32 fc);
|
|
extern void exception2_read(uae_u32 opcode, uaecptr addr, int size, int fc);
|
|
extern void exception2_write(uae_u32 opcode, uaecptr addr, int size, uae_u32 val, int fc);
|
|
extern void exception2_fetch_opcode(uae_u32 opcode, int offset, int pcoffset);
|
|
extern void exception2_fetch(uae_u32 opcode, int offset, int pcoffset);
|
|
extern void m68k_reset (void);
|
|
extern void cpureset (void);
|
|
extern void cpu_halt (int id);
|
|
extern int cpu_sleep_millis(int ms);
|
|
extern void cpu_change(int newmodel);
|
|
extern void cpu_fallback(int mode);
|
|
|
|
extern void fill_prefetch (void);
|
|
extern void fill_prefetch_020_ntx(void);
|
|
extern void fill_prefetch_030_ntx(void);
|
|
extern void fill_prefetch_030_ntx_continue(void);
|
|
extern void fill_prefetch_020(void);
|
|
extern void fill_prefetch_030(void);
|
|
|
|
#define CPU_OP_NAME(a) op ## a
|
|
|
|
/* 68060 */
|
|
extern const struct cputbl op_smalltbl_0[];
|
|
extern const struct cputbl op_smalltbl_40[];
|
|
extern const struct cputbl op_smalltbl_50[];
|
|
extern const struct cputbl op_smalltbl_24[]; // CE
|
|
extern const struct cputbl op_smalltbl_33[]; // MMU
|
|
/* 68040 */
|
|
extern const struct cputbl op_smalltbl_1[];
|
|
extern const struct cputbl op_smalltbl_41[];
|
|
extern const struct cputbl op_smalltbl_51[];
|
|
extern const struct cputbl op_smalltbl_25[]; // CE
|
|
extern const struct cputbl op_smalltbl_31[]; // MMU
|
|
/* 68030 */
|
|
extern const struct cputbl op_smalltbl_2[];
|
|
extern const struct cputbl op_smalltbl_42[];
|
|
extern const struct cputbl op_smalltbl_52[];
|
|
extern const struct cputbl op_smalltbl_22[]; // prefetch
|
|
extern const struct cputbl op_smalltbl_23[]; // CE
|
|
extern const struct cputbl op_smalltbl_32[]; // MMU
|
|
extern const struct cputbl op_smalltbl_34[]; // MMU + cache
|
|
extern const struct cputbl op_smalltbl_35[]; // MMU + CE + cache
|
|
/* 68020 */
|
|
extern const struct cputbl op_smalltbl_3[];
|
|
extern const struct cputbl op_smalltbl_43[];
|
|
extern const struct cputbl op_smalltbl_53[];
|
|
extern const struct cputbl op_smalltbl_20[]; // prefetch
|
|
extern const struct cputbl op_smalltbl_21[]; // CE
|
|
/* 68010 */
|
|
extern const struct cputbl op_smalltbl_4[];
|
|
extern const struct cputbl op_smalltbl_44[];
|
|
extern const struct cputbl op_smalltbl_54[];
|
|
extern const struct cputbl op_smalltbl_11[]; // prefetch
|
|
extern const struct cputbl op_smalltbl_13[]; // CE
|
|
/* 68000 */
|
|
extern const struct cputbl op_smalltbl_5[];
|
|
extern const struct cputbl op_smalltbl_45[];
|
|
extern const struct cputbl op_smalltbl_55[];
|
|
extern const struct cputbl op_smalltbl_12[]; // prefetch
|
|
extern const struct cputbl op_smalltbl_14[]; // CE
|
|
|
|
extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
|
|
|
|
#ifdef JIT
|
|
extern void (*flush_icache)(int);
|
|
extern void compemu_reset(void);
|
|
#else
|
|
#define flush_icache(int) do {} while (0)
|
|
#define flush_icache_hard(int) do {} while (0)
|
|
#endif
|
|
bool check_prefs_changed_comp (bool);
|
|
|
|
extern int movec_illg (int regno);
|
|
extern uae_u32 val_move2c (int regno);
|
|
extern void val_move2c2 (int regno, uae_u32 val);
|
|
struct cpum2c {
|
|
int regno;
|
|
int flags;
|
|
const TCHAR *regname;
|
|
};
|
|
extern struct cpum2c m2cregs[];
|
|
|
|
extern bool is_cpu_tracer (void);
|
|
extern bool set_cpu_tracer (bool force);
|
|
extern bool can_cpu_tracer (void);
|
|
|
|
#define CPU_HALT_PPC_ONLY -1
|
|
#define CPU_HALT_BUS_ERROR_DOUBLE_FAULT 1
|
|
#define CPU_HALT_DOUBLE_FAULT 2
|
|
#define CPU_HALT_OPCODE_FETCH_FROM_NON_EXISTING_ADDRESS 3
|
|
#define CPU_HALT_ACCELERATOR_CPU_FALLBACK 4
|
|
#define CPU_HALT_ALL_CPUS_STOPPED 5
|
|
#define CPU_HALT_FAKE_DMA 6
|
|
#define CPU_HALT_AUTOCONFIG_CONFLICT 7
|
|
#define CPU_HALT_PCI_CONFLICT 8
|
|
#define CPU_HALT_CPU_STUCK 9
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#define CPU_HALT_SSP_IN_NON_EXISTING_ADDRESS 10
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#define CPU_HALT_INVALID_START_ADDRESS 11
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#define CPU_HALT_68060_HALT 12
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#define CPU_HALT_BKPT 13
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uae_u32 process_cpu_indirect_memory_read(uae_u32 addr, int size);
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void process_cpu_indirect_memory_write(uae_u32 addr, uae_u32 data, int size);
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#endif /* UAE_NEWCPU_H */
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