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WinUAE/cpuemu_31.cpp

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#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "memory.h"
#include "custom.h"
#include "events.h"
#include "newcpu.h"
#include "cpu_prefetch.h"
#include "cputbl.h"
#include "cpummu.h"
#define SET_ALWAYS_CFLG(x) SET_CFLG(x)
#define SET_ALWAYS_NFLG(x) SET_NFLG(x)
/* OR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* OR.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ORSR.B #<data>.W */
uae_u32 REGPARAM2 op_003c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
MakeSR();
uae_s16 src = get_iword_mmu040(2);
src &= 0xFF;
regs.sr |= src;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* OR.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ORSR.W #<data>.W */
uae_u32 REGPARAM2 op_007c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
MakeSR();
uae_s16 src = get_iword_mmu040(2);
if(regs.t0) check_t0_trace();
regs.sr |= src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_00a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_00a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* OR.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_00b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* OR.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_00b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* OR.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_00b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* CHK2.B #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
m68k_incpci(4);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CHK2.B #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.B #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CHK2.B #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.B #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
m68k_incpci(8);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CHK2.B #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.B #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_00fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s8)get_byte_mmu040(dsta);
upper = (uae_s32)(uae_s8)get_byte_mmu040(dsta + 1);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 0);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BTST.L Dn,Dn */
uae_u32 REGPARAM2 op_0100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVPMR.W (d16,An),Dn */
uae_u32 REGPARAM2 op_0108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_u16 val = (get_byte_mmu040(mempa) & 0xff) << 8;
val |= (get_byte_mmu040(mempa + 2) & 0xff);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(4);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B Dn,(An) */
uae_u32 REGPARAM2 op_0110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BTST.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BTST.B Dn,-(An) */
uae_u32 REGPARAM2 op_0120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BTST.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_0128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* BTST.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_0138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_0139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BTST.B Dn,(d16,PC) */
uae_u32 REGPARAM2 op_013a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = 2;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_getpci() + 2;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B Dn,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_013b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = 3;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* BTST.B Dn,#<data>.B */
uae_u32 REGPARAM2 op_013c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = get_ibyte_mmu040(2);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.L Dn,Dn */
uae_u32 REGPARAM2 op_0140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_dreg(regs, dstreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVPMR.L (d16,An),Dn */
uae_u32 REGPARAM2 op_0148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_u32 val = (get_byte_mmu040(mempa) & 0xff) << 24;
val |= (get_byte_mmu040(mempa + 2) & 0xff) << 16;
val |= (get_byte_mmu040(mempa + 4) & 0xff) << 8;
val |= (get_byte_mmu040(mempa + 6) & 0xff);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(4);
return (4 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B Dn,(An) */
uae_u32 REGPARAM2 op_0150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BCHG.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BCHG.B Dn,-(An) */
uae_u32 REGPARAM2 op_0160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BCHG.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_0168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* BCHG.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_0178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_0179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BCLR.L Dn,Dn */
uae_u32 REGPARAM2 op_0180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_dreg(regs, dstreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVPRM.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_0188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
put_byte_mmu040(mempa, src >> 8);
put_byte_mmu040(mempa + 2, src);
m68k_incpci(4);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B Dn,(An) */
uae_u32 REGPARAM2 op_0190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BCLR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_0198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BCLR.B Dn,-(An) */
uae_u32 REGPARAM2 op_01a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BCLR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_01a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_01b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* BCLR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_01b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_01b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BSET.L Dn,Dn */
uae_u32 REGPARAM2 op_01c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_dreg(regs, dstreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVPRM.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_01c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
put_byte_mmu040(mempa, src >> 24);
put_byte_mmu040(mempa + 2, src >> 16);
put_byte_mmu040(mempa + 4, src >> 8);
put_byte_mmu040(mempa + 6, src);
m68k_incpci(4);
return (4 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B Dn,(An) */
uae_u32 REGPARAM2 op_01d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BSET.B Dn,(An)+ */
uae_u32 REGPARAM2 op_01d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BSET.B Dn,-(An) */
uae_u32 REGPARAM2 op_01e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BSET.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_01e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_01f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* BSET.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_01f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_01f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0200_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0210_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0218_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0220_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0228_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0230_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* AND.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0238_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0239_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ANDSR.B #<data>.W */
uae_u32 REGPARAM2 op_023c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
MakeSR();
uae_s16 src = get_iword_mmu040(2);
src &= 0xFF;
src |= 0xff00;
regs.sr &= src;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0240_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0250_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0258_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0260_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0268_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0270_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* AND.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0278_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0279_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ANDSR.W #<data>.W */
uae_u32 REGPARAM2 op_027c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
MakeSR();
uae_s16 src = get_iword_mmu040(2);
if(regs.t0) check_t0_trace();
regs.sr &= src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0280_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0290_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0298_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_02a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_02a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* AND.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_02b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* AND.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_02b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* AND.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_02b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* CHK2.W #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
m68k_incpci(4);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CHK2.W #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.W #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CHK2.W #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.W #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
m68k_incpci(8);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CHK2.W #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.W #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_02fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = (uae_s32)(uae_s16)get_word_mmu040(dsta);
upper = (uae_s32)(uae_s16)get_word_mmu040(dsta + 2);
if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 1);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* SUB.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0400_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0410_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0418_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0420_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0428_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0430_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* SUB.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0438_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0439_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* SUB.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0440_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0450_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0458_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0460_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0468_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0470_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* SUB.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0478_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0479_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* SUB.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0480_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0490_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0498_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_04a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_04a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* SUB.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_04b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* SUB.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_04b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* SUB.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_04b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* CHK2.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
m68k_incpci(4);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CHK2.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CHK2.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
m68k_incpci(8);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CHK2.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
m68k_incpci(6);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK2.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_04fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];
lower = get_long_mmu040(dsta); upper = get_long_mmu040(dsta + 4);
SET_CFLG(0);
SET_ZFLG(0);
setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : 2);
if(upper == reg || lower == reg) {
SET_ZFLG(1);
}else{
if (lower <= upper && (reg < lower || reg > upper)) SET_ALWAYS_CFLG(1);
if (lower > upper && reg > upper && reg < lower) SET_ALWAYS_CFLG(1);
}
if ((extra & 0x800) && GET_CFLG()) {
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* ADD.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0600_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0610_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0618_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0620_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0628_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0630_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* ADD.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0638_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0639_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ADD.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0640_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0650_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0658_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0660_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0668_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0670_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* ADD.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0678_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0679_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ADD.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0680_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0690_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0698_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_06a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_06a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ADD.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_06b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* ADD.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_06b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* ADD.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_06b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* RTM.L Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* RTM.L An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CALLM.L (d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_06fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* BTST.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0800_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0810_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0818_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0820_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(4);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BTST.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0828_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BTST.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0830_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* BTST.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0838_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BTST.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0839_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* BTST.B #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_083a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BTST.B #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_083b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* BCHG.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0840_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_dreg(regs, dstreg) = (dst);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0850_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0858_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0860_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCHG.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0868_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BCHG.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0870_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* BCHG.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0878_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BCHG.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0879_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
dst ^= (1 << src);
SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* BCLR.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_0880_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_dreg(regs, dstreg) = (dst);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_0890_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0898_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_08a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BCLR.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_08a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BCLR.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_08b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* BCLR.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_08b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BCLR.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_08b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst &= ~(1 << src);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* BSET.L #<data>.W,Dn */
uae_u32 REGPARAM2 op_08c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= 31;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_dreg(regs, dstreg) = (dst);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B #<data>.W,(An) */
uae_u32 REGPARAM2 op_08d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_08d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B #<data>.W,-(An) */
uae_u32 REGPARAM2 op_08e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* BSET.B #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_08e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BSET.B #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_08f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* BSET.B #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_08f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BSET.B #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_08f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src &= 7;
SET_ZFLG(1 ^ ((dst >> src) & 1));
dst |= (1 << src);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EOR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0a00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0a10_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0a18_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0a20_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0a28_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0a30_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* EOR.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0a38_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0a39_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EORSR.B #<data>.W */
uae_u32 REGPARAM2 op_0a3c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
MakeSR();
uae_s16 src = get_iword_mmu040(2);
src &= 0xFF;
regs.sr ^= src;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0a40_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0a50_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0a58_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0a60_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0a68_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0a70_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* EOR.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0a78_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0a79_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EORSR.W #<data>.W */
uae_u32 REGPARAM2 op_0a7c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
MakeSR();
uae_s16 src = get_iword_mmu040(2);
if(regs.t0) check_t0_trace();
regs.sr ^= src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0a80_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0a90_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0a98_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_0aa0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_0aa8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EOR.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0ab0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* EOR.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_0ab8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EOR.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_0ab9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* CAS.B #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ad0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.B #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ad8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.B #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ae0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.B #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ae8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CAS.B #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0af0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CAS.B #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0af8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CAS.B #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0af9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_lrmw_byte_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(m68k_dreg(regs, rc)));
int flgs = ((uae_s8)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(m68k_dreg(regs, rc))) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_byte_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_byte_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CMP.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_0c00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_0c10_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_0c18_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_0c20_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_0c28_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0c30_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* CMP.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_0c38_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_0c39_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* CMP.B #<data>.B,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0c3a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CMP.B #<data>.B,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0c3b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CMP.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_0c40_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_0c50_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_0c58_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_0c60_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_0c68_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0c70_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* CMP.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_0c78_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_0c79_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* CMP.W #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0c7a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CMP.W #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0c7b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CMP.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_0c80_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_0c90_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_0c98_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_0ca0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_0ca8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* CMP.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_0cb0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* CMP.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_0cb8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* CMP.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_0cb9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(10);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* CMP.L #<data>.L,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 6;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(6);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CMP.L #<data>.L,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cbb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
#endif
/* CAS.W #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.W #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cd8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.W #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ce0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.W #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ce8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CAS.W #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CAS.W #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CAS.W #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s16 dst = get_lrmw_word_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(m68k_dreg(regs, rc)));
int flgs = ((uae_s16)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, rc))) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_word_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_word_mmu040(dsta, dst);
m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CAS2.W #<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0cfc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 extra;
extra = get_ilong_mmu040(2);
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
uae_u16 dst1 = get_lrmw_word_mmu040(rn1), dst2 = get_lrmw_word_mmu040(rn2);
uae_u32 newv = ((uae_u16)(dst1)) - ((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7)));
int flgs = ((uae_s16)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
int flgo = ((uae_s16)(dst1)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u16)(dst1)));
SET_NFLG(flgn != 0);
if (GET_ZFLG()) {
uae_u32 newv = ((uae_u16)(dst2)) - ((uae_u16)(m68k_dreg(regs, extra & 7)));
int flgs = ((uae_s16)(m68k_dreg(regs, extra & 7))) < 0;
int flgo = ((uae_s16)(dst2)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(m68k_dreg(regs, extra & 7))) > ((uae_u16)(dst2)));
SET_NFLG(flgn != 0);
if (GET_ZFLG()) {
put_lrmw_word_mmu040(rn2, m68k_dreg(regs, (extra >> 6) & 7));
put_lrmw_word_mmu040(rn1, m68k_dreg(regs, (extra >> 22) & 7));
}
}
if (!GET_ZFLG()) {
m68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);
m68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);
}
if(regs.t0) check_t0_trace();
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.B #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e10_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg);
uae_s8 src = sfc040_get_byte(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.B #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e18_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src = regs.regs[(extra >> 12) & 15];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg);
uae_s8 src = sfc040_get_byte(srca);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.B #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e20_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
src = regs.regs[(extra >> 12) & 15];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
uae_s8 src = sfc040_get_byte(srca);
m68k_areg(regs, dstreg) = srca;
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.B #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e28_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 src = sfc040_get_byte(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
m68k_incpci(6);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.B #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e30_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
m68k_incpci(4);
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
uae_s8 src = sfc040_get_byte(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,2 */
#endif
/* MOVES.B #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e38_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s8 src = sfc040_get_byte(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
m68k_incpci(6);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.B #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e39_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = get_ilong_mmu040(4);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_byte(dsta, src);
} else {
uaecptr srca;
srca = get_ilong_mmu040(4);
uae_s8 src = sfc040_get_byte(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xff) | ((src) & 0xff);
}
m68k_incpci(8);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* MOVES.W #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e50_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg);
uae_s16 src = sfc040_get_word(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.W #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e58_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
src = regs.regs[(extra >> 12) & 15];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg);
uae_s16 src = sfc040_get_word(srca);
m68k_areg(regs, dstreg) += 2;
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.W #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e60_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
src = regs.regs[(extra >> 12) & 15];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg) - 2;
uae_s16 src = sfc040_get_word(srca);
m68k_areg(regs, dstreg) = srca;
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.W #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e68_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 src = sfc040_get_word(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
m68k_incpci(6);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.W #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e70_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
m68k_incpci(4);
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
uae_s16 src = sfc040_get_word(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,2 */
#endif
/* MOVES.W #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e78_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s16 src = sfc040_get_word(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
m68k_incpci(6);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.W #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e79_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = get_ilong_mmu040(4);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_word(dsta, src);
} else {
uaecptr srca;
srca = get_ilong_mmu040(4);
uae_s16 src = sfc040_get_word(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (m68k_dreg(regs, (extra >> 12) & 7) & ~0xffff) | ((src) & 0xffff);
}
m68k_incpci(8);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* MOVES.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e90_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg);
uae_s32 src = sfc040_get_long(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0e98_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
src = regs.regs[(extra >> 12) & 15];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg);
uae_s32 src = sfc040_get_long(srca);
m68k_areg(regs, dstreg) += 4;
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ea0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
src = regs.regs[(extra >> 12) & 15];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg) - 4;
uae_s32 src = sfc040_get_long(srca);
m68k_areg(regs, dstreg) = srca;
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
m68k_incpci(4);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVES.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ea8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 src = sfc040_get_long(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
m68k_incpci(6);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0eb0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
m68k_incpci(4);
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
uae_s32 src = sfc040_get_long(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,2 */
#endif
/* MOVES.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0eb8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 src = sfc040_get_long(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
m68k_incpci(6);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVES.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0eb9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 extra = get_iword_mmu040(2);
if (extra & 0x800) {
uae_u32 src = regs.regs[(extra >> 12) & 15];
uaecptr dsta;
dsta = get_ilong_mmu040(4);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
dfc040_put_long(dsta, src);
} else {
uaecptr srca;
srca = get_ilong_mmu040(4);
uae_s32 src = sfc040_get_long(srca);
if (extra & 0x8000) {
m68k_areg(regs, (extra >> 12) & 7) = src;
} else {
m68k_dreg(regs, (extra >> 12) & 7) = (src);
}
m68k_incpci(8);
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CAS.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ed0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ed8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ee0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CAS.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ee8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CAS.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ef0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* CAS.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ef8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CAS.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0ef9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s32 dst = get_lrmw_long_mmu040(dsta);
int ru = (src >> 6) & 7;
int rc = src & 7;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(m68k_dreg(regs, rc)));
int flgs = ((uae_s32)(m68k_dreg(regs, rc))) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, rc))) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
if (GET_ZFLG()) {
put_lrmw_long_mmu040(dsta, (m68k_dreg(regs, ru)));
} else {
put_lrmw_long_mmu040(dsta, dst);
m68k_dreg(regs, rc) = dst;
}
if(regs.t0) check_t0_trace();
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* CAS2.L #<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_0efc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 extra;
extra = get_ilong_mmu040(2);
uae_u32 rn1 = regs.regs[(extra >> 28) & 15];
uae_u32 rn2 = regs.regs[(extra >> 12) & 15];
uae_u32 dst1 = get_lrmw_long_mmu040(rn1), dst2 = get_lrmw_long_mmu040(rn2);
uae_u32 newv = ((uae_u32)(dst1)) - ((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7)));
int flgs = ((uae_s32)(m68k_dreg(regs, (extra >> 16) & 7))) < 0;
int flgo = ((uae_s32)(dst1)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, (extra >> 16) & 7))) > ((uae_u32)(dst1)));
SET_NFLG(flgn != 0);
if (GET_ZFLG()) {
uae_u32 newv = ((uae_u32)(dst2)) - ((uae_u32)(m68k_dreg(regs, extra & 7)));
int flgs = ((uae_s32)(m68k_dreg(regs, extra & 7))) < 0;
int flgo = ((uae_s32)(dst2)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(m68k_dreg(regs, extra & 7))) > ((uae_u32)(dst2)));
SET_NFLG(flgn != 0);
if (GET_ZFLG()) {
put_lrmw_long_mmu040(rn2, m68k_dreg(regs, (extra >> 6) & 7));
put_lrmw_long_mmu040(rn1, m68k_dreg(regs, (extra >> 22) & 7));
}
}
if (!GET_ZFLG()) {
m68k_dreg(regs, (extra >> 16) & 7) = dst1;
m68k_dreg(regs, (extra >> 0) & 7) = dst2;
}
if(regs.t0) check_t0_trace();
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MOVE.B Dn,Dn */
uae_u32 REGPARAM2 op_1000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An),Dn */
uae_u32 REGPARAM2 op_1010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An)+,Dn */
uae_u32 REGPARAM2 op_1018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B -(An),Dn */
uae_u32 REGPARAM2 op_1020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (d16,An),Dn */
uae_u32 REGPARAM2 op_1028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_1030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_1038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_1039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_103a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_103b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_103c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B Dn,(An) */
uae_u32 REGPARAM2 op_1080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An),(An) */
uae_u32 REGPARAM2 op_1090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An)+,(An) */
uae_u32 REGPARAM2 op_1098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B -(An),(An) */
uae_u32 REGPARAM2 op_10a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (d16,An),(An) */
uae_u32 REGPARAM2 op_10a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_10b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (xxx).W,(An) */
uae_u32 REGPARAM2 op_10b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (xxx).L,(An) */
uae_u32 REGPARAM2 op_10b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d16,PC),(An) */
uae_u32 REGPARAM2 op_10ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_10bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B #<data>.B,(An) */
uae_u32 REGPARAM2 op_10bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B Dn,(An)+ */
uae_u32 REGPARAM2 op_10c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An),(An)+ */
uae_u32 REGPARAM2 op_10d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An)+,(An)+ */
uae_u32 REGPARAM2 op_10d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B -(An),(An)+ */
uae_u32 REGPARAM2 op_10e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (d16,An),(An)+ */
uae_u32 REGPARAM2 op_10e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_10f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_10f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_10f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_10fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_10fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B #<data>.B,(An)+ */
uae_u32 REGPARAM2 op_10fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B Dn,-(An) */
uae_u32 REGPARAM2 op_1100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An),-(An) */
uae_u32 REGPARAM2 op_1110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (An)+,-(An) */
uae_u32 REGPARAM2 op_1118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B -(An),-(An) */
uae_u32 REGPARAM2 op_1120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.B (d16,An),-(An) */
uae_u32 REGPARAM2 op_1128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_1130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (xxx).W,-(An) */
uae_u32 REGPARAM2 op_1138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (xxx).L,-(An) */
uae_u32 REGPARAM2 op_1139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d16,PC),-(An) */
uae_u32 REGPARAM2 op_113a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_113b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B #<data>.B,-(An) */
uae_u32 REGPARAM2 op_113c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_1140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (An),(d16,An) */
uae_u32 REGPARAM2 op_1150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (An)+,(d16,An) */
uae_u32 REGPARAM2 op_1158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B -(An),(d16,An) */
uae_u32 REGPARAM2 op_1160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_1168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_1170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.B (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_1178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_1179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.B (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_117a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_117b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.B #<data>.B,(d16,An) */
uae_u32 REGPARAM2 op_117c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_1180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_1190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_1198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.B (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.B (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,2 */
/* MOVE.B (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.B (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* MOVE.B (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.B (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_11bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,2 */
/* MOVE.B #<data>.B,(d8,An,Xn) */
uae_u32 REGPARAM2 op_11bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_11c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (An),(xxx).W */
uae_u32 REGPARAM2 op_11d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (An)+,(xxx).W */
uae_u32 REGPARAM2 op_11d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B -(An),(xxx).W */
uae_u32 REGPARAM2 op_11e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.B (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_11e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_11f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.B (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_11f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_11f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.B (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_11fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_11fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.B #<data>.B,(xxx).W */
uae_u32 REGPARAM2 op_11fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_13c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (An),(xxx).L */
uae_u32 REGPARAM2 op_13d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (An)+,(xxx).L */
uae_u32 REGPARAM2 op_13d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B -(An),(xxx).L */
uae_u32 REGPARAM2 op_13e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.B (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_13e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.B (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_13f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 6,0 */
/* MOVE.B (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_13f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.B (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_13f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* MOVE.B (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_13fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.B (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_13fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 6,0 */
/* MOVE.B #<data>.B,(xxx).L */
uae_u32 REGPARAM2 op_13fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L Dn,Dn */
uae_u32 REGPARAM2 op_2000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L An,Dn */
uae_u32 REGPARAM2 op_2008_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An),Dn */
uae_u32 REGPARAM2 op_2010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An)+,Dn */
uae_u32 REGPARAM2 op_2018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L -(An),Dn */
uae_u32 REGPARAM2 op_2020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (d16,An),Dn */
uae_u32 REGPARAM2 op_2028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_2030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_2038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_2039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_203a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_203b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_203c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVEA.L Dn,An */
uae_u32 REGPARAM2 op_2040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.L An,An */
uae_u32 REGPARAM2 op_2048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.L (An),An */
uae_u32 REGPARAM2 op_2050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.L (An)+,An */
uae_u32 REGPARAM2 op_2058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
mmufixup[0].reg = -1;
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.L -(An),An */
uae_u32 REGPARAM2 op_2060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
mmufixup[0].reg = -1;
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.L (d16,An),An */
uae_u32 REGPARAM2 op_2068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_2070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVEA.L (xxx).W,An */
uae_u32 REGPARAM2 op_2078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.L (xxx).L,An */
uae_u32 REGPARAM2 op_2079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVEA.L (d16,PC),An */
uae_u32 REGPARAM2 op_207a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_207b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVEA.L #<data>.L,An */
uae_u32 REGPARAM2 op_207c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L Dn,(An) */
uae_u32 REGPARAM2 op_2080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L An,(An) */
uae_u32 REGPARAM2 op_2088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An),(An) */
uae_u32 REGPARAM2 op_2090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An)+,(An) */
uae_u32 REGPARAM2 op_2098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L -(An),(An) */
uae_u32 REGPARAM2 op_20a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (d16,An),(An) */
uae_u32 REGPARAM2 op_20a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_20b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (xxx).W,(An) */
uae_u32 REGPARAM2 op_20b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (xxx).L,(An) */
uae_u32 REGPARAM2 op_20b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d16,PC),(An) */
uae_u32 REGPARAM2 op_20ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_20bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L #<data>.L,(An) */
uae_u32 REGPARAM2 op_20bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L Dn,(An)+ */
uae_u32 REGPARAM2 op_20c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L An,(An)+ */
uae_u32 REGPARAM2 op_20c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An),(An)+ */
uae_u32 REGPARAM2 op_20d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An)+,(An)+ */
uae_u32 REGPARAM2 op_20d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L -(An),(An)+ */
uae_u32 REGPARAM2 op_20e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (d16,An),(An)+ */
uae_u32 REGPARAM2 op_20e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_20f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_20f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_20f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_20fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_20fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L #<data>.L,(An)+ */
uae_u32 REGPARAM2 op_20fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L Dn,-(An) */
uae_u32 REGPARAM2 op_2100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L An,-(An) */
uae_u32 REGPARAM2 op_2108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An),-(An) */
uae_u32 REGPARAM2 op_2110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (An)+,-(An) */
uae_u32 REGPARAM2 op_2118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L -(An),-(An) */
uae_u32 REGPARAM2 op_2120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.L (d16,An),-(An) */
uae_u32 REGPARAM2 op_2128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_2130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (xxx).W,-(An) */
uae_u32 REGPARAM2 op_2138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (xxx).L,-(An) */
uae_u32 REGPARAM2 op_2139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d16,PC),-(An) */
uae_u32 REGPARAM2 op_213a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_213b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L #<data>.L,-(An) */
uae_u32 REGPARAM2 op_213c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_2140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L An,(d16,An) */
uae_u32 REGPARAM2 op_2148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (An),(d16,An) */
uae_u32 REGPARAM2 op_2150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (An)+,(d16,An) */
uae_u32 REGPARAM2 op_2158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L -(An),(d16,An) */
uae_u32 REGPARAM2 op_2160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_2168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_2170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.L (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_2178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_2179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_217a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_217b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.L #<data>.L,(d16,An) */
uae_u32 REGPARAM2 op_217c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L An,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_2190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_2198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.L (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.L (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,2 */
/* MOVE.L (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.L (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* MOVE.L (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.L (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_21bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,2 */
/* MOVE.L #<data>.L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_21bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* MOVE.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_21c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L An,(xxx).W */
uae_u32 REGPARAM2 op_21c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (An),(xxx).W */
uae_u32 REGPARAM2 op_21d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (An)+,(xxx).W */
uae_u32 REGPARAM2 op_21d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L -(An),(xxx).W */
uae_u32 REGPARAM2 op_21e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.L (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_21e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_21f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.L (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_21f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_21f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_21fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_21fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.L #<data>.L,(xxx).W */
uae_u32 REGPARAM2 op_21fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_23c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L An,(xxx).L */
uae_u32 REGPARAM2 op_23c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (An),(xxx).L */
uae_u32 REGPARAM2 op_23d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (An)+,(xxx).L */
uae_u32 REGPARAM2 op_23d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L -(An),(xxx).L */
uae_u32 REGPARAM2 op_23e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.L (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_23e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_23f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 6,0 */
/* MOVE.L (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_23f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_23f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* MOVE.L (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_23fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.L (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_23fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 6,0 */
/* MOVE.L #<data>.L,(xxx).L */
uae_u32 REGPARAM2 op_23fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* MOVE.W Dn,Dn */
uae_u32 REGPARAM2 op_3000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W An,Dn */
uae_u32 REGPARAM2 op_3008_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An),Dn */
uae_u32 REGPARAM2 op_3010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An)+,Dn */
uae_u32 REGPARAM2 op_3018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W -(An),Dn */
uae_u32 REGPARAM2 op_3020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (d16,An),Dn */
uae_u32 REGPARAM2 op_3028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_3030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_3038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_3039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_303a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_303b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_303c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.W Dn,An */
uae_u32 REGPARAM2 op_3040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.W An,An */
uae_u32 REGPARAM2 op_3048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.W (An),An */
uae_u32 REGPARAM2 op_3050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.W (An)+,An */
uae_u32 REGPARAM2 op_3058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
mmufixup[0].reg = -1;
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.W -(An),An */
uae_u32 REGPARAM2 op_3060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
mmufixup[0].reg = -1;
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVEA.W (d16,An),An */
uae_u32 REGPARAM2 op_3068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_3070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVEA.W (xxx).W,An */
uae_u32 REGPARAM2 op_3078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.W (xxx).L,An */
uae_u32 REGPARAM2 op_3079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVEA.W (d16,PC),An */
uae_u32 REGPARAM2 op_307a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVEA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_307b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVEA.W #<data>.W,An */
uae_u32 REGPARAM2 op_307c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
src = (uae_s32)(uae_s16)src;
m68k_areg(regs, dstreg) = (uae_s32)(uae_s16)(src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W Dn,(An) */
uae_u32 REGPARAM2 op_3080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W An,(An) */
uae_u32 REGPARAM2 op_3088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An),(An) */
uae_u32 REGPARAM2 op_3090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An)+,(An) */
uae_u32 REGPARAM2 op_3098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W -(An),(An) */
uae_u32 REGPARAM2 op_30a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (d16,An),(An) */
uae_u32 REGPARAM2 op_30a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,An,Xn),(An) */
uae_u32 REGPARAM2 op_30b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (xxx).W,(An) */
uae_u32 REGPARAM2 op_30b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (xxx).L,(An) */
uae_u32 REGPARAM2 op_30b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d16,PC),(An) */
uae_u32 REGPARAM2 op_30ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,PC,Xn),(An) */
uae_u32 REGPARAM2 op_30bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_30bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W Dn,(An)+ */
uae_u32 REGPARAM2 op_30c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W An,(An)+ */
uae_u32 REGPARAM2 op_30c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An),(An)+ */
uae_u32 REGPARAM2 op_30d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An)+,(An)+ */
uae_u32 REGPARAM2 op_30d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W -(An),(An)+ */
uae_u32 REGPARAM2 op_30e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (d16,An),(An)+ */
uae_u32 REGPARAM2 op_30e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,An,Xn),(An)+ */
uae_u32 REGPARAM2 op_30f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (xxx).W,(An)+ */
uae_u32 REGPARAM2 op_30f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (xxx).L,(An)+ */
uae_u32 REGPARAM2 op_30f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d16,PC),(An)+ */
uae_u32 REGPARAM2 op_30fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,PC,Xn),(An)+ */
uae_u32 REGPARAM2 op_30fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_30fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W Dn,-(An) */
uae_u32 REGPARAM2 op_3100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W An,-(An) */
uae_u32 REGPARAM2 op_3108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An),-(An) */
uae_u32 REGPARAM2 op_3110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (An)+,-(An) */
uae_u32 REGPARAM2 op_3118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W -(An),-(An) */
uae_u32 REGPARAM2 op_3120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MOVE.W (d16,An),-(An) */
uae_u32 REGPARAM2 op_3128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,An,Xn),-(An) */
uae_u32 REGPARAM2 op_3130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (xxx).W,-(An) */
uae_u32 REGPARAM2 op_3138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (xxx).L,-(An) */
uae_u32 REGPARAM2 op_3139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d16,PC),-(An) */
uae_u32 REGPARAM2 op_313a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d8,PC,Xn),-(An) */
uae_u32 REGPARAM2 op_313b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_313c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
m68k_areg(regs, dstreg) = dsta;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_3140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W An,(d16,An) */
uae_u32 REGPARAM2 op_3148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (An),(d16,An) */
uae_u32 REGPARAM2 op_3150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (An)+,(d16,An) */
uae_u32 REGPARAM2 op_3158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W -(An),(d16,An) */
uae_u32 REGPARAM2 op_3160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d16,An),(d16,An) */
uae_u32 REGPARAM2 op_3168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d8,An,Xn),(d16,An) */
uae_u32 REGPARAM2 op_3170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.W (xxx).W,(d16,An) */
uae_u32 REGPARAM2 op_3178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (xxx).L,(d16,An) */
uae_u32 REGPARAM2 op_3179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.W (d16,PC),(d16,An) */
uae_u32 REGPARAM2 op_317a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d8,PC,Xn),(d16,An) */
uae_u32 REGPARAM2 op_317b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_317c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W An,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_3190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (An)+,(d8,An,Xn) */
uae_u32 REGPARAM2 op_3198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W -(An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MOVE.W (d16,An),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.W (d8,An,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,2 */
/* MOVE.W (xxx).W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.W (xxx).L,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
m68k_incpci(6);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 2,0 */
/* MOVE.W (d16,PC),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.W (d8,PC,Xn),(d8,An,Xn) */
uae_u32 REGPARAM2 op_31bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 1);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,2 */
/* MOVE.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_31bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MOVE.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_31c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W An,(xxx).W */
uae_u32 REGPARAM2 op_31c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (An),(xxx).W */
uae_u32 REGPARAM2 op_31d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (An)+,(xxx).W */
uae_u32 REGPARAM2 op_31d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W -(An),(xxx).W */
uae_u32 REGPARAM2 op_31e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MOVE.W (d16,An),(xxx).W */
uae_u32 REGPARAM2 op_31e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d8,An,Xn),(xxx).W */
uae_u32 REGPARAM2 op_31f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.W (xxx).W,(xxx).W */
uae_u32 REGPARAM2 op_31f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (xxx).L,(xxx).W */
uae_u32 REGPARAM2 op_31f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.W (d16,PC),(xxx).W */
uae_u32 REGPARAM2 op_31fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d8,PC,Xn),(xxx).W */
uae_u32 REGPARAM2 op_31fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 4,0 */
/* MOVE.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_31fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_33c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W An,(xxx).L */
uae_u32 REGPARAM2 op_33c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (An),(xxx).L */
uae_u32 REGPARAM2 op_33d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (An)+,(xxx).L */
uae_u32 REGPARAM2 op_33d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W -(An),(xxx).L */
uae_u32 REGPARAM2 op_33e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MOVE.W (d16,An),(xxx).L */
uae_u32 REGPARAM2 op_33e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.W (d8,An,Xn),(xxx).L */
uae_u32 REGPARAM2 op_33f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 6,0 */
/* MOVE.W (xxx).W,(xxx).L */
uae_u32 REGPARAM2 op_33f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.W (xxx).L,(xxx).L */
uae_u32 REGPARAM2 op_33f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(6);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(10);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 10 0,0 */
/* MOVE.W (d16,PC),(xxx).L */
uae_u32 REGPARAM2 op_33fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MOVE.W (d8,PC,Xn),(xxx).L */
uae_u32 REGPARAM2 op_33fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uaecptr dsta;
dsta = get_ilong_mmu040(0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 6,0 */
/* MOVE.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_33fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(8);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* NEGX.B Dn */
uae_u32 REGPARAM2 op_4000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.B (An) */
uae_u32 REGPARAM2 op_4010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.B (An)+ */
uae_u32 REGPARAM2 op_4018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.B -(An) */
uae_u32 REGPARAM2 op_4020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.B (d16,An) */
uae_u32 REGPARAM2 op_4028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEGX.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NEGX.B (xxx).W */
uae_u32 REGPARAM2 op_4038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEGX.B (xxx).L */
uae_u32 REGPARAM2 op_4039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* NEGX.W Dn */
uae_u32 REGPARAM2 op_4040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.W (An) */
uae_u32 REGPARAM2 op_4050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.W (An)+ */
uae_u32 REGPARAM2 op_4058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.W -(An) */
uae_u32 REGPARAM2 op_4060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.W (d16,An) */
uae_u32 REGPARAM2 op_4068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEGX.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NEGX.W (xxx).W */
uae_u32 REGPARAM2 op_4078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEGX.W (xxx).L */
uae_u32 REGPARAM2 op_4079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* NEGX.L Dn */
uae_u32 REGPARAM2 op_4080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, srcreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.L (An) */
uae_u32 REGPARAM2 op_4090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.L (An)+ */
uae_u32 REGPARAM2 op_4098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.L -(An) */
uae_u32 REGPARAM2 op_40a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEGX.L (d16,An) */
uae_u32 REGPARAM2 op_40a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEGX.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_40b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NEGX.L (xxx).W */
uae_u32 REGPARAM2 op_40b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEGX.L (xxx).L */
uae_u32 REGPARAM2 op_40b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 newv = 0 - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVSR2.W Dn */
uae_u32 REGPARAM2 op_40c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
MakeSR();
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVSR2.W (An) */
uae_u32 REGPARAM2 op_40d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg);
MakeSR();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVSR2.W (An)+ */
uae_u32 REGPARAM2 op_40d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += 2;
MakeSR();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVSR2.W -(An) */
uae_u32 REGPARAM2 op_40e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
MakeSR();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVSR2.W (d16,An) */
uae_u32 REGPARAM2 op_40e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
MakeSR();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVSR2.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_40f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
MakeSR();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MVSR2.W (xxx).W */
uae_u32 REGPARAM2 op_40f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
MakeSR();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVSR2.W (xxx).L */
uae_u32 REGPARAM2 op_40f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = get_ilong_mmu040(2);
MakeSR();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CHK.L Dn,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CHK.L (An),Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CHK.L (An)+,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CHK.L -(An),Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* CHK.L (d16,An),Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CHK.L (d8,An,Xn),Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
#endif
/* CHK.L (xxx).W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CHK.L (xxx).L,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(6);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK.L (d16,PC),Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_413a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* CHK.L (d8,PC,Xn),Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_413b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
#endif
/* CHK.L #<data>.L,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_413c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(6);
if (dst > src) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 2);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* CHK.W Dn,Dn */
uae_u32 REGPARAM2 op_4180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CHK.W (An),Dn */
uae_u32 REGPARAM2 op_4190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CHK.W (An)+,Dn */
uae_u32 REGPARAM2 op_4198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CHK.W -(An),Dn */
uae_u32 REGPARAM2 op_41a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
m68k_incpci(2);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CHK.W (d16,An),Dn */
uae_u32 REGPARAM2 op_41a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CHK.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_41b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CHK.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_41b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CHK.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_41b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(6);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CHK.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_41ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CHK.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_41bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CHK.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_41bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
if (dst > src) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if ((uae_s32)dst < 0) {
setchkundefinedflags(src, dst, 1);
Exception_cpu(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
setchkundefinedflags(src, dst, 1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LEA.L (An),An */
uae_u32 REGPARAM2 op_41d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
m68k_areg(regs, dstreg) = (srca);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LEA.L (d16,An),An */
uae_u32 REGPARAM2 op_41e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
m68k_areg(regs, dstreg) = (srca);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LEA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_41f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
m68k_areg(regs, dstreg) = (srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* LEA.L (xxx).W,An */
uae_u32 REGPARAM2 op_41f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
m68k_areg(regs, dstreg) = (srca);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LEA.L (xxx).L,An */
uae_u32 REGPARAM2 op_41f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
m68k_areg(regs, dstreg) = (srca);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* LEA.L (d16,PC),An */
uae_u32 REGPARAM2 op_41fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
m68k_areg(regs, dstreg) = (srca);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LEA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_41fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
m68k_areg(regs, dstreg) = (srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CLR.B Dn */
uae_u32 REGPARAM2 op_4200_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.B (An) */
uae_u32 REGPARAM2 op_4210_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.B (An)+ */
uae_u32 REGPARAM2 op_4218_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.B -(An) */
uae_u32 REGPARAM2 op_4220_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.B (d16,An) */
uae_u32 REGPARAM2 op_4228_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CLR.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4230_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CLR.B (xxx).W */
uae_u32 REGPARAM2 op_4238_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CLR.B (xxx).L */
uae_u32 REGPARAM2 op_4239_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(0)) == 0);
SET_NFLG(((uae_s8)(0)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CLR.W Dn */
uae_u32 REGPARAM2 op_4240_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.W (An) */
uae_u32 REGPARAM2 op_4250_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.W (An)+ */
uae_u32 REGPARAM2 op_4258_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.W -(An) */
uae_u32 REGPARAM2 op_4260_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.W (d16,An) */
uae_u32 REGPARAM2 op_4268_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CLR.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4270_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CLR.W (xxx).W */
uae_u32 REGPARAM2 op_4278_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CLR.W (xxx).L */
uae_u32 REGPARAM2 op_4279_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(0)) == 0);
SET_NFLG(((uae_s16)(0)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CLR.L Dn */
uae_u32 REGPARAM2 op_4280_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_dreg(regs, srcreg) = (0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.L (An) */
uae_u32 REGPARAM2 op_4290_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.L (An)+ */
uae_u32 REGPARAM2 op_4298_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.L -(An) */
uae_u32 REGPARAM2 op_42a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CLR.L (d16,An) */
uae_u32 REGPARAM2 op_42a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CLR.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_42b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CLR.L (xxx).W */
uae_u32 REGPARAM2 op_42b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CLR.L (xxx).L */
uae_u32 REGPARAM2 op_42b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(0)) == 0);
SET_NFLG(((uae_s32)(0)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVSR2.B Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
MakeSR();
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr & 0xff) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* MVSR2.B (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
MakeSR();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* MVSR2.B (An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += 2;
MakeSR();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* MVSR2.B -(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
MakeSR();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* MVSR2.B (d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
MakeSR();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MVSR2.B (d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
MakeSR();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
#endif
/* MVSR2.B (xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
MakeSR();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MVSR2.B (xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_42f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
MakeSR();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, regs.sr & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* NEG.B Dn */
uae_u32 REGPARAM2 op_4400_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.B (An) */
uae_u32 REGPARAM2 op_4410_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.B (An)+ */
uae_u32 REGPARAM2 op_4418_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.B -(An) */
uae_u32 REGPARAM2 op_4420_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.B (d16,An) */
uae_u32 REGPARAM2 op_4428_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEG.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4430_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NEG.B (xxx).W */
uae_u32 REGPARAM2 op_4438_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEG.B (xxx).L */
uae_u32 REGPARAM2 op_4439_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ((uae_u8)(0)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(0)) < 0;
int flgn = ((uae_s8)(dst)) < 0;
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* NEG.W Dn */
uae_u32 REGPARAM2 op_4440_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.W (An) */
uae_u32 REGPARAM2 op_4450_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.W (An)+ */
uae_u32 REGPARAM2 op_4458_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.W -(An) */
uae_u32 REGPARAM2 op_4460_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.W (d16,An) */
uae_u32 REGPARAM2 op_4468_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEG.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4470_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NEG.W (xxx).W */
uae_u32 REGPARAM2 op_4478_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEG.W (xxx).L */
uae_u32 REGPARAM2 op_4479_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ((uae_u16)(0)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(0)) < 0;
int flgn = ((uae_s16)(dst)) < 0;
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* NEG.L Dn */
uae_u32 REGPARAM2 op_4480_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, srcreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.L (An) */
uae_u32 REGPARAM2 op_4490_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.L (An)+ */
uae_u32 REGPARAM2 op_4498_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.L -(An) */
uae_u32 REGPARAM2 op_44a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NEG.L (d16,An) */
uae_u32 REGPARAM2 op_44a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEG.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_44b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NEG.L (xxx).W */
uae_u32 REGPARAM2 op_44b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NEG.L (xxx).L */
uae_u32 REGPARAM2 op_44b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ((uae_u32)(0)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(0)) < 0;
int flgn = ((uae_s32)(dst)) < 0;
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(0)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MV2SR.B Dn */
uae_u32 REGPARAM2 op_44c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.B (An) */
uae_u32 REGPARAM2 op_44d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.B (An)+ */
uae_u32 REGPARAM2 op_44d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.B -(An) */
uae_u32 REGPARAM2 op_44e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.B (d16,An) */
uae_u32 REGPARAM2 op_44e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MV2SR.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_44f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MV2SR.B (xxx).W */
uae_u32 REGPARAM2 op_44f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MV2SR.B (xxx).L */
uae_u32 REGPARAM2 op_44f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MV2SR.B (d16,PC) */
uae_u32 REGPARAM2 op_44fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MV2SR.B (d8,PC,Xn) */
uae_u32 REGPARAM2 op_44fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MV2SR.B #<data>.B */
uae_u32 REGPARAM2 op_44fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
MakeSR();
regs.sr &= 0xFF00;
regs.sr |= src & 0xFF;
MakeFromSR();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.B Dn */
uae_u32 REGPARAM2 op_4600_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.B (An) */
uae_u32 REGPARAM2 op_4610_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.B (An)+ */
uae_u32 REGPARAM2 op_4618_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.B -(An) */
uae_u32 REGPARAM2 op_4620_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.B (d16,An) */
uae_u32 REGPARAM2 op_4628_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4630_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NOT.B (xxx).W */
uae_u32 REGPARAM2 op_4638_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.B (xxx).L */
uae_u32 REGPARAM2 op_4639_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(dst)) == 0);
SET_NFLG(((uae_s8)(dst)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* NOT.W Dn */
uae_u32 REGPARAM2 op_4640_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.W (An) */
uae_u32 REGPARAM2 op_4650_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.W (An)+ */
uae_u32 REGPARAM2 op_4658_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.W -(An) */
uae_u32 REGPARAM2 op_4660_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.W (d16,An) */
uae_u32 REGPARAM2 op_4668_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4670_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NOT.W (xxx).W */
uae_u32 REGPARAM2 op_4678_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.W (xxx).L */
uae_u32 REGPARAM2 op_4679_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* NOT.L Dn */
uae_u32 REGPARAM2 op_4680_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_dreg(regs, srcreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.L (An) */
uae_u32 REGPARAM2 op_4690_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.L (An)+ */
uae_u32 REGPARAM2 op_4698_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.L -(An) */
uae_u32 REGPARAM2 op_46a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOT.L (d16,An) */
uae_u32 REGPARAM2 op_46a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_46b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NOT.L (xxx).W */
uae_u32 REGPARAM2 op_46b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NOT.L (xxx).L */
uae_u32 REGPARAM2 op_46b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_u32 dst = ~src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(srca, dst);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MV2SR.W Dn */
uae_u32 REGPARAM2 op_46c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 src = m68k_dreg(regs, srcreg);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.W (An) */
uae_u32 REGPARAM2 op_46d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.W (An)+ */
uae_u32 REGPARAM2 op_46d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.W -(An) */
uae_u32 REGPARAM2 op_46e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MV2SR.W (d16,An) */
uae_u32 REGPARAM2 op_46e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MV2SR.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_46f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MV2SR.W (xxx).W */
uae_u32 REGPARAM2 op_46f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MV2SR.W (xxx).L */
uae_u32 REGPARAM2 op_46f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MV2SR.W (d16,PC) */
uae_u32 REGPARAM2 op_46fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MV2SR.W (d8,PC,Xn) */
uae_u32 REGPARAM2 op_46fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MV2SR.W #<data>.W */
uae_u32 REGPARAM2 op_46fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uae_s16 src = get_iword_mmu040(2);
if(regs.t0) check_t0_trace();
regs.sr = src;
MakeFromSR_T0();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NBCD.B Dn */
uae_u32 REGPARAM2 op_4800_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LINK.L An,#<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4808_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 offs;
offs = get_ilong_mmu040(2);
mmufixup[0].reg = -1;
uaecptr olda;
olda = m68k_areg(regs, 7) - 4;
m68k_areg(regs, 7) = olda;
uae_s32 src = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
m68k_areg(regs, 7) += offs;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(olda, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* NBCD.B (An) */
uae_u32 REGPARAM2 op_4810_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NBCD.B (An)+ */
uae_u32 REGPARAM2 op_4818_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NBCD.B -(An) */
uae_u32 REGPARAM2 op_4820_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NBCD.B (d16,An) */
uae_u32 REGPARAM2 op_4828_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NBCD.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4830_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* NBCD.B (xxx).W */
uae_u32 REGPARAM2 op_4838_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* NBCD.B (xxx).L */
uae_u32 REGPARAM2 op_4839_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = - (src & 0xF0);
uae_u16 newv;
int cflg, tmp_newv;
tmp_newv = newv_hi + newv_lo;
if (newv_lo > 9) newv_lo -= 6;
newv = newv_hi + newv_lo;
cflg = (newv & 0x1F0) > 0x90;
if (cflg) newv -= 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SWAP.W Dn */
uae_u32 REGPARAM2 op_4840_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_dreg(regs, srcreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* BKPTQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4848_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* PEA.L (An) */
uae_u32 REGPARAM2 op_4850_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* PEA.L (d16,An) */
uae_u32 REGPARAM2 op_4868_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* PEA.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4870_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* PEA.L (xxx).W */
uae_u32 REGPARAM2 op_4878_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* PEA.L (xxx).L */
uae_u32 REGPARAM2 op_4879_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* PEA.L (d16,PC) */
uae_u32 REGPARAM2 op_487a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* PEA.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_487b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uaecptr dsta;
dsta = m68k_areg(regs, 7) - 4;
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
m68k_areg(regs, 7) = dsta;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* EXT.W Dn */
uae_u32 REGPARAM2 op_4880_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u16 dst = (uae_s16)(uae_s8)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(dst)) == 0);
SET_NFLG(((uae_s16)(dst)) < 0);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVMLE.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_4890_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_word_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
put_word_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMLE.W #<data>.W,-(An) */
uae_u32 REGPARAM2 op_48a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg) - 0;
}
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (amask) {
srca -= 2;
int predec = movem_index2[amask] != dstreg ? 0 : 2;
put_word_mmu040(srca, m68k_areg(regs, movem_index2[amask]) - predec);
amask = movem_next[amask];
}
while (dmask) {
srca -= 2;
put_word_mmu040(srca, m68k_dreg(regs, movem_index2[dmask]));
dmask = movem_next[dmask];
}
m68k_areg(regs, dstreg) = srca;
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMLE.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_48a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_word_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
put_word_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMLE.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_48b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
m68k_incpci(4);
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_word_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
put_word_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MVMLE.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_48b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_word_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
put_word_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMLE.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_48b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = get_ilong_mmu040(4);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_word_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
put_word_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EXT.L Dn */
uae_u32 REGPARAM2 op_48c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u32 dst = (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_dreg(regs, srcreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVMLE.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_48d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_long_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
put_long_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMLE.L #<data>.W,-(An) */
uae_u32 REGPARAM2 op_48e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg) - 0;
}
uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (amask) {
srca -= 4;
int predec = movem_index2[amask] != dstreg ? 0 : 4;
put_long_mmu040(srca, m68k_areg(regs, movem_index2[amask]) - predec);
amask = movem_next[amask];
}
while (dmask) {
srca -= 4;
put_long_mmu040(srca, m68k_dreg(regs, movem_index2[dmask]));
dmask = movem_next[dmask];
}
m68k_areg(regs, dstreg) = srca;
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMLE.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_48e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_long_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
put_long_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMLE.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_48f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
m68k_incpci(4);
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_long_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
put_long_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MVMLE.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_48f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_long_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
put_long_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMLE.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_48f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = get_ilong_mmu040(4);
}
uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
put_long_mmu040(srca, m68k_dreg(regs, movem_index1[dmask]));
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
put_long_mmu040(srca, m68k_areg(regs, movem_index1[amask]));
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* EXT.B Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_49c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uae_u32 dst = (uae_s32)(uae_s8)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(dst)) == 0);
SET_NFLG(((uae_s32)(dst)) < 0);
m68k_dreg(regs, srcreg) = (dst);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* TST.B Dn */
uae_u32 REGPARAM2 op_4a00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.B (An) */
uae_u32 REGPARAM2 op_4a10_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.B (An)+ */
uae_u32 REGPARAM2 op_4a18_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.B -(An) */
uae_u32 REGPARAM2 op_4a20_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.B (d16,An) */
uae_u32 REGPARAM2 op_4a28_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TST.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4a30_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* TST.B (xxx).W */
uae_u32 REGPARAM2 op_4a38_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TST.B (xxx).L */
uae_u32 REGPARAM2 op_4a39_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TST.B (d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a3a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TST.B (d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a3b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
#endif
/* TST.B #<data>.B */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a3c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s8 src = get_ibyte_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TST.W Dn */
uae_u32 REGPARAM2 op_4a40_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.W An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a48_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* TST.W (An) */
uae_u32 REGPARAM2 op_4a50_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.W (An)+ */
uae_u32 REGPARAM2 op_4a58_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.W -(An) */
uae_u32 REGPARAM2 op_4a60_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.W (d16,An) */
uae_u32 REGPARAM2 op_4a68_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TST.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_4a70_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* TST.W (xxx).W */
uae_u32 REGPARAM2 op_4a78_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TST.W (xxx).L */
uae_u32 REGPARAM2 op_4a79_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TST.W (d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a7a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TST.W (d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a7b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
#endif
/* TST.W #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a7c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TST.L Dn */
uae_u32 REGPARAM2 op_4a80_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.L An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4a88_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_areg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* TST.L (An) */
uae_u32 REGPARAM2 op_4a90_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.L (An)+ */
uae_u32 REGPARAM2 op_4a98_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.L -(An) */
uae_u32 REGPARAM2 op_4aa0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TST.L (d16,An) */
uae_u32 REGPARAM2 op_4aa8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TST.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4ab0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* TST.L (xxx).W */
uae_u32 REGPARAM2 op_4ab8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TST.L (xxx).L */
uae_u32 REGPARAM2 op_4ab9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TST.L (d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4aba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TST.L (d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4abb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
#endif
/* TST.L #<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4abc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 src;
src = get_ilong_mmu040(2);
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TAS.B Dn */
uae_u32 REGPARAM2 op_4ac0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TAS.B (An) */
uae_u32 REGPARAM2 op_4ad0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_lrmw_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TAS.B (An)+ */
uae_u32 REGPARAM2 op_4ad8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_lrmw_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TAS.B -(An) */
uae_u32 REGPARAM2 op_4ae0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_lrmw_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* TAS.B (d16,An) */
uae_u32 REGPARAM2 op_4ae8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_lrmw_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TAS.B (d8,An,Xn) */
uae_u32 REGPARAM2 op_4af0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_lrmw_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* TAS.B (xxx).W */
uae_u32 REGPARAM2 op_4af8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_lrmw_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* TAS.B (xxx).L */
uae_u32 REGPARAM2 op_4af9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_lrmw_byte_mmu040(srca);
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
src |= 0x80;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_lrmw_byte_mmu040(srca, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MULL.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MULL.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c10_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(4);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MULL.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c18_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
m68k_incpci(4);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
cpu_restore_fixup();
}
if (e < 0) {
op_unimpl(opcode);
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MULL.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c20_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
m68k_incpci(4);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
cpu_restore_fixup();
}
if (e < 0) {
op_unimpl(opcode);
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MULL.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c28_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(6);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MULL.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c30_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* MULL.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c38_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(6);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MULL.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c39_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(8);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* MULL.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c3a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(6);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* MULL.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c3b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s32 dst = get_long_mmu040(dsta);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* MULL.L #<data>.W,#<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c3c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uae_s32 dst;
dst = get_ilong_mmu040(4);
m68k_incpci(8);
int e = m68k_mull(opcode, dst, extra);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* DIVL.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c40_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_incpci(4);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* DIVL.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c50_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(4);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* DIVL.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c58_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
m68k_incpci(4);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
cpu_restore_fixup();
}
if (e < 0) {
op_unimpl(opcode);
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* DIVL.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c60_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
m68k_incpci(4);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
cpu_restore_fixup();
}
if (e < 0) {
op_unimpl(opcode);
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* DIVL.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c68_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(6);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* DIVL.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c70_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* DIVL.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c78_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(6);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* DIVL.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c79_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(8);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* DIVL.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c7a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_s32 dst = get_long_mmu040(dsta);
m68k_incpci(6);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* DIVL.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c7b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_s32 dst = get_long_mmu040(dsta);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* DIVL.L #<data>.W,#<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4c7c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(2);
uae_s32 dst;
dst = get_ilong_mmu040(4);
m68k_incpci(8);
int e = m68k_divl(opcode, dst, extra, oldpc);
if (e <= 0) {
if (e < 0) {
op_unimpl(opcode);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* MVMEL.W #<data>.W,(An) */
uae_u32 REGPARAM2 op_4c90_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMEL.W #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_4c98_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
m68k_areg(regs, dstreg) = srca;
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMEL.W #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_4ca8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMEL.W #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_4cb0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
m68k_incpci(4);
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MVMEL.W #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_4cb8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMEL.W #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_4cb9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = get_ilong_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MVMEL.W #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_4cba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_getpci() + 4;
srca += (uae_s32)(uae_s16)get_iword_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMEL.W #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_4cbb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
m68k_incpci(4);
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_mmu040(srca);
srca += 2;
amask = movem_next[amask];
}
mmu040_movem = 0;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MVMEL.L #<data>.W,(An) */
uae_u32 REGPARAM2 op_4cd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMEL.L #<data>.W,(An)+ */
uae_u32 REGPARAM2 op_4cd8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
m68k_areg(regs, dstreg) = srca;
mmu040_movem = 0;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MVMEL.L #<data>.W,(d16,An) */
uae_u32 REGPARAM2 op_4ce8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMEL.L #<data>.W,(d8,An,Xn) */
uae_u32 REGPARAM2 op_4cf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
m68k_incpci(4);
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* MVMEL.L #<data>.W,(xxx).W */
uae_u32 REGPARAM2 op_4cf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = (uae_s32)(uae_s16)get_iword_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMEL.L #<data>.W,(xxx).L */
uae_u32 REGPARAM2 op_4cf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = get_ilong_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
/* MVMEL.L #<data>.W,(d16,PC) */
uae_u32 REGPARAM2 op_4cfa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
srca = m68k_getpci() + 4;
srca += (uae_s32)(uae_s16)get_iword_mmu040(4);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MVMEL.L #<data>.W,(d8,PC,Xn) */
uae_u32 REGPARAM2 op_4cfb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_u16 mask = get_iword_mmu040(2);
uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;
uaecptr srca;
m68k_incpci(4);
if (mmu040_movem) {
srca = mmu040_movem_ea;
} else {
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
}
mmu040_movem = 1;
mmu040_movem_ea = srca;
while (dmask) {
m68k_dreg(regs, movem_index1[dmask]) = get_long_mmu040(srca);
srca += 4;
dmask = movem_next[dmask];
}
while (amask) {
m68k_areg(regs, movem_index1[amask]) = get_long_mmu040(srca);
srca += 4;
amask = movem_next[amask];
}
mmu040_movem = 0;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
/* TRAPQ.L #<data> */
uae_u32 REGPARAM2 op_4e40_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 15);
uae_u32 src = srcreg;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
Exception_cpu(src + 32);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LINK.W An,#<data>.W */
uae_u32 REGPARAM2 op_4e50_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
mmufixup[0].reg = -1;
uaecptr olda;
olda = m68k_areg(regs, 7) - 4;
m68k_areg(regs, 7) = olda;
uae_s32 src = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = (m68k_areg(regs, 7));
m68k_areg(regs, 7) += offs;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(olda, src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* UNLK.L An */
uae_u32 REGPARAM2 op_4e58_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 old = get_long_mmu040(src);
m68k_areg(regs, 7) = src + 4;
m68k_areg(regs, srcreg) = old;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVR2USP.L An */
uae_u32 REGPARAM2 op_4e60_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
uae_s32 src = m68k_areg(regs, srcreg);
regs.usp = src;
if(regs.t0) check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MVUSP2R.L An */
uae_u32 REGPARAM2 op_4e68_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_areg(regs, srcreg) = (regs.usp);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RESET.L */
uae_u32 REGPARAM2 op_4e70_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
bool r = cpureset();
if (r) {
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* NOP.L */
uae_u32 REGPARAM2 op_4e71_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if(regs.t0) check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* STOP.L #<data>.W */
uae_u32 REGPARAM2 op_4e72_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
if (!regs.stopped) {
uae_s16 src = get_iword_mmu040(2);
regs.ir = src;
}
uae_u16 sr = regs.ir;
regs.sr = sr;
checkint();
MakeFromSR_STOP();
do_cycles_stop(4);
m68k_setstopped(1);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* RTE.L */
uae_u32 REGPARAM2 op_4e73_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
uaecptr oldpc = m68k_getpci();
uae_u16 oldsr = regs.sr, newsr;
uae_u32 newpc;
for (;;) {
uaecptr a = m68k_areg(regs, 7);
uae_u16 sr = get_word_mmu040(a);
uae_u32 pc = get_long_mmu040(a + 2);
uae_u16 format = get_word_mmu040(a + 2 + 4);
int frame = format >> 12;
int offset = 8;
newsr = sr; newpc = pc;
if (frame == 0x0) {
m68k_areg(regs, 7) += offset; break; }
else if (frame == 0x1) {
m68k_areg(regs, 7) += offset; }
else if (frame == 0x2) {
m68k_areg(regs, 7) += offset + 4; break; }
else if (frame == 0x3) {
m68k_areg(regs, 7) += offset + 4; break; }
else if (frame == 0x4) {
m68k_areg(regs, 7) += offset + 8; break; }
else if (frame == 0x7) {
m68k_do_rte_mmu040 (a); m68k_areg(regs, 7) += offset + 52; break; }
else {
Exception_cpu(14);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
regs.sr = newsr;
oldsr = newsr;
MakeFromSR_T0();
}
regs.sr = newsr;
MakeFromSR_T0();
if (newpc & 1) {
MakeFromSR();
exception3_read_prefetch_68040bug(opcode, newpc, oldsr);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(newpc);
#ifdef DEBUGGER
branch_stack_pop_rte(oldpc);
#endif
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* RTD.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4e74_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 offs = get_iword_mmu040(2);
uaecptr pca;
pca = m68k_areg(regs, 7);
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
uae_s32 pc = get_long_mmu040(pca);
m68k_areg(regs, 7) += 4;
m68k_areg(regs, 7) += offs;
if (pc & 1) {
m68k_areg(regs, 7) -= 4 + offs;
exception3_read_prefetch_only(opcode, pc);
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(pc);
if(regs.t0) check_t0_trace();
mmufixup[0].reg = -1;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
#endif
/* RTS.L */
uae_u32 REGPARAM2 op_4e75_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
m68k_do_rts_mmu040();
#ifdef DEBUGGER
if (debugmem_trace) {
branch_stack_pop_rts(oldpc);
}
#endif
if (m68k_getpci() & 1) {
uaecptr faultpc = m68k_getpci();
m68k_setpci(oldpc);
m68k_areg(regs, 7) -= 4;
exception3_read_prefetch_only(opcode, faultpc);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* TRAPV.L */
uae_u32 REGPARAM2 op_4e76_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (GET_VFLG()) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RTR.L */
uae_u32 REGPARAM2 op_4e77_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
MakeSR();
uaecptr sra;
sra = m68k_areg(regs, 7);
mmufixup[0].reg = 7 | 0x0;
mmufixup[0].value = m68k_areg(regs, 7);
uae_s16 sr = get_word_mmu040(sra);
m68k_areg(regs, 7) += 2;
uaecptr pca;
pca = m68k_areg(regs, 7);
uae_s32 pc = get_long_mmu040(pca);
m68k_areg(regs, 7) += 4;
mmufixup[0].reg = -1;
if (pc & 1) {
m68k_areg(regs, 7) -= 6;
uae_u16 oldsr = regs.sr;
regs.sr &= 0xFF00; sr &= 0xFF;
regs.sr |= sr;
MakeFromSR();
exception3_read_prefetch_68040bug(opcode, pc, oldsr);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
regs.sr &= 0xFF00; sr &= 0xFF;
regs.sr |= sr;
MakeFromSR();
m68k_setpci(pc);
if(regs.t0) check_t0_trace();
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* MOVEC2.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4e7a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
int regno = (src >> 12) & 15;
uae_u32 *regp = regs.regs + regno;
if (!m68k_movec2(src & 0xFFF, regp)) {
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* MOVE2C.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_4e7b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 src = get_iword_mmu040(2);
int regno = (src >> 12) & 15;
uae_u32 *regp = regs.regs + regno;
if (!m68k_move2c(src & 0xFFF, regp)) {
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if(regs.t0) check_t0_trace();
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* JSR.L (An) */
uae_u32 REGPARAM2 op_4e90_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 2;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* JSR.L (d16,An) */
uae_u32 REGPARAM2 op_4ea8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 4;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* JSR.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4eb0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 0;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 B */
/* JSR.L (xxx).W */
uae_u32 REGPARAM2 op_4eb8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 4;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* JSR.L (xxx).L */
uae_u32 REGPARAM2 op_4eb9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 6;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* JSR.L (d16,PC) */
uae_u32 REGPARAM2 op_4eba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 4;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* JSR.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_4ebb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 0;
put_long_mmu040(m68k_areg(regs, 7) - 4, nextpc);
m68k_areg(regs, 7) -= 4;
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 B */
/* JMP.L (An) */
uae_u32 REGPARAM2 op_4ed0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
if (srca & 1) {
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* JMP.L (d16,An) */
uae_u32 REGPARAM2 op_4ee8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
if (srca & 1) {
count_cycles += 2 * CYCLE_UNIT / 2;
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* JMP.L (d8,An,Xn) */
uae_u32 REGPARAM2 op_4ef0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
if (srca & 1) {
count_cycles += 6 * CYCLE_UNIT / 2;
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 B */
/* JMP.L (xxx).W */
uae_u32 REGPARAM2 op_4ef8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
if (srca & 1) {
count_cycles += 2 * CYCLE_UNIT / 2;
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* JMP.L (xxx).L */
uae_u32 REGPARAM2 op_4ef9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
if (srca & 1) {
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* JMP.L (d16,PC) */
uae_u32 REGPARAM2 op_4efa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
if (srca & 1) {
count_cycles += 2 * CYCLE_UNIT / 2;
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* JMP.L (d8,PC,Xn) */
uae_u32 REGPARAM2 op_4efb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
if (srca & 1) {
count_cycles += 6 * CYCLE_UNIT / 2;
m68k_incpci(2);
exception3_read_prefetch_only(opcode, srca);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_setpci(srca);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 B */
/* ADDQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_5000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.B #<data>,(An) */
uae_u32 REGPARAM2 op_5010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.B #<data>,(An)+ */
uae_u32 REGPARAM2 op_5018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.B #<data>,-(An) */
uae_u32 REGPARAM2 op_5020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.B #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDQ.B #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDQ.B #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDQ.B #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_5040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDAQ.W #<data>,An */
uae_u32 REGPARAM2 op_5048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.W #<data>,(An) */
uae_u32 REGPARAM2 op_5050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.W #<data>,(An)+ */
uae_u32 REGPARAM2 op_5058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.W #<data>,-(An) */
uae_u32 REGPARAM2 op_5060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.W #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDQ.W #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDQ.W #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDQ.W #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_5080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDAQ.L #<data>,An */
uae_u32 REGPARAM2 op_5088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.L #<data>,(An) */
uae_u32 REGPARAM2 op_5090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.L #<data>,(An)+ */
uae_u32 REGPARAM2 op_5098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.L #<data>,-(An) */
uae_u32 REGPARAM2 op_50a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_50a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_50b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDQ.L #<data>,(xxx).W */
uae_u32 REGPARAM2 op_50b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDQ.L #<data>,(xxx).L */
uae_u32 REGPARAM2 op_50b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* Scc.B Dn (T) */
uae_u32 REGPARAM2 op_50c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(0) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (T) */
uae_u32 REGPARAM2 op_50c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(0)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (T) */
uae_u32 REGPARAM2 op_50d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(0) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (T) */
uae_u32 REGPARAM2 op_50d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(0) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (T) */
uae_u32 REGPARAM2 op_50e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(0) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (T) */
uae_u32 REGPARAM2 op_50e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(0) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (T) */
uae_u32 REGPARAM2 op_50f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(0) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (T) */
uae_u32 REGPARAM2 op_50f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(0) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (T) */
uae_u32 REGPARAM2 op_50f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(0) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (T) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_50fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(0)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (T) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_50fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(0)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (T) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_50fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(0)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* SUBQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_5100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.B #<data>,(An) */
uae_u32 REGPARAM2 op_5110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.B #<data>,(An)+ */
uae_u32 REGPARAM2 op_5118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.B #<data>,-(An) */
uae_u32 REGPARAM2 op_5120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.B #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBQ.B #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBQ.B #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBQ.B #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_5140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBAQ.W #<data>,An */
uae_u32 REGPARAM2 op_5148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.W #<data>,(An) */
uae_u32 REGPARAM2 op_5150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.W #<data>,(An)+ */
uae_u32 REGPARAM2 op_5158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.W #<data>,-(An) */
uae_u32 REGPARAM2 op_5160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.W #<data>,(d16,An) */
uae_u32 REGPARAM2 op_5168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBQ.W #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_5170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBQ.W #<data>,(xxx).W */
uae_u32 REGPARAM2 op_5178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBQ.W #<data>,(xxx).L */
uae_u32 REGPARAM2 op_5179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_5180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBAQ.L #<data>,An */
uae_u32 REGPARAM2 op_5188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.L #<data>,(An) */
uae_u32 REGPARAM2 op_5190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.L #<data>,(An)+ */
uae_u32 REGPARAM2 op_5198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.L #<data>,-(An) */
uae_u32 REGPARAM2 op_51a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBQ.L #<data>,(d16,An) */
uae_u32 REGPARAM2 op_51a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBQ.L #<data>,(d8,An,Xn) */
uae_u32 REGPARAM2 op_51b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 src = srcreg;
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBQ.L #<data>,(xxx).W */
uae_u32 REGPARAM2 op_51b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBQ.L #<data>,(xxx).L */
uae_u32 REGPARAM2 op_51b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 src = srcreg;
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* Scc.B Dn (F) */
uae_u32 REGPARAM2 op_51c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(1) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (F) */
uae_u32 REGPARAM2 op_51c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(1)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (F) */
uae_u32 REGPARAM2 op_51d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(1) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (F) */
uae_u32 REGPARAM2 op_51d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(1) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (F) */
uae_u32 REGPARAM2 op_51e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(1) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (F) */
uae_u32 REGPARAM2 op_51e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(1) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (F) */
uae_u32 REGPARAM2 op_51f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(1) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (F) */
uae_u32 REGPARAM2 op_51f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(1) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (F) */
uae_u32 REGPARAM2 op_51f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(1) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (F) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_51fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(1)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (F) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_51fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(1)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (F) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_51fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(1)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (HI) */
uae_u32 REGPARAM2 op_52c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(2) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (HI) */
uae_u32 REGPARAM2 op_52c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(2)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (HI) */
uae_u32 REGPARAM2 op_52d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(2) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (HI) */
uae_u32 REGPARAM2 op_52d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(2) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (HI) */
uae_u32 REGPARAM2 op_52e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(2) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (HI) */
uae_u32 REGPARAM2 op_52e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(2) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (HI) */
uae_u32 REGPARAM2 op_52f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(2) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (HI) */
uae_u32 REGPARAM2 op_52f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(2) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (HI) */
uae_u32 REGPARAM2 op_52f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(2) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (HI) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_52fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(2)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (HI) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_52fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(2)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (HI) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_52fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(2)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (LS) */
uae_u32 REGPARAM2 op_53c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(3) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (LS) */
uae_u32 REGPARAM2 op_53c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(3)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (LS) */
uae_u32 REGPARAM2 op_53d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(3) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (LS) */
uae_u32 REGPARAM2 op_53d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(3) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (LS) */
uae_u32 REGPARAM2 op_53e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(3) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (LS) */
uae_u32 REGPARAM2 op_53e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(3) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (LS) */
uae_u32 REGPARAM2 op_53f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(3) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (LS) */
uae_u32 REGPARAM2 op_53f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(3) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (LS) */
uae_u32 REGPARAM2 op_53f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(3) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (LS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_53fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(3)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (LS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_53fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(3)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (LS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_53fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(3)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (CC) */
uae_u32 REGPARAM2 op_54c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(4) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (CC) */
uae_u32 REGPARAM2 op_54c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(4)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (CC) */
uae_u32 REGPARAM2 op_54d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(4) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (CC) */
uae_u32 REGPARAM2 op_54d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(4) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (CC) */
uae_u32 REGPARAM2 op_54e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(4) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (CC) */
uae_u32 REGPARAM2 op_54e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(4) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (CC) */
uae_u32 REGPARAM2 op_54f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(4) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (CC) */
uae_u32 REGPARAM2 op_54f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(4) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (CC) */
uae_u32 REGPARAM2 op_54f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(4) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (CC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_54fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(4)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (CC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_54fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(4)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (CC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_54fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(4)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (CS) */
uae_u32 REGPARAM2 op_55c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(5) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (CS) */
uae_u32 REGPARAM2 op_55c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(5)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (CS) */
uae_u32 REGPARAM2 op_55d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(5) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (CS) */
uae_u32 REGPARAM2 op_55d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(5) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (CS) */
uae_u32 REGPARAM2 op_55e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(5) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (CS) */
uae_u32 REGPARAM2 op_55e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(5) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (CS) */
uae_u32 REGPARAM2 op_55f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(5) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (CS) */
uae_u32 REGPARAM2 op_55f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(5) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (CS) */
uae_u32 REGPARAM2 op_55f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(5) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (CS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_55fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(5)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (CS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_55fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(5)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (CS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_55fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(5)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (NE) */
uae_u32 REGPARAM2 op_56c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(6) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (NE) */
uae_u32 REGPARAM2 op_56c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(6)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (NE) */
uae_u32 REGPARAM2 op_56d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(6) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (NE) */
uae_u32 REGPARAM2 op_56d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(6) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (NE) */
uae_u32 REGPARAM2 op_56e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(6) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (NE) */
uae_u32 REGPARAM2 op_56e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(6) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (NE) */
uae_u32 REGPARAM2 op_56f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(6) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (NE) */
uae_u32 REGPARAM2 op_56f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(6) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (NE) */
uae_u32 REGPARAM2 op_56f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(6) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (NE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_56fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(6)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (NE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_56fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(6)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (NE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_56fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(6)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (EQ) */
uae_u32 REGPARAM2 op_57c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(7) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (EQ) */
uae_u32 REGPARAM2 op_57c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(7)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (EQ) */
uae_u32 REGPARAM2 op_57d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(7) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (EQ) */
uae_u32 REGPARAM2 op_57d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(7) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (EQ) */
uae_u32 REGPARAM2 op_57e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(7) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (EQ) */
uae_u32 REGPARAM2 op_57e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(7) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (EQ) */
uae_u32 REGPARAM2 op_57f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(7) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (EQ) */
uae_u32 REGPARAM2 op_57f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(7) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (EQ) */
uae_u32 REGPARAM2 op_57f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(7) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (EQ) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_57fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(7)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (EQ) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_57fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(7)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (EQ) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_57fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(7)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (VC) */
uae_u32 REGPARAM2 op_58c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(8) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (VC) */
uae_u32 REGPARAM2 op_58c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(8)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (VC) */
uae_u32 REGPARAM2 op_58d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(8) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (VC) */
uae_u32 REGPARAM2 op_58d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(8) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (VC) */
uae_u32 REGPARAM2 op_58e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(8) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (VC) */
uae_u32 REGPARAM2 op_58e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(8) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (VC) */
uae_u32 REGPARAM2 op_58f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(8) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (VC) */
uae_u32 REGPARAM2 op_58f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(8) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (VC) */
uae_u32 REGPARAM2 op_58f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(8) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (VC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_58fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(8)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (VC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_58fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(8)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (VC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_58fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(8)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (VS) */
uae_u32 REGPARAM2 op_59c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(9) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (VS) */
uae_u32 REGPARAM2 op_59c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(9)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (VS) */
uae_u32 REGPARAM2 op_59d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(9) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (VS) */
uae_u32 REGPARAM2 op_59d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(9) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (VS) */
uae_u32 REGPARAM2 op_59e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(9) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (VS) */
uae_u32 REGPARAM2 op_59e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(9) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (VS) */
uae_u32 REGPARAM2 op_59f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(9) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (VS) */
uae_u32 REGPARAM2 op_59f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(9) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (VS) */
uae_u32 REGPARAM2 op_59f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(9) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (VS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_59fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(9)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (VS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_59fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(9)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (VS) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_59fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(9)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (PL) */
uae_u32 REGPARAM2 op_5ac0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(10) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (PL) */
uae_u32 REGPARAM2 op_5ac8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(10)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (PL) */
uae_u32 REGPARAM2 op_5ad0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(10) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (PL) */
uae_u32 REGPARAM2 op_5ad8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(10) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (PL) */
uae_u32 REGPARAM2 op_5ae0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(10) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (PL) */
uae_u32 REGPARAM2 op_5ae8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(10) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (PL) */
uae_u32 REGPARAM2 op_5af0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(10) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (PL) */
uae_u32 REGPARAM2 op_5af8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(10) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (PL) */
uae_u32 REGPARAM2 op_5af9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(10) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (PL) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5afa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(10)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (PL) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5afb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(10)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (PL) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5afc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(10)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (MI) */
uae_u32 REGPARAM2 op_5bc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(11) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (MI) */
uae_u32 REGPARAM2 op_5bc8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(11)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (MI) */
uae_u32 REGPARAM2 op_5bd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(11) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (MI) */
uae_u32 REGPARAM2 op_5bd8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(11) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (MI) */
uae_u32 REGPARAM2 op_5be0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(11) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (MI) */
uae_u32 REGPARAM2 op_5be8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(11) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (MI) */
uae_u32 REGPARAM2 op_5bf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(11) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (MI) */
uae_u32 REGPARAM2 op_5bf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(11) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (MI) */
uae_u32 REGPARAM2 op_5bf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(11) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (MI) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5bfa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(11)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (MI) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5bfb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(11)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (MI) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5bfc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(11)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (GE) */
uae_u32 REGPARAM2 op_5cc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(12) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (GE) */
uae_u32 REGPARAM2 op_5cc8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(12)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (GE) */
uae_u32 REGPARAM2 op_5cd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(12) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (GE) */
uae_u32 REGPARAM2 op_5cd8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(12) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (GE) */
uae_u32 REGPARAM2 op_5ce0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(12) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (GE) */
uae_u32 REGPARAM2 op_5ce8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(12) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (GE) */
uae_u32 REGPARAM2 op_5cf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(12) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (GE) */
uae_u32 REGPARAM2 op_5cf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(12) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (GE) */
uae_u32 REGPARAM2 op_5cf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(12) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (GE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5cfa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(12)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (GE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5cfb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(12)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (GE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5cfc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(12)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (LT) */
uae_u32 REGPARAM2 op_5dc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(13) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (LT) */
uae_u32 REGPARAM2 op_5dc8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(13)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (LT) */
uae_u32 REGPARAM2 op_5dd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(13) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (LT) */
uae_u32 REGPARAM2 op_5dd8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(13) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (LT) */
uae_u32 REGPARAM2 op_5de0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(13) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (LT) */
uae_u32 REGPARAM2 op_5de8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(13) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (LT) */
uae_u32 REGPARAM2 op_5df0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(13) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (LT) */
uae_u32 REGPARAM2 op_5df8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(13) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (LT) */
uae_u32 REGPARAM2 op_5df9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(13) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (LT) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5dfa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(13)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (LT) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5dfb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(13)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (LT) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5dfc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(13)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (GT) */
uae_u32 REGPARAM2 op_5ec0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(14) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (GT) */
uae_u32 REGPARAM2 op_5ec8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(14)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (GT) */
uae_u32 REGPARAM2 op_5ed0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(14) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (GT) */
uae_u32 REGPARAM2 op_5ed8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(14) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (GT) */
uae_u32 REGPARAM2 op_5ee0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(14) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (GT) */
uae_u32 REGPARAM2 op_5ee8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(14) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (GT) */
uae_u32 REGPARAM2 op_5ef0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(14) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (GT) */
uae_u32 REGPARAM2 op_5ef8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(14) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (GT) */
uae_u32 REGPARAM2 op_5ef9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(14) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (GT) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5efa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(14)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (GT) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5efb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(14)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (GT) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5efc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(14)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Scc.B Dn (LE) */
uae_u32 REGPARAM2 op_5fc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
int val = cctrue(15) ? 0xff : 0x00;
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff);
count_cycles += ((val ? 2 : 0)) * CYCLE_UNIT / 2;
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DBcc.W Dn,#<data>.W (LE) */
uae_u32 REGPARAM2 op_5fc8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 offs = get_iword_mmu040(2);
uaecptr oldpc = m68k_getpci();
if (offs & 1) {
exception3_read_prefetch(opcode, oldpc + (uae_s32)offs + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (!cctrue(15)) {
m68k_incpci((uae_s32)offs + 2);
m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src - 1)) & 0xffff);
if (src) {
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
count_cycles += 6 * CYCLE_UNIT / 2;
}
m68k_setpci(oldpc + 4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* Scc.B (An) (LE) */
uae_u32 REGPARAM2 op_5fd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
int val = cctrue(15) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (An)+ (LE) */
uae_u32 REGPARAM2 op_5fd8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
int val = cctrue(15) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B -(An) (LE) */
uae_u32 REGPARAM2 op_5fe0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) = srca;
int val = cctrue(15) ? 0xff : 0x00;
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* Scc.B (d16,An) (LE) */
uae_u32 REGPARAM2 op_5fe8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(15) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (d8,An,Xn) (LE) */
uae_u32 REGPARAM2 op_5ff0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
int val = cctrue(15) ? 0xff : 0x00;
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* Scc.B (xxx).W (LE) */
uae_u32 REGPARAM2 op_5ff8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
int val = cctrue(15) ? 0xff : 0x00;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* Scc.B (xxx).L (LE) */
uae_u32 REGPARAM2 op_5ff9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr srca;
srca = get_ilong_mmu040(2);
int val = cctrue(15) ? 0xff : 0x00;
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(srca, val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* TRAPcc.L #<data>.W (LE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5ffa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 dummy = get_iword_mmu040(2);
m68k_incpci(4);
if (cctrue(15)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* TRAPcc.L #<data>.L (LE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5ffb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 dummy;
dummy = get_ilong_mmu040(2);
m68k_incpci(6);
if (cctrue(15)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* TRAPcc.L (LE) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_5ffc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
m68k_incpci(2);
if (cctrue(15)) {
Exception_cpu(7);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
#endif
/* Bcc.W #<data>.W (T) */
uae_u32 REGPARAM2 op_6000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(0)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (T) */
uae_u32 REGPARAM2 op_6001_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(0)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (T) */
uae_u32 REGPARAM2 op_60ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(0)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* BSR.W #<data>.W */
uae_u32 REGPARAM2 op_6100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 s;
uae_s16 src = get_iword_mmu040(2);
s = (uae_s32)src + 2;
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 4;
if (s & 1) {
exception3_read_prefetch(opcode, oldpc + s);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_do_bsr_mmu040(nextpc, s);
#ifdef DEBUGGER
if (debugmem_trace) {
branch_stack_push(oldpc, nextpc);
}
#endif
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BSRQ.B #<data> */
uae_u32 REGPARAM2 op_6101_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uae_s32 s;
uae_u32 src = srcreg;
s = (uae_s32)src + 2;
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 2;
if (s & 1) {
exception3_read_prefetch(opcode, oldpc + s);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_do_bsr_mmu040(nextpc, s);
#ifdef DEBUGGER
if (debugmem_trace) {
branch_stack_push(oldpc, nextpc);
}
#endif
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* BSR.L #<data>.L */
uae_u32 REGPARAM2 op_61ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s32 s;
uae_s32 src;
src = get_ilong_mmu040(2);
s = (uae_s32)src + 2;
uaecptr oldpc = m68k_getpci();
uaecptr nextpc = oldpc + 6;
if (s & 1) {
exception3_read_prefetch(opcode, oldpc + s);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_do_bsr_mmu040(nextpc, s);
#ifdef DEBUGGER
if (debugmem_trace) {
branch_stack_push(oldpc, nextpc);
}
#endif
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (HI) */
uae_u32 REGPARAM2 op_6200_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(2)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (HI) */
uae_u32 REGPARAM2 op_6201_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(2)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (HI) */
uae_u32 REGPARAM2 op_62ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(2)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (LS) */
uae_u32 REGPARAM2 op_6300_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(3)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (LS) */
uae_u32 REGPARAM2 op_6301_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(3)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (LS) */
uae_u32 REGPARAM2 op_63ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(3)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (CC) */
uae_u32 REGPARAM2 op_6400_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(4)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (CC) */
uae_u32 REGPARAM2 op_6401_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(4)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (CC) */
uae_u32 REGPARAM2 op_64ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(4)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (CS) */
uae_u32 REGPARAM2 op_6500_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(5)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (CS) */
uae_u32 REGPARAM2 op_6501_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(5)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (CS) */
uae_u32 REGPARAM2 op_65ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(5)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (NE) */
uae_u32 REGPARAM2 op_6600_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(6)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (NE) */
uae_u32 REGPARAM2 op_6601_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(6)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (NE) */
uae_u32 REGPARAM2 op_66ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(6)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (EQ) */
uae_u32 REGPARAM2 op_6700_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(7)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (EQ) */
uae_u32 REGPARAM2 op_6701_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(7)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (EQ) */
uae_u32 REGPARAM2 op_67ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(7)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (VC) */
uae_u32 REGPARAM2 op_6800_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(8)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (VC) */
uae_u32 REGPARAM2 op_6801_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(8)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (VC) */
uae_u32 REGPARAM2 op_68ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(8)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (VS) */
uae_u32 REGPARAM2 op_6900_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(9)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (VS) */
uae_u32 REGPARAM2 op_6901_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(9)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (VS) */
uae_u32 REGPARAM2 op_69ff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(9)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (PL) */
uae_u32 REGPARAM2 op_6a00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(10)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (PL) */
uae_u32 REGPARAM2 op_6a01_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(10)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (PL) */
uae_u32 REGPARAM2 op_6aff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(10)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (MI) */
uae_u32 REGPARAM2 op_6b00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(11)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (MI) */
uae_u32 REGPARAM2 op_6b01_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(11)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (MI) */
uae_u32 REGPARAM2 op_6bff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(11)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (GE) */
uae_u32 REGPARAM2 op_6c00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(12)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (GE) */
uae_u32 REGPARAM2 op_6c01_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(12)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (GE) */
uae_u32 REGPARAM2 op_6cff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(12)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (LT) */
uae_u32 REGPARAM2 op_6d00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(13)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (LT) */
uae_u32 REGPARAM2 op_6d01_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(13)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (LT) */
uae_u32 REGPARAM2 op_6dff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(13)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (GT) */
uae_u32 REGPARAM2 op_6e00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(14)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (GT) */
uae_u32 REGPARAM2 op_6e01_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(14)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (GT) */
uae_u32 REGPARAM2 op_6eff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(14)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* Bcc.W #<data>.W (LE) */
uae_u32 REGPARAM2 op_6f00_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s16 src = get_iword_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(15)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 B */
/* BccQ.B #<data> (LE) */
uae_u32 REGPARAM2 op_6f01_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uaecptr oldpc = m68k_getpci();
uae_u32 src = srcreg;
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(15)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 B */
/* Bcc.L #<data>.L (LE) */
uae_u32 REGPARAM2 op_6fff_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr oldpc = m68k_getpci();
uae_s32 src;
src = get_ilong_mmu040(2);
if (src & 1) {
exception3_read_prefetch(opcode, m68k_getpci() + (uae_s32)src + 2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (cctrue(15)) {
m68k_incpci((uae_s32)src + 2);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 B */
/* MOVEQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_7000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (uae_s32)(uae_s8)(real_opcode & 255);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_u32 src = srcreg;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B Dn,Dn */
uae_u32 REGPARAM2 op_8000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B (An),Dn */
uae_u32 REGPARAM2 op_8010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B (An)+,Dn */
uae_u32 REGPARAM2 op_8018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B -(An),Dn */
uae_u32 REGPARAM2 op_8020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B (d16,An),Dn */
uae_u32 REGPARAM2 op_8028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_8030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_8038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_8039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_803a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_803b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_803c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W Dn,Dn */
uae_u32 REGPARAM2 op_8040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W (An),Dn */
uae_u32 REGPARAM2 op_8050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W (An)+,Dn */
uae_u32 REGPARAM2 op_8058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W -(An),Dn */
uae_u32 REGPARAM2 op_8060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W (d16,An),Dn */
uae_u32 REGPARAM2 op_8068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_8070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_8078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_8079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_807a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_807b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_807c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L Dn,Dn */
uae_u32 REGPARAM2 op_8080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L (An),Dn */
uae_u32 REGPARAM2 op_8090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L (An)+,Dn */
uae_u32 REGPARAM2 op_8098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L -(An),Dn */
uae_u32 REGPARAM2 op_80a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L (d16,An),Dn */
uae_u32 REGPARAM2 op_80a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_80b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_80b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_80b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* OR.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_80ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_80bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_80bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* DIVU.W Dn,Dn */
uae_u32 REGPARAM2 op_80c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVU.W (An),Dn */
uae_u32 REGPARAM2 op_80d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVU.W (An)+,Dn */
uae_u32 REGPARAM2 op_80d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVU.W -(An),Dn */
uae_u32 REGPARAM2 op_80e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVU.W (d16,An),Dn */
uae_u32 REGPARAM2 op_80e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* DIVU.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_80f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(0);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* DIVU.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_80f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* DIVU.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_80f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(6);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* DIVU.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_80fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* DIVU.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_80fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(0);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* DIVU.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_80fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(0, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;
uae_u32 rem = (uae_u32)dst % (uae_u32)(uae_u16)src;
if (newv > 0xffff) {
setdivuflags((uae_u32)dst, (uae_u16)src);
} else {
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SBCD.B Dn,Dn */
uae_u32 REGPARAM2 op_8100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
uae_u16 newv, tmp_newv;
int bcd = 0;
newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SBCD.B -(An),-(An) */
uae_u32 REGPARAM2 op_8108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);
uae_u16 newv, tmp_newv;
int bcd = 0;
newv = tmp_newv = newv_hi + newv_lo;
if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };
if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG() ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }
SET_CFLG((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG() ? 1 : 0)) & 0x300) > 0xFF);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B Dn,(An) */
uae_u32 REGPARAM2 op_8110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_8118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B Dn,-(An) */
uae_u32 REGPARAM2 op_8120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_8128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_8130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_8138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_8139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* PACK.L Dn,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_8140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_u16 val = m68k_dreg(regs, srcreg) + get_iword_mmu040(2);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* PACK.L -(An),-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_8148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_u16 val;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) -= 2;
val = (uae_u16)(get_word_mmu040(m68k_areg(regs, srcreg)));
val += get_iword_mmu040(2);
m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* OR.W Dn,(An) */
uae_u32 REGPARAM2 op_8150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W Dn,(An)+ */
uae_u32 REGPARAM2 op_8158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W Dn,-(An) */
uae_u32 REGPARAM2 op_8160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_8168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_8170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_8178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_8179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* UNPK.L Dn,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_8180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_u16 val = m68k_dreg(regs, srcreg);
val = ((val << 4) & 0xf00) | (val & 0xf);
val += get_iword_mmu040(2);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* UNPK.L -(An),-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_8188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_u16 val;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];
val = (uae_u16)(get_byte_mmu040(m68k_areg(regs, srcreg)) & 0xff);
val = (((val << 4) & 0xf00) | (val & 0xf)) + get_iword_mmu040(2);
m68k_areg(regs, dstreg) -= 2;
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(m68k_areg(regs, dstreg), val);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* OR.L Dn,(An) */
uae_u32 REGPARAM2 op_8190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L Dn,(An)+ */
uae_u32 REGPARAM2 op_8198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L Dn,-(An) */
uae_u32 REGPARAM2 op_81a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* OR.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_81a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_81b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* OR.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_81b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* OR.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_81b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src |= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* DIVS.W Dn,Dn */
uae_u32 REGPARAM2 op_81c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVS.W (An),Dn */
uae_u32 REGPARAM2 op_81d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVS.W (An)+,Dn */
uae_u32 REGPARAM2 op_81d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVS.W -(An),Dn */
uae_u32 REGPARAM2 op_81e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(2);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* DIVS.W (d16,An),Dn */
uae_u32 REGPARAM2 op_81e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* DIVS.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_81f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(0);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* DIVS.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_81f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* DIVS.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_81f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(6);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* DIVS.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_81fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* DIVS.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_81fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(0);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* DIVS.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_81fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
if (src == 0) {
divbyzero_special(1, dst);
m68k_incpci(4);
Exception_cpu(5);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
if (dst == 0x80000000 && src == -1) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;
uae_u16 rem = (uae_s32)dst % (uae_s32)(uae_s16)src;
if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {
setdivsflags((uae_s32)dst, (uae_s16)src);
} else {
if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_NFLG(((uae_s16)(newv)) < 0);
newv = (newv & 0xffff) | ((uae_u32)rem << 16);
m68k_dreg(regs, dstreg) = (newv);
}
}
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B Dn,Dn */
uae_u32 REGPARAM2 op_9000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B (An),Dn */
uae_u32 REGPARAM2 op_9010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B (An)+,Dn */
uae_u32 REGPARAM2 op_9018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B -(An),Dn */
uae_u32 REGPARAM2 op_9020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B (d16,An),Dn */
uae_u32 REGPARAM2 op_9028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_9030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_9038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_9039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_903a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_903b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_903c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W Dn,Dn */
uae_u32 REGPARAM2 op_9040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W An,Dn */
uae_u32 REGPARAM2 op_9048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W (An),Dn */
uae_u32 REGPARAM2 op_9050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W (An)+,Dn */
uae_u32 REGPARAM2 op_9058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W -(An),Dn */
uae_u32 REGPARAM2 op_9060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W (d16,An),Dn */
uae_u32 REGPARAM2 op_9068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_9070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_9078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_9079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_907a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_907b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_907c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.L Dn,Dn */
uae_u32 REGPARAM2 op_9080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L An,Dn */
uae_u32 REGPARAM2 op_9088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L (An),Dn */
uae_u32 REGPARAM2 op_9090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L (An)+,Dn */
uae_u32 REGPARAM2 op_9098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L -(An),Dn */
uae_u32 REGPARAM2 op_90a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L (d16,An),Dn */
uae_u32 REGPARAM2 op_90a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_90b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_90b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_90b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUB.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_90ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_90bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_90bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBA.W Dn,An */
uae_u32 REGPARAM2 op_90c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.W An,An */
uae_u32 REGPARAM2 op_90c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.W (An),An */
uae_u32 REGPARAM2 op_90d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.W (An)+,An */
uae_u32 REGPARAM2 op_90d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.W -(An),An */
uae_u32 REGPARAM2 op_90e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.W (d16,An),An */
uae_u32 REGPARAM2 op_90e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_90f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBA.W (xxx).W,An */
uae_u32 REGPARAM2 op_90f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBA.W (xxx).L,An */
uae_u32 REGPARAM2 op_90f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBA.W (d16,PC),An */
uae_u32 REGPARAM2 op_90fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_90fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBA.W #<data>.W,An */
uae_u32 REGPARAM2 op_90fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBX.B Dn,Dn */
uae_u32 REGPARAM2 op_9100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBX.B -(An),-(An) */
uae_u32 REGPARAM2 op_9108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B Dn,(An) */
uae_u32 REGPARAM2 op_9110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B Dn,(An)+ */
uae_u32 REGPARAM2 op_9118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B Dn,-(An) */
uae_u32 REGPARAM2 op_9120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_9128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_9130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_9138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_9139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBX.W Dn,Dn */
uae_u32 REGPARAM2 op_9140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBX.W -(An),-(An) */
uae_u32 REGPARAM2 op_9148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W Dn,(An) */
uae_u32 REGPARAM2 op_9150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W Dn,(An)+ */
uae_u32 REGPARAM2 op_9158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W Dn,-(An) */
uae_u32 REGPARAM2 op_9160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_9168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_9170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_9178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_9179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBX.L Dn,Dn */
uae_u32 REGPARAM2 op_9180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBX.L -(An),-(An) */
uae_u32 REGPARAM2 op_9188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L Dn,(An) */
uae_u32 REGPARAM2 op_9190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L Dn,(An)+ */
uae_u32 REGPARAM2 op_9198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L Dn,-(An) */
uae_u32 REGPARAM2 op_91a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUB.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_91a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_91b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUB.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_91b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUB.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_91b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBA.L Dn,An */
uae_u32 REGPARAM2 op_91c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.L An,An */
uae_u32 REGPARAM2 op_91c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.L (An),An */
uae_u32 REGPARAM2 op_91d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.L (An)+,An */
uae_u32 REGPARAM2 op_91d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.L -(An),An */
uae_u32 REGPARAM2 op_91e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* SUBA.L (d16,An),An */
uae_u32 REGPARAM2 op_91e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_91f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBA.L (xxx).W,An */
uae_u32 REGPARAM2 op_91f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBA.L (xxx).L,An */
uae_u32 REGPARAM2 op_91f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* SUBA.L (d16,PC),An */
uae_u32 REGPARAM2 op_91fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* SUBA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_91fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* SUBA.L #<data>.L,An */
uae_u32 REGPARAM2 op_91fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst - src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.B Dn,Dn */
uae_u32 REGPARAM2 op_b000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.B (An),Dn */
uae_u32 REGPARAM2 op_b010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.B (An)+,Dn */
uae_u32 REGPARAM2 op_b018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.B -(An),Dn */
uae_u32 REGPARAM2 op_b020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.B (d16,An),Dn */
uae_u32 REGPARAM2 op_b028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMP.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_b038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_b039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_b03a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b03b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMP.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_b03c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W Dn,Dn */
uae_u32 REGPARAM2 op_b040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.W An,Dn */
uae_u32 REGPARAM2 op_b048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.W (An),Dn */
uae_u32 REGPARAM2 op_b050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.W (An)+,Dn */
uae_u32 REGPARAM2 op_b058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.W -(An),Dn */
uae_u32 REGPARAM2 op_b060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.W (d16,An),Dn */
uae_u32 REGPARAM2 op_b068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMP.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_b078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_b079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_b07a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b07b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMP.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_b07c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.L Dn,Dn */
uae_u32 REGPARAM2 op_b080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.L An,Dn */
uae_u32 REGPARAM2 op_b088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.L (An),Dn */
uae_u32 REGPARAM2 op_b090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.L (An)+,Dn */
uae_u32 REGPARAM2 op_b098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.L -(An),Dn */
uae_u32 REGPARAM2 op_b0a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMP.L (d16,An),Dn */
uae_u32 REGPARAM2 op_b0a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_b0b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMP.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_b0b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_b0b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMP.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_b0ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMP.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_b0bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMP.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_b0bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMPA.W Dn,An */
uae_u32 REGPARAM2 op_b0c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.W An,An */
uae_u32 REGPARAM2 op_b0c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.W (An),An */
uae_u32 REGPARAM2 op_b0d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.W (An)+,An */
uae_u32 REGPARAM2 op_b0d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.W -(An),An */
uae_u32 REGPARAM2 op_b0e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.W (d16,An),An */
uae_u32 REGPARAM2 op_b0e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMPA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_b0f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMPA.W (xxx).W,An */
uae_u32 REGPARAM2 op_b0f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMPA.W (xxx).L,An */
uae_u32 REGPARAM2 op_b0f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMPA.W (d16,PC),An */
uae_u32 REGPARAM2 op_b0fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMPA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_b0fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMPA.W #<data>.W,An */
uae_u32 REGPARAM2 op_b0fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B Dn,Dn */
uae_u32 REGPARAM2 op_b100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPM.B (An)+,(An)+ */
uae_u32 REGPARAM2 op_b108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) - ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u8)(src)) > ((uae_u8)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.B Dn,(An) */
uae_u32 REGPARAM2 op_b110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.B Dn,(An)+ */
uae_u32 REGPARAM2 op_b118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.B Dn,-(An) */
uae_u32 REGPARAM2 op_b120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_b128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* EOR.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_b138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_b139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.W Dn,Dn */
uae_u32 REGPARAM2 op_b140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPM.W (An)+,(An)+ */
uae_u32 REGPARAM2 op_b148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) - ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.W Dn,(An) */
uae_u32 REGPARAM2 op_b150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.W Dn,(An)+ */
uae_u32 REGPARAM2 op_b158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.W Dn,-(An) */
uae_u32 REGPARAM2 op_b160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_b168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* EOR.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_b178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_b179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EOR.L Dn,Dn */
uae_u32 REGPARAM2 op_b180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPM.L (An)+,(An)+ */
uae_u32 REGPARAM2 op_b188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.L Dn,(An) */
uae_u32 REGPARAM2 op_b190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.L Dn,(An)+ */
uae_u32 REGPARAM2 op_b198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.L Dn,-(An) */
uae_u32 REGPARAM2 op_b1a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EOR.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_b1a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_b1b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* EOR.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_b1b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* EOR.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_b1b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src ^= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMPA.L Dn,An */
uae_u32 REGPARAM2 op_b1c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.L An,An */
uae_u32 REGPARAM2 op_b1c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.L (An),An */
uae_u32 REGPARAM2 op_b1d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.L (An)+,An */
uae_u32 REGPARAM2 op_b1d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.L -(An),An */
uae_u32 REGPARAM2 op_b1e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* CMPA.L (d16,An),An */
uae_u32 REGPARAM2 op_b1e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMPA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_b1f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMPA.L (xxx).W,An */
uae_u32 REGPARAM2 op_b1f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMPA.L (xxx).L,An */
uae_u32 REGPARAM2 op_b1f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* CMPA.L (d16,PC),An */
uae_u32 REGPARAM2 op_b1fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* CMPA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_b1fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* CMPA.L #<data>.L,An */
uae_u32 REGPARAM2 op_b1fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) - ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs != flgo) && (flgn != flgo));
SET_CFLG(((uae_u32)(src)) > ((uae_u32)(dst)));
SET_NFLG(flgn != 0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.B Dn,Dn */
uae_u32 REGPARAM2 op_c000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B (An),Dn */
uae_u32 REGPARAM2 op_c010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B (An)+,Dn */
uae_u32 REGPARAM2 op_c018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B -(An),Dn */
uae_u32 REGPARAM2 op_c020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B (d16,An),Dn */
uae_u32 REGPARAM2 op_c028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_c038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_c039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_c03a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c03b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_c03c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W Dn,Dn */
uae_u32 REGPARAM2 op_c040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W (An),Dn */
uae_u32 REGPARAM2 op_c050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W (An)+,Dn */
uae_u32 REGPARAM2 op_c058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W -(An),Dn */
uae_u32 REGPARAM2 op_c060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c07a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c07b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c07c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L Dn,Dn */
uae_u32 REGPARAM2 op_c080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L (An),Dn */
uae_u32 REGPARAM2 op_c090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L (An)+,Dn */
uae_u32 REGPARAM2 op_c098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L -(An),Dn */
uae_u32 REGPARAM2 op_c0a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L (d16,An),Dn */
uae_u32 REGPARAM2 op_c0a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c0b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_c0b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_c0b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* AND.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_c0ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c0bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_c0bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MULU.W Dn,Dn */
uae_u32 REGPARAM2 op_c0c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULU.W (An),Dn */
uae_u32 REGPARAM2 op_c0d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULU.W (An)+,Dn */
uae_u32 REGPARAM2 op_c0d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULU.W -(An),Dn */
uae_u32 REGPARAM2 op_c0e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULU.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c0e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MULU.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c0f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MULU.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c0f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MULU.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c0f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MULU.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c0fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MULU.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c0fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MULU.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c0fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ABCD.B Dn,Dn */
uae_u32 REGPARAM2 op_c100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
uae_u16 newv, tmp_newv;
int cflg;
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
cflg = (newv & 0x3F0) > 0x90;
if (cflg) newv += 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ABCD.B -(An),-(An) */
uae_u32 REGPARAM2 op_c108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG() ? 1 : 0);
uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);
uae_u16 newv, tmp_newv;
int cflg;
newv = tmp_newv = newv_hi + newv_lo;if (newv_lo > 9) { newv += 6; }
cflg = (newv & 0x3F0) > 0x90;
if (cflg) newv += 0x60;
SET_CFLG(cflg);
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B Dn,(An) */
uae_u32 REGPARAM2 op_c110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B Dn,(An)+ */
uae_u32 REGPARAM2 op_c118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B Dn,-(An) */
uae_u32 REGPARAM2 op_c120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_c128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_c138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_c139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s8)(src)) == 0);
SET_NFLG(((uae_s8)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EXG.L Dn,Dn */
uae_u32 REGPARAM2 op_c140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
m68k_dreg(regs, srcreg) = (dst);
m68k_dreg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* EXG.L An,An */
uae_u32 REGPARAM2 op_c148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
m68k_areg(regs, srcreg) = (dst);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W Dn,(An) */
uae_u32 REGPARAM2 op_c150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W Dn,(An)+ */
uae_u32 REGPARAM2 op_c158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W Dn,-(An) */
uae_u32 REGPARAM2 op_c160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_c168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_c178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_c179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(src)) == 0);
SET_NFLG(((uae_s16)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* EXG.L Dn,An */
uae_u32 REGPARAM2 op_c188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
m68k_dreg(regs, srcreg) = (dst);
m68k_areg(regs, dstreg) = (src);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L Dn,(An) */
uae_u32 REGPARAM2 op_c190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L Dn,(An)+ */
uae_u32 REGPARAM2 op_c198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L Dn,-(An) */
uae_u32 REGPARAM2 op_c1a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* AND.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_c1a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_c1b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* AND.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_c1b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* AND.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_c1b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
src &= dst;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(src)) == 0);
SET_NFLG(((uae_s32)(src)) < 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, src);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MULS.W Dn,Dn */
uae_u32 REGPARAM2 op_c1c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULS.W (An),Dn */
uae_u32 REGPARAM2 op_c1d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULS.W (An)+,Dn */
uae_u32 REGPARAM2 op_c1d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULS.W -(An),Dn */
uae_u32 REGPARAM2 op_c1e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* MULS.W (d16,An),Dn */
uae_u32 REGPARAM2 op_c1e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MULS.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_c1f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MULS.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_c1f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MULS.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_c1f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* MULS.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_c1fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* MULS.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_c1fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* MULS.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_c1fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;
CLEAR_CZNV();
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B Dn,Dn */
uae_u32 REGPARAM2 op_d000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B (An),Dn */
uae_u32 REGPARAM2 op_d010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B (An)+,Dn */
uae_u32 REGPARAM2 op_d018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) += areg_byteinc[srcreg];
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B -(An),Dn */
uae_u32 REGPARAM2 op_d020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s8 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B (d16,An),Dn */
uae_u32 REGPARAM2 op_d028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.B (xxx).W,Dn */
uae_u32 REGPARAM2 op_d038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B (xxx).L,Dn */
uae_u32 REGPARAM2 op_d039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.B (d16,PC),Dn */
uae_u32 REGPARAM2 op_d03a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d03b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s8 src = get_byte_mmu040(srca);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.B #<data>.B,Dn */
uae_u32 REGPARAM2 op_d03c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = get_ibyte_mmu040(2);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W Dn,Dn */
uae_u32 REGPARAM2 op_d040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W An,Dn */
uae_u32 REGPARAM2 op_d048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W (An),Dn */
uae_u32 REGPARAM2 op_d050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W (An)+,Dn */
uae_u32 REGPARAM2 op_d058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W -(An),Dn */
uae_u32 REGPARAM2 op_d060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s16 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W (d16,An),Dn */
uae_u32 REGPARAM2 op_d068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.W (xxx).W,Dn */
uae_u32 REGPARAM2 op_d078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W (xxx).L,Dn */
uae_u32 REGPARAM2 op_d079_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.W (d16,PC),Dn */
uae_u32 REGPARAM2 op_d07a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d07b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.W #<data>.W,Dn */
uae_u32 REGPARAM2 op_d07c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.L Dn,Dn */
uae_u32 REGPARAM2 op_d080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L An,Dn */
uae_u32 REGPARAM2 op_d088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L (An),Dn */
uae_u32 REGPARAM2 op_d090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L (An)+,Dn */
uae_u32 REGPARAM2 op_d098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L -(An),Dn */
uae_u32 REGPARAM2 op_d0a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_dreg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L (d16,An),Dn */
uae_u32 REGPARAM2 op_d0a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.L (d8,An,Xn),Dn */
uae_u32 REGPARAM2 op_d0b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.L (xxx).W,Dn */
uae_u32 REGPARAM2 op_d0b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.L (xxx).L,Dn */
uae_u32 REGPARAM2 op_d0b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADD.L (d16,PC),Dn */
uae_u32 REGPARAM2 op_d0ba_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.L (d8,PC,Xn),Dn */
uae_u32 REGPARAM2 op_d0bb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.L #<data>.L,Dn */
uae_u32 REGPARAM2 op_d0bc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDA.W Dn,An */
uae_u32 REGPARAM2 op_d0c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.W An,An */
uae_u32 REGPARAM2 op_d0c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.W (An),An */
uae_u32 REGPARAM2 op_d0d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.W (An)+,An */
uae_u32 REGPARAM2 op_d0d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) += 2;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.W -(An),An */
uae_u32 REGPARAM2 op_d0e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.W (d16,An),An */
uae_u32 REGPARAM2 op_d0e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDA.W (d8,An,Xn),An */
uae_u32 REGPARAM2 op_d0f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDA.W (xxx).W,An */
uae_u32 REGPARAM2 op_d0f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDA.W (xxx).L,An */
uae_u32 REGPARAM2 op_d0f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDA.W (d16,PC),An */
uae_u32 REGPARAM2 op_d0fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDA.W (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_d0fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s16 src = get_word_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDA.W #<data>.W,An */
uae_u32 REGPARAM2 op_d0fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = get_iword_mmu040(2);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDX.B Dn,Dn */
uae_u32 REGPARAM2 op_d100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uae_s8 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDX.B -(An),-(An) */
uae_u32 REGPARAM2 op_d108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg];
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s8 src = get_byte_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s8)(newv)) == 0));
SET_NFLG(((uae_s8)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B Dn,(An) */
uae_u32 REGPARAM2 op_d110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B Dn,(An)+ */
uae_u32 REGPARAM2 op_d118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) += areg_byteinc[dstreg];
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B Dn,-(An) */
uae_u32 REGPARAM2 op_d120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg];
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s8 dst = get_byte_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.B Dn,(d16,An) */
uae_u32 REGPARAM2 op_d128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.B Dn,(xxx).W */
uae_u32 REGPARAM2 op_d138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.B Dn,(xxx).L */
uae_u32 REGPARAM2 op_d139_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s8 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s8 dst = get_byte_mmu040(dsta);
uae_u32 newv = ((uae_u8)(dst)) + ((uae_u8)(src));
int flgs = ((uae_s8)(src)) < 0;
int flgo = ((uae_s8)(dst)) < 0;
int flgn = ((uae_s8)(newv)) < 0;
SET_ZFLG(((uae_s8)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u8)(~dst)) < ((uae_u8)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_byte_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDX.W Dn,Dn */
uae_u32 REGPARAM2 op_d140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uae_s16 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDX.W -(An),-(An) */
uae_u32 REGPARAM2 op_d148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 src = get_word_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));
SET_NFLG(((uae_s16)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W Dn,(An) */
uae_u32 REGPARAM2 op_d150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W Dn,(An)+ */
uae_u32 REGPARAM2 op_d158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) += 2;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W Dn,-(An) */
uae_u32 REGPARAM2 op_d160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 2;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s16 dst = get_word_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.W Dn,(d16,An) */
uae_u32 REGPARAM2 op_d168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.W Dn,(xxx).W */
uae_u32 REGPARAM2 op_d178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.W Dn,(xxx).L */
uae_u32 REGPARAM2 op_d179_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s16 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s16 dst = get_word_mmu040(dsta);
uae_u32 newv = ((uae_u16)(dst)) + ((uae_u16)(src));
int flgs = ((uae_s16)(src)) < 0;
int flgo = ((uae_s16)(dst)) < 0;
int flgn = ((uae_s16)(newv)) < 0;
SET_ZFLG(((uae_s16)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDX.L Dn,Dn */
uae_u32 REGPARAM2 op_d180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_dreg(regs, dstreg);
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_dreg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDX.L -(An),-(An) */
uae_u32 REGPARAM2 op_d188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
mmufixup[0].reg = -1;
uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));
COPY_CARRY();
SET_ZFLG(GET_ZFLG() & (((uae_s32)(newv)) == 0));
SET_NFLG(((uae_s32)(newv)) < 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (3 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L Dn,(An) */
uae_u32 REGPARAM2 op_d190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L Dn,(An)+ */
uae_u32 REGPARAM2 op_d198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) += 4;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L Dn,-(An) */
uae_u32 REGPARAM2 op_d1a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) - 4;
mmufixup[0].reg = dstreg | 0x0;
mmufixup[0].value = m68k_areg(regs, dstreg);
uae_s32 dst = get_long_mmu040(dsta);
m68k_areg(regs, dstreg) = dsta;
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADD.L Dn,(d16,An) */
uae_u32 REGPARAM2 op_d1a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.L Dn,(d8,An,Xn) */
uae_u32 REGPARAM2 op_d1b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
m68k_incpci(2);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADD.L Dn,(xxx).W */
uae_u32 REGPARAM2 op_d1b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADD.L Dn,(xxx).L */
uae_u32 REGPARAM2 op_d1b9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_s32 src = m68k_dreg(regs, srcreg);
uaecptr dsta;
dsta = get_ilong_mmu040(2);
uae_s32 dst = get_long_mmu040(dsta);
uae_u32 newv = ((uae_u32)(dst)) + ((uae_u32)(src));
int flgs = ((uae_s32)(src)) < 0;
int flgo = ((uae_s32)(dst)) < 0;
int flgn = ((uae_s32)(newv)) < 0;
SET_ZFLG(((uae_s32)(newv)) == 0);
SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));
SET_CFLG(((uae_u32)(~dst)) < ((uae_u32)(src)));
COPY_CARRY();
SET_NFLG(flgn != 0);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_long_mmu040(dsta, newv);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDA.L Dn,An */
uae_u32 REGPARAM2 op_d1c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_dreg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.L An,An */
uae_u32 REGPARAM2 op_d1c8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src = m68k_areg(regs, srcreg);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.L (An),An */
uae_u32 REGPARAM2 op_d1d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.L (An)+,An */
uae_u32 REGPARAM2 op_d1d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) += 4;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.L -(An),An */
uae_u32 REGPARAM2 op_d1e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) - 4;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s32 src = get_long_mmu040(srca);
m68k_areg(regs, srcreg) = srca;
uae_s32 dst = m68k_areg(regs, dstreg);
mmufixup[0].reg = -1;
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ADDA.L (d16,An),An */
uae_u32 REGPARAM2 op_d1e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDA.L (d8,An,Xn),An */
uae_u32 REGPARAM2 op_d1f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
srca = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDA.L (xxx).W,An */
uae_u32 REGPARAM2 op_d1f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDA.L (xxx).L,An */
uae_u32 REGPARAM2 op_d1f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = get_ilong_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ADDA.L (d16,PC),An */
uae_u32 REGPARAM2 op_d1fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
srca = m68k_getpci() + 2;
srca += (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ADDA.L (d8,PC,Xn),An */
uae_u32 REGPARAM2 op_d1fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uaecptr srca;
m68k_incpci(2);
uaecptr tmppc = m68k_getpci();
srca = x_get_disp_ea_020(tmppc, 0);
uae_s32 src = get_long_mmu040(srca);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ADDA.L #<data>.L,An */
uae_u32 REGPARAM2 op_d1fc_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = (real_opcode >> 9) & 7;
uae_s32 src;
src = get_ilong_mmu040(2);
uae_s32 dst = m68k_areg(regs, dstreg);
uae_u32 newv = dst + src;
m68k_areg(regs, dstreg) = (newv);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ASRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
uae_u32 sign = (0x80 & val) >> 7;
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
val = 0xff & (uae_u32)(0 - sign);
SET_CFLG(sign);
COPY_CARRY();
} else {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
val &= 0xff;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e008_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
SET_CFLG((cnt == 8) & (val >> 7));
COPY_CARRY();
val = 0;
} else {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXRQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
cnt--;
{
uae_u32 carry;
uae_u32 hival = (val << 1) | GET_XFLG();
hival <<= (7 - cnt);
val >>= cnt;
carry = val & 1;
val >>= 1;
val |= hival;
SET_XFLG(carry);
val &= 0xff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RORQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
uae_u32 hival;
cnt &= 7;
hival = val << (8 - cnt);
val >>= cnt;
val |= hival;
val &= 0xff;
SET_CFLG((val & 0x80) >> 7);
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASR.B Dn,Dn */
uae_u32 REGPARAM2 op_e020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
uae_u32 sign = (0x80 & val) >> 7;
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
val = 0xff & (uae_u32)(0 - sign);
SET_CFLG(sign);
COPY_CARRY();
} else if (cnt > 0) {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
val |= (0xff << (8 - cnt)) & (uae_u32)(0 - sign);
val &= 0xff;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSR.B Dn,Dn */
uae_u32 REGPARAM2 op_e028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
SET_CFLG((cnt == 8) & (val >> 7));
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXR.B Dn,Dn */
uae_u32 REGPARAM2 op_e030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 36) cnt -= 36;
if (cnt >= 18) cnt -= 18;
if (cnt >= 9) cnt -= 9;
if (cnt > 0) {
cnt--;
{
uae_u32 carry;
uae_u32 hival = (val << 1) | GET_XFLG();
hival <<= (7 - cnt);
val >>= cnt;
carry = val & 1;
val >>= 1;
val |= hival;
SET_XFLG(carry);
val &= 0xff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROR.B Dn,Dn */
uae_u32 REGPARAM2 op_e038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt > 0) {
uae_u32 hival;
cnt &= 7;
hival = val << (8 - cnt);
val >>= cnt;
val |= hival;
val &= 0xff;
SET_CFLG((val & 0x80) >> 7);
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e040_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
uae_u32 sign = (0x8000 & val) >> 15;
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
val = 0xffff & (uae_u32)(0 - sign);
SET_CFLG(sign);
COPY_CARRY();
} else {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
val &= 0xffff;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e048_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
SET_CFLG((cnt == 16) & (val >> 15));
COPY_CARRY();
val = 0;
} else {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXRQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e050_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
cnt--;
{
uae_u32 carry;
uae_u32 hival = (val << 1) | GET_XFLG();
hival <<= (15 - cnt);
val >>= cnt;
carry = val & 1;
val >>= 1;
val |= hival;
SET_XFLG(carry);
val &= 0xffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RORQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e058_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
uae_u32 hival;
cnt &= 15;
hival = val << (16 - cnt);
val >>= cnt;
val |= hival;
val &= 0xffff;
SET_CFLG((val & 0x8000) >> 15);
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASR.W Dn,Dn */
uae_u32 REGPARAM2 op_e060_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
uae_u32 sign = (0x8000 & val) >> 15;
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
val = 0xffff & (uae_u32)(0 - sign);
SET_CFLG(sign);
COPY_CARRY();
} else if (cnt > 0) {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
val |= (0xffff << (16 - cnt)) & (uae_u32)(0 - sign);
val &= 0xffff;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSR.W Dn,Dn */
uae_u32 REGPARAM2 op_e068_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
SET_CFLG((cnt == 16) & (val >> 15));
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXR.W Dn,Dn */
uae_u32 REGPARAM2 op_e070_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 34) cnt -= 34;
if (cnt >= 17) cnt -= 17;
if (cnt > 0) {
cnt--;
{
uae_u32 carry;
uae_u32 hival = (val << 1) | GET_XFLG();
hival <<= (15 - cnt);
val >>= cnt;
carry = val & 1;
val >>= 1;
val |= hival;
SET_XFLG(carry);
val &= 0xffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROR.W Dn,Dn */
uae_u32 REGPARAM2 op_e078_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt > 0) {
uae_u32 hival;
cnt &= 15;
hival = val << (16 - cnt);
val >>= cnt;
val |= hival;
val &= 0xffff;
SET_CFLG((val & 0x8000) >> 15);
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e080_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
uae_u32 sign = (0x80000000 & val) >> 31;
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
val = 0xffffffff & (uae_u32)(0 - sign);
SET_CFLG(sign);
COPY_CARRY();
} else {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
val &= 0xffffffff;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e088_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
SET_CFLG((cnt == 32) & (val >> 31));
COPY_CARRY();
val = 0;
} else {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXRQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e090_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
cnt--;
{
uae_u32 carry;
uae_u32 hival = (val << 1) | GET_XFLG();
hival <<= (31 - cnt);
val >>= cnt;
carry = val & 1;
val >>= 1;
val |= hival;
SET_XFLG(carry);
val &= 0xffffffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RORQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e098_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
uae_u32 hival;
cnt &= 31;
hival = val << (32 - cnt);
val >>= cnt;
val |= hival;
val &= 0xffffffff;
SET_CFLG((val & 0x80000000) >> 31);
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
uae_u32 sign = (0x80000000 & val) >> 31;
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
val = 0xffffffff & (uae_u32)(0 - sign);
SET_CFLG(sign);
COPY_CARRY();
} else if (cnt > 0) {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
val |= (0xffffffff << (32 - cnt)) & (uae_u32)(0 - sign);
val &= 0xffffffff;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
SET_CFLG((cnt == 32) & (val >> 31));
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
val >>= cnt - 1;
SET_CFLG(val & 1);
COPY_CARRY();
val >>= 1;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 33) cnt -= 33;
if (cnt > 0) {
cnt--;
{
uae_u32 carry;
uae_u32 hival = (val << 1) | GET_XFLG();
hival <<= (31 - cnt);
val >>= cnt;
carry = val & 1;
val >>= 1;
val |= hival;
SET_XFLG(carry);
val &= 0xffffffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROR.L Dn,Dn */
uae_u32 REGPARAM2 op_e0b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt > 0) {
uae_u32 hival;
cnt &= 31;
hival = val << (32 - cnt);
val >>= cnt;
val |= hival;
val &= 0xffffffff;
SET_CFLG((val & 0x80000000) >> 31);
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASRW.W (An) */
uae_u32 REGPARAM2 op_e0d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASRW.W (An)+ */
uae_u32 REGPARAM2 op_e0d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASRW.W -(An) */
uae_u32 REGPARAM2 op_e0e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASRW.W (d16,An) */
uae_u32 REGPARAM2 op_e0e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ASRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e0f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ASRW.W (xxx).W */
uae_u32 REGPARAM2 op_e0f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ASRW.W (xxx).L */
uae_u32 REGPARAM2 op_e0f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 cflg = val & 1;
val = (val >> 1) | sign;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(cflg);
COPY_CARRY();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ASLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e100_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
SET_VFLG(val != 0);
SET_CFLG(cnt == 8 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else {
uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
SET_VFLG((val & mask) != mask && (val & mask) != 0);
val <<= cnt - 1;
SET_CFLG((val & 0x80) >> 7);
COPY_CARRY();
val <<= 1;
val &= 0xff;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e108_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
SET_CFLG(cnt == 8 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else {
val <<= (cnt - 1);
SET_CFLG((val & 0x80) >> 7);
COPY_CARRY();
val <<= 1;
val &= 0xff;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e110_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
cnt--;
{
uae_u32 carry;
uae_u32 loval = val >> (7 - cnt);
carry = loval & 1;
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
SET_XFLG(carry);
val &= 0xff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROLQ.B #<data>,Dn */
uae_u32 REGPARAM2 op_e118_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
uae_u32 loval;
cnt &= 7;
loval = val >> (8 - cnt);
val <<= cnt;
val |= loval;
val &= 0xff;
SET_CFLG(val & 1);
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASL.B Dn,Dn */
uae_u32 REGPARAM2 op_e120_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
SET_VFLG(val != 0);
SET_CFLG(cnt == 8 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
uae_u32 mask = (0xff << (7 - cnt)) & 0xff;
SET_VFLG((val & mask) != mask && (val & mask) != 0);
val <<= cnt - 1;
SET_CFLG((val & 0x80) >> 7);
COPY_CARRY();
val <<= 1;
val &= 0xff;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSL.B Dn,Dn */
uae_u32 REGPARAM2 op_e128_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 8) {
SET_CFLG(cnt == 8 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
val <<= (cnt - 1);
SET_CFLG((val & 0x80) >> 7);
COPY_CARRY();
val <<= 1;
val &= 0xff;
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXL.B Dn,Dn */
uae_u32 REGPARAM2 op_e130_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 36) cnt -= 36;
if (cnt >= 18) cnt -= 18;
if (cnt >= 9) cnt -= 9;
if (cnt > 0) {
cnt--;
{
uae_u32 carry;
uae_u32 loval = val >> (7 - cnt);
carry = loval & 1;
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
SET_XFLG(carry);
val &= 0xff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROL.B Dn,Dn */
uae_u32 REGPARAM2 op_e138_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s8 cnt = m68k_dreg(regs, srcreg);
uae_s8 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u8)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt > 0) {
uae_u32 loval;
cnt &= 7;
loval = val >> (8 - cnt);
val <<= cnt;
val |= loval;
val &= 0xff;
SET_CFLG(val & 1);
}
SET_ZFLG(((uae_s8)(val)) == 0);
SET_NFLG(((uae_s8)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e140_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
SET_VFLG(val != 0);
SET_CFLG(cnt == 16 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else {
uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
SET_VFLG((val & mask) != mask && (val & mask) != 0);
val <<= cnt - 1;
SET_CFLG((val & 0x8000) >> 15);
COPY_CARRY();
val <<= 1;
val &= 0xffff;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e148_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
SET_CFLG(cnt == 16 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else {
val <<= (cnt - 1);
SET_CFLG((val & 0x8000) >> 15);
COPY_CARRY();
val <<= 1;
val &= 0xffff;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e150_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
cnt--;
{
uae_u32 carry;
uae_u32 loval = val >> (15 - cnt);
carry = loval & 1;
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
SET_XFLG(carry);
val &= 0xffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROLQ.W #<data>,Dn */
uae_u32 REGPARAM2 op_e158_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
uae_u32 loval;
cnt &= 15;
loval = val >> (16 - cnt);
val <<= cnt;
val |= loval;
val &= 0xffff;
SET_CFLG(val & 1);
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASL.W Dn,Dn */
uae_u32 REGPARAM2 op_e160_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
SET_VFLG(val != 0);
SET_CFLG(cnt == 16 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
uae_u32 mask = (0xffff << (15 - cnt)) & 0xffff;
SET_VFLG((val & mask) != mask && (val & mask) != 0);
val <<= cnt - 1;
SET_CFLG((val & 0x8000) >> 15);
COPY_CARRY();
val <<= 1;
val &= 0xffff;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSL.W Dn,Dn */
uae_u32 REGPARAM2 op_e168_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 16) {
SET_CFLG(cnt == 16 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
val <<= (cnt - 1);
SET_CFLG((val & 0x8000) >> 15);
COPY_CARRY();
val <<= 1;
val &= 0xffff;
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXL.W Dn,Dn */
uae_u32 REGPARAM2 op_e170_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 34) cnt -= 34;
if (cnt >= 17) cnt -= 17;
if (cnt > 0) {
cnt--;
{
uae_u32 carry;
uae_u32 loval = val >> (15 - cnt);
carry = loval & 1;
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
SET_XFLG(carry);
val &= 0xffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROL.W Dn,Dn */
uae_u32 REGPARAM2 op_e178_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s16 cnt = m68k_dreg(regs, srcreg);
uae_s16 data = m68k_dreg(regs, dstreg);
uae_u32 val = (uae_u16)data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt > 0) {
uae_u32 loval;
cnt &= 15;
loval = val >> (16 - cnt);
val <<= cnt;
val |= loval;
val &= 0xffff;
SET_CFLG(val & 1);
}
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e180_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
SET_VFLG(val != 0);
SET_CFLG(cnt == 32 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else {
uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
SET_VFLG((val & mask) != mask && (val & mask) != 0);
val <<= cnt - 1;
SET_CFLG((val & 0x80000000) >> 31);
COPY_CARRY();
val <<= 1;
val &= 0xffffffff;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e188_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
SET_CFLG(cnt == 32 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else {
val <<= (cnt - 1);
SET_CFLG((val & 0x80000000) >> 31);
COPY_CARRY();
val <<= 1;
val &= 0xffffffff;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e190_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
cnt--;
{
uae_u32 carry;
uae_u32 loval = val >> (31 - cnt);
carry = loval & 1;
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
SET_XFLG(carry);
val &= 0xffffffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROLQ.L #<data>,Dn */
uae_u32 REGPARAM2 op_e198_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = imm8_table[((real_opcode >> 9) & 7)];
uae_u32 dstreg = real_opcode & 7;
uae_u32 cnt = srcreg;
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
{
uae_u32 loval;
cnt &= 31;
loval = val >> (32 - cnt);
val <<= cnt;
val |= loval;
val &= 0xffffffff;
SET_CFLG(val & 1);
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1a0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
SET_VFLG(val != 0);
SET_CFLG(cnt == 32 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
uae_u32 mask = (0xffffffff << (31 - cnt)) & 0xffffffff;
SET_VFLG((val & mask) != mask && (val & mask) != 0);
val <<= cnt - 1;
SET_CFLG((val & 0x80000000) >> 31);
COPY_CARRY();
val <<= 1;
val &= 0xffffffff;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1a8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 32) {
SET_CFLG(cnt == 32 ? val & 1 : 0);
COPY_CARRY();
val = 0;
} else if (cnt > 0) {
val <<= (cnt - 1);
SET_CFLG((val & 0x80000000) >> 31);
COPY_CARRY();
val <<= 1;
val &= 0xffffffff;
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1b0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt >= 33) cnt -= 33;
if (cnt > 0) {
cnt--;
{
uae_u32 carry;
uae_u32 loval = val >> (31 - cnt);
carry = loval & 1;
val = (((val << 1) | GET_XFLG()) << cnt) | (loval >> 1);
SET_XFLG(carry);
val &= 0xffffffff;
}
}
SET_CFLG(GET_XFLG());
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROL.L Dn,Dn */
uae_u32 REGPARAM2 op_e1b8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 9) & 7);
uae_u32 dstreg = real_opcode & 7;
uae_s32 cnt = m68k_dreg(regs, srcreg);
uae_s32 data = m68k_dreg(regs, dstreg);
uae_u32 val = data;
CLEAR_CZNV();
int ccnt = cnt & 63;
cnt &= 63;
if (cnt > 0) {
uae_u32 loval;
cnt &= 31;
loval = val >> (32 - cnt);
val <<= cnt;
val |= loval;
val &= 0xffffffff;
SET_CFLG(val & 1);
}
SET_ZFLG(((uae_s32)(val)) == 0);
SET_NFLG(((uae_s32)(val)) < 0);
m68k_dreg(regs, dstreg) = (val);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASLW.W (An) */
uae_u32 REGPARAM2 op_e1d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASLW.W (An)+ */
uae_u32 REGPARAM2 op_e1d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASLW.W -(An) */
uae_u32 REGPARAM2 op_e1e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ASLW.W (d16,An) */
uae_u32 REGPARAM2 op_e1e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ASLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e1f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ASLW.W (xxx).W */
uae_u32 REGPARAM2 op_e1f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ASLW.W (xxx).L */
uae_u32 REGPARAM2 op_e1f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 sign = 0x8000 & val;
uae_u32 sign2;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
sign2 = 0x8000 & val;
SET_CFLG(sign != 0);
COPY_CARRY();
SET_VFLG(GET_VFLG() | (sign2 != sign));
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* LSRW.W (An) */
uae_u32 REGPARAM2 op_e2d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSRW.W (An)+ */
uae_u32 REGPARAM2 op_e2d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSRW.W -(An) */
uae_u32 REGPARAM2 op_e2e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSRW.W (d16,An) */
uae_u32 REGPARAM2 op_e2e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LSRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e2f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* LSRW.W (xxx).W */
uae_u32 REGPARAM2 op_e2f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LSRW.W (xxx).L */
uae_u32 REGPARAM2 op_e2f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u32 val = (uae_u16)data;
uae_u32 carry = val & 1;
val >>= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* LSLW.W (An) */
uae_u32 REGPARAM2 op_e3d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSLW.W (An)+ */
uae_u32 REGPARAM2 op_e3d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSLW.W -(An) */
uae_u32 REGPARAM2 op_e3e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* LSLW.W (d16,An) */
uae_u32 REGPARAM2 op_e3e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LSLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e3f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* LSLW.W (xxx).W */
uae_u32 REGPARAM2 op_e3f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* LSLW.W (xxx).L */
uae_u32 REGPARAM2 op_e3f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ROXRW.W (An) */
uae_u32 REGPARAM2 op_e4d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXRW.W (An)+ */
uae_u32 REGPARAM2 op_e4d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXRW.W -(An) */
uae_u32 REGPARAM2 op_e4e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXRW.W (d16,An) */
uae_u32 REGPARAM2 op_e4e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ROXRW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e4f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ROXRW.W (xxx).W */
uae_u32 REGPARAM2 op_e4f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ROXRW.W (xxx).L */
uae_u32 REGPARAM2 op_e4f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (GET_XFLG()) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
COPY_CARRY();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ROXLW.W (An) */
uae_u32 REGPARAM2 op_e5d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXLW.W (An)+ */
uae_u32 REGPARAM2 op_e5d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXLW.W -(An) */
uae_u32 REGPARAM2 op_e5e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROXLW.W (d16,An) */
uae_u32 REGPARAM2 op_e5e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ROXLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e5f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ROXLW.W (xxx).W */
uae_u32 REGPARAM2 op_e5f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ROXLW.W (xxx).L */
uae_u32 REGPARAM2 op_e5f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (GET_XFLG()) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
COPY_CARRY();
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* RORW.W (An) */
uae_u32 REGPARAM2 op_e6d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RORW.W (An)+ */
uae_u32 REGPARAM2 op_e6d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RORW.W -(An) */
uae_u32 REGPARAM2 op_e6e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* RORW.W (d16,An) */
uae_u32 REGPARAM2 op_e6e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* RORW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e6f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* RORW.W (xxx).W */
uae_u32 REGPARAM2 op_e6f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* RORW.W (xxx).L */
uae_u32 REGPARAM2 op_e6f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 1;
val >>= 1;
if (carry) val |= 0x8000;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* ROLW.W (An) */
uae_u32 REGPARAM2 op_e7d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROLW.W (An)+ */
uae_u32 REGPARAM2 op_e7d8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg);
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) += 2;
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROLW.W -(An) */
uae_u32 REGPARAM2 op_e7e0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) - 2;
mmufixup[0].reg = srcreg | 0x0;
mmufixup[0].value = m68k_areg(regs, srcreg);
uae_s16 data = get_word_mmu040(dataa);
m68k_areg(regs, srcreg) = dataa;
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
m68k_incpci(2);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
mmufixup[0].reg = -1;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 0,0 */
/* ROLW.W (d16,An) */
uae_u32 REGPARAM2 op_e7e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
dataa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ROLW.W (d8,An,Xn) */
uae_u32 REGPARAM2 op_e7f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr dataa;
m68k_incpci(2);
dataa = x_get_disp_ea_020(m68k_areg(regs, srcreg), 0);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 2 2,0 */
/* ROLW.W (xxx).W */
uae_u32 REGPARAM2 op_e7f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = (uae_s32)(uae_s16)get_iword_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
m68k_incpci(4);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
/* ROLW.W (xxx).L */
uae_u32 REGPARAM2 op_e7f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uaecptr dataa;
dataa = get_ilong_mmu040(2);
uae_s16 data = get_word_mmu040(dataa);
uae_u16 val = data;
uae_u32 carry = val & 0x8000;
val <<= 1;
if (carry) val |= 1;
CLEAR_CZNV();
SET_ZFLG(((uae_s16)(val)) == 0);
SET_NFLG(((uae_s16)(val)) < 0);
SET_CFLG(carry >> 15);
m68k_incpci(6);
regs.instruction_pc = m68k_getpci();
mmu_restart = false;
put_word_mmu040(dataa, val);
return (2 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
/* BFTST.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFTST.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFTST.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFTST.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFTST.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFTST.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFTST.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFTST.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e8fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFEXTU.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFEXTU.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9d0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFEXTU.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9e8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFEXTU.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9f0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFEXTU.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9f8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFEXTU.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9f9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFEXTU.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9fa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFEXTU.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_e9fb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFCHG.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eac0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFCHG.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ead0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFCHG.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eae8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFCHG.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eaf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
x_put_bitfield(dsta, bdata, tmp, offset, width);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFCHG.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eaf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFCHG.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eaf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFEXTS.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFEXTS.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFEXTS.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebe8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFEXTS.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFEXTS.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFEXTS.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFEXTS.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebfa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFEXTS.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ebfb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
m68k_dreg(regs, (extra >> 12) & 7) = tmp;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFCLR.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ecc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFCLR.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ecd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFCLR.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ece8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFCLR.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ecf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
x_put_bitfield(dsta, bdata, tmp, offset, width);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFCLR.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ecf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFCLR.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ecf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFFFO.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFFFO.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFFFO.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_ede8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFFFO.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edf0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFFFO.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edf8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFFFO.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edf9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFFFO.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edfa_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_getpci() + 4;
dsta += (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFFFO.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_edfb_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
uaecptr tmppc = m68k_getpci();
dsta = x_get_disp_ea_020(tmppc, 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 offset2 = offset;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
{ uae_u32 mask = 1 << (width - 1);
while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}
m68k_dreg(regs, (extra >> 12) & 7) = offset2;
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFSET.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eec0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFSET.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eed0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFSET.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eee8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFSET.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eef0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
x_put_bitfield(dsta, bdata, tmp, offset, width);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFSET.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eef8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFSET.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eef9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* BFINS.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_efc0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = m68k_dreg(regs, (extra >> 12) & 7);
tmp = tmp & (0xffffffffu >> (32 - width));
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFINS.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_efd0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = m68k_dreg(regs, (extra >> 12) & 7);
tmp = tmp & (0xffffffffu >> (32 - width));
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 0,0 */
#endif
/* BFINS.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_efe8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = m68k_dreg(regs, (extra >> 12) & 7);
tmp = tmp & (0xffffffffu >> (32 - width));
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFINS.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eff0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
m68k_incpci(4);
dsta = x_get_disp_ea_020(m68k_areg(regs, dstreg), 0);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = m68k_dreg(regs, (extra >> 12) & 7);
tmp = tmp & (0xffffffffu >> (32 - width));
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
x_put_bitfield(dsta, bdata, tmp, offset, width);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 4 2,0 */
#endif
/* BFINS.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eff8_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = (uae_s32)(uae_s16)get_iword_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = m68k_dreg(regs, (extra >> 12) & 7);
tmp = tmp & (0xffffffffu >> (32 - width));
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 6 0,0 */
#endif
/* BFINS.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_eff9_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_s16 extra = get_iword_mmu040(2);
uaecptr dsta;
dsta = get_ilong_mmu040(4);
uae_u32 bdata[2];
uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp;
dsta += offset >> 3;
tmp = x_get_bitfield(dsta, bdata, offset, width);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = m68k_dreg(regs, (extra >> 12) & 7);
tmp = tmp & (0xffffffffu >> (32 - width));
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
x_put_bitfield(dsta, bdata, tmp, offset, width);
m68k_incpci(8);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
/* 8 0,0 */
#endif
/* MMUOP030.L Dn,#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f000_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L An,#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f008_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L (An),#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f010_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L (An)+,#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f018_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L -(An),#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f020_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L (d16,An),#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f028_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L (d8,An,Xn),#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f030_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L (xxx).W,#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f038_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MMUOP030.L (xxx).L,#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f039_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
op_illg(opcode);
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f200_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f208_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f210_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f218_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f220_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f228_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f230_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f238_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f239_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f23a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 2;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,(d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f23b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 dstreg = 3;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FPP.L #<data>.W,#<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f23c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_arithmetic(opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f240_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FDBcc.L #<data>.W,Dn */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f248_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_dbcc (opcode, extra);
if (regs.fp_branch) {
regs.fp_branch = false;
if(regs.t0) check_t0_trace();
}
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f250_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f258_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,-(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f260_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,(d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f268_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,(d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f270_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,(xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f278_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FScc.L #<data>.W,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f279_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uae_s16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_scc (opcode, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FTRAPcc.L #<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f27a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uaecptr oldpc = m68k_getpci();
uae_u16 extra = get_iword_mmu040(2);
uae_s16 dummy = get_iword_mmu040(4);
m68k_incpci(6);
fpuop_trapcc (opcode, oldpc, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FTRAPcc.L #<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f27b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uaecptr oldpc = m68k_getpci();
uae_u16 extra = get_iword_mmu040(2);
uae_s32 dummy;
dummy = get_ilong_mmu040(4);
m68k_incpci(8);
fpuop_trapcc (opcode, oldpc, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FTRAPcc.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f27c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
#ifdef FPUEMU
uaecptr oldpc = m68k_getpci();
uae_u16 extra = get_iword_mmu040(2);
m68k_incpci(4);
fpuop_trapcc (opcode, oldpc, extra);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FBccQ.L #<data>,#<data>.W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f280_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 63);
#ifdef FPUEMU
m68k_incpci(2);
uaecptr pc = m68k_getpci();
uae_s16 extra = get_iword_mmu040(0);
m68k_incpci(2);
fpuop_bcc (opcode, pc,extra);
if (regs.fp_branch) {
regs.fp_branch = false;
if(regs.t0) check_t0_trace();
}
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FBccQ.L #<data>,#<data>.L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f2c0_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 63);
#ifdef FPUEMU
m68k_incpci(2);
uaecptr pc = m68k_getpci();
uae_s32 extra;
extra = get_ilong_mmu040(0);
m68k_incpci(4);
fpuop_bcc (opcode, pc,extra);
if (regs.fp_branch) {
regs.fp_branch = false;
if(regs.t0) check_t0_trace();
}
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FSAVE.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f310_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_save (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FSAVE.L -(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f320_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_save (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FSAVE.L (d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f328_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_save (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FSAVE.L (d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f330_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_save (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FSAVE.L (xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f338_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_save (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FSAVE.L (xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f339_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_save (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f350_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f358_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (d16,An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f368_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (d8,An,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f370_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (xxx).W */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f378_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f379_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (d16,PC) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f37a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* FRESTORE.L (d8,PC,Xn) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f37b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
if (!regs.s) {
Exception(8);
return 0;
}
#ifdef FPUEMU
m68k_incpci(2);
fpuop_restore (opcode);
#endif
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVLQ.L #<data>,An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f408_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVPQ.L #<data>,An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f410_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f418_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f419_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f41a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f41b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f41c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f41d_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f41e_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CINVAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f41f_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHLQ.L #<data>,An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f428_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHPQ.L #<data>,An */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f430_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
uae_u32 dstreg = real_opcode & 7;
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f438_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f439_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f43a_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f43b_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f43c_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f43d_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f43e_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* CPUSHAQ.L #<data> */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f43f_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = ((real_opcode >> 6) & 3);
if (!regs.s) {
Exception(8);
return 0;
}
flush_cpu_caches_040(opcode);
flush_mmu040(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);
if (opcode & 0x80) {
flush_icache((opcode >> 6) & 3);
}
check_t0_trace();
m68k_incpci(2);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* PFLUSHN.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f500_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_incpci(2);
mmu_op(opcode, 0);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* PFLUSH.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f508_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_incpci(2);
mmu_op(opcode, 0);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* PFLUSHAN.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f510_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_incpci(2);
mmu_op(opcode, 0);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* PFLUSHA.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f518_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_incpci(2);
mmu_op(opcode, 0);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* PTESTW.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f548_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_incpci(2);
mmu_op(opcode, 0);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* PTESTR.L (An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f568_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
if (!regs.s) {
Exception(8);
return 0;
}
m68k_incpci(2);
mmu_op(opcode, 0);
if(regs.t0) check_t0_trace();
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MOVE16.L (An)+,(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f600_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr memsa;
memsa = m68k_areg(regs, srcreg);
uaecptr memda;
memda = get_ilong_mmu040(2);
get_move16_mmu (memsa, mmu040_move16);
put_move16_mmu (memda, mmu040_move16);
m68k_areg(regs, srcreg) += 16;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MOVE16.L (xxx).L,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f608_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr memsa;
memsa = get_ilong_mmu040(2);
uaecptr memda;
memda = m68k_areg(regs, dstreg);
get_move16_mmu (memsa, mmu040_move16);
put_move16_mmu (memda, mmu040_move16);
m68k_areg(regs, dstreg) += 16;
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MOVE16.L (An),(xxx).L */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f610_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uaecptr memsa;
memsa = m68k_areg(regs, srcreg);
uaecptr memda;
memda = get_ilong_mmu040(2);
get_move16_mmu (memsa, mmu040_move16);
put_move16_mmu (memda, mmu040_move16);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MOVE16.L (xxx).L,(An) */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f618_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 dstreg = real_opcode & 7;
uaecptr memsa;
memsa = get_ilong_mmu040(2);
uaecptr memda;
memda = m68k_areg(regs, dstreg);
get_move16_mmu (memsa, mmu040_move16);
put_move16_mmu (memda, mmu040_move16);
m68k_incpci(6);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
/* MOVE16.L (An)+,(An)+ */
#ifndef CPUEMU_68000_ONLY
uae_u32 REGPARAM2 op_f620_31_ff(uae_u32 opcode)
{
int count_cycles = 0;
uae_u32 real_opcode = opcode;
uae_u32 srcreg = (real_opcode & 7);
uae_u32 dstreg = 0;
uaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;
dstreg = (get_iword_mmu040(2) >> 12) & 7;
memd = m68k_areg(regs, dstreg) & ~15;
uae_u32 v[4];
get_move16_mmu (mems, v);
put_move16_mmu (memd, v);
if (srcreg != dstreg)
m68k_areg(regs, srcreg) += 16;
m68k_areg(regs, dstreg) += 16;
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
}
#endif
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