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https://github.com/LIV2/WinUAE.git
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123 lines
3.5 KiB
C
123 lines
3.5 KiB
C
#ifndef UAE_CPUBOARD_H
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#define UAE_CPUBOARD_H
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#include "uae/types.h"
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bool cpuboard_autoconfig_init(struct autoconfig_info*);
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bool cpuboard_maprom(void);
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void cpuboard_map(void);
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void cpuboard_reset(int hardreset);
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void cpuboard_rethink(void);
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void cpuboard_cleanup(void);
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void cpuboard_init(void);
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void cpuboard_clear(void);
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bool cpuboard_is_ppcboard_irq(void);
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int cpuboard_memorytype(struct uae_prefs *p);
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int cpuboard_maxmemory(struct uae_prefs *p);
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bool cpuboard_32bit(struct uae_prefs *p);
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bool cpuboard_jitdirectompatible(struct uae_prefs *p);
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bool is_ppc_cpu(struct uae_prefs *);
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bool cpuboard_io_special(int addr, uae_u32 *val, int size, bool write);
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void cpuboard_overlay_override(void);
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void cpuboard_setboard(struct uae_prefs *p, int type, int subtype);
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uaecptr cpuboard_get_reset_pc(uaecptr *stack);
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void cpuboard_set_flash_unlocked(bool unlocked);
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void cpuboard_set_cpu(struct uae_prefs *p);
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bool cpuboard_forced_hardreset(void);
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bool ppc_interrupt(int new_m68k_ipl);
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void cyberstorm_scsi_ram_put(uaecptr addr, uae_u32);
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uae_u32 cyberstorm_scsi_ram_get(uaecptr addr);
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int REGPARAM3 cyberstorm_scsi_ram_check(uaecptr addr, uae_u32 size) REGPARAM;
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uae_u8 *REGPARAM3 cyberstorm_scsi_ram_xlate(uaecptr addr) REGPARAM;
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void cyberstorm_mk3_ppc_irq(int id, int level);
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void blizzardppc_irq(int id, int level);
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void cyberstorm_mk3_ppc_irq_setonly(int id, int level);
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void blizzardppc_irq_setonly(int id, int level);
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void cpuboard_gvpmaprom(int);
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#define BOARD_MEMORY_Z2 1
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#define BOARD_MEMORY_Z3 2
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#define BOARD_MEMORY_HIGHMEM 3
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#define BOARD_MEMORY_BLIZZARD_12xx 4
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#define BOARD_MEMORY_BLIZZARD_PPC 5
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#define BOARD_MEMORY_25BITMEM 6
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#define BOARD_MEMORY_CUSTOM_32 7
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#define ISCPUBOARDP(p, type,subtype) (cpuboards[(p)->cpuboard_type].id == type && (type < 0 || (p)->cpuboard_subtype == subtype))
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#define ISCPUBOARD(type,subtype) (cpuboards[currprefs.cpuboard_type].id == type && (type < 0 || currprefs.cpuboard_subtype == subtype))
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#define BOARD_ACT 1
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#define BOARD_ACT_SUB_APOLLO 0
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#define BOARD_COMMODORE 2
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#define BOARD_COMMODORE_SUB_A26x0 0
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#define BOARD_DCE 3
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#define BOARD_DCE_SUB_SX32PRO 0
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#define BOARD_DCE_SUB_TYPHOON2 1
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#define BOARD_DKB 4
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#define BOARD_DKB_SUB_12x0 0
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#define BOARD_DKB_SUB_WILDFIRE 1
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#define BOARD_GVP 5
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#define BOARD_GVP_SUB_A3001SI 0
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#define BOARD_GVP_SUB_A3001SII 1
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#define BOARD_GVP_SUB_A530 2
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#define BOARD_GVP_SUB_GFORCE030 3
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#define BOARD_GVP_SUB_GFORCE040 4
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#define BOARD_GVP_SUB_TEKMAGIC 5
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#define BOARD_GVP_SUB_A1230SI 6
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#define BOARD_GVP_SUB_A1230SII 7
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#define BOARD_GVP_SUB_QUIKPAK 8
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#define BOARD_KUPKE 6
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#define BOARD_MACROSYSTEM 7
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#define BOARD_MACROSYSTEM_SUB_WARPENGINE_A4000 0
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#define BOARD_MACROSYSTEM_SUB_FALCON040 1
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#define BOARD_MTEC 8
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#define BOARD_MTEC_SUB_EMATRIX530 0
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#define BOARD_BLIZZARD 9
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#define BOARD_BLIZZARD_SUB_1230II 0
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#define BOARD_BLIZZARD_SUB_1230III 1
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#define BOARD_BLIZZARD_SUB_1230IV 2
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#define BOARD_BLIZZARD_SUB_1260 3
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#define BOARD_BLIZZARD_SUB_2060 4
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#define BOARD_BLIZZARD_SUB_PPC 5
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#define BOARD_CYBERSTORM 10
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#define BOARD_CYBERSTORM_SUB_MK1 0
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#define BOARD_CYBERSTORM_SUB_MK2 1
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#define BOARD_CYBERSTORM_SUB_MK3 2
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#define BOARD_CYBERSTORM_SUB_PPC 3
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#define BOARD_RCS 11
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#define BOARD_RCS_SUB_FUSIONFORTY 0
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#define BOARD_IVS 12
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#define BOARD_IVS_SUB_VECTOR 0
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#define BOARD_PPS 13
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#define BOARD_PPS_SUB_ZEUS040 0
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#define BOARD_CSA 14
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#define BOARD_CSA_SUB_MAGNUM40 0
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#define BOARD_CSA_SUB_12GAUGE 1
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#define BOARD_HARDITAL 15
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#define BOARD_HARDITAL_SUB_TQM 0
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#define BOARD_HARMS 16
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#define BOARD_HARMS_SUB_3KPRO 0
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#define BOARD_DRACO 17
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#define BOARD_DRACO_SUB_DRACO 0
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#endif /* UAE_CPUBOARD_H */
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