WinUAE/cputest/cputestgen.ini

[cputest]

; CPU model (68000, 68020, 68030, 68040 or 68060).
cpu=68040

; CPU address space.
; If 24-bit, tester will assume upper 8-bits of addresses gets ignored.
; 24 = 24-bit address space, 32 = 32-bit address space. 680x0 = this and higher CPU models are 32-bit.
cpu_address_space=68020

; 1 = all instructions are supported (for example MOVEP if 68060 etc)
cpu_no_unimplemented=0

; FPU model (empty string or 0, 68881, 68882, 68040, 68060)
; Enable only when testing FPU. Only FPU instruction tests are allowed if FPU is enabled.
; if CPU is 68040/060 and FPU is 68881/68882, FPU type will be automatically corrected.
fpu=

; 1 = all instructions are supported (for example FSxxx and FDxx if 6888x, all normally
; unimplemented (software emulated) if 68040/68060
;fpu_unimplemented=1

; 0 = test inputs are never unnormals. 1 = test inputs can be unnormals.
;fpu_unnormals=0

; Don't generate tests that create result that has larger or smaller 16-bit extended double exponent.
; Min exponent >0 does not prevent zero results.
; Max precision: 1 = float, 2 = double, default = extended.
fpu_min_exponent=
fpu_max_exponent=
;fpu_max_precision=2

; Write generated instructions to standard output. Always disabled in "all" mode.
verbose=1

; Where to generate test files
path=data/

; gzip compression
; 0 = do not compress
; 1 = compress only test data files
; 2 = compress only main data files
; 3 = compress all data files
feature_gzip=1

; data file max size in kilobytes (split size)
; 0 = no split
max_file_size=0

; Low address space limits. Real hardware must have RAM in this space. Comment out to disable.
; Start should be zero if Amiga, set to 0x0800 if Atari ST.
; Must be disabled if cycle counting (instruction/interrupt), cycle count tests must only access real Fast RAM.
;test_low_memory_start=0x0000
;test_low_memory_end=0x8000

; High address space limits (0x00ff8000 to 0x01000000 is complete space if 24-bit). Comment out to disable.
; Automatically disabled if 32-bit CPU and end == 0x01000000
;test_high_memory_start=0x00ff8000
test_high_memory_end=0x01000000

; ROM high address space. High memory is only used for read tests, uses last 32k of ROM image file.
high_rom=D:\amiga\roms\Kickstart v3.1 rev 40.63 (1993)(Commodore)(A500-A600-A2000)[!].rom

; main test memory start and size (real hardware must have RAM in this address space)
test_memory_start=0x00460000
;test_memory_start=0x68800000
;test_memory_start=0x43800000
;test_memory_start=0x07800000
test_memory_size=0xa0000
;
;test_memory_start=0x340000
;test_memory_size=0x80000


; address where test instructions are located
; if not defined: mid point of test memory
opcode_memory_start=0x87ffa0

; number of test rounds
; registers are re-randomized after each round if not in target ea mode.
test_rounds=1

; minimum number of tests/opcode
min_opcode_test_rounds=0

; test word or long odd data access address errors (68000/010 only)
; 0 = do not generate address errors
; 1 = include address errors
; 2 = only generate test instructions that generate address errors (trace is allowed)
feature_exception3_data=0

; test branches to odd addresses
; same options as above
feature_exception3_instruction=0

; Use static effective address instead of random EA.
; Multiple values supported (max 8), separated by commas.
; Useful for bus error and address error testing
; Disables above exception3 modes.
; If odd value and 68000/010: skip all tests that don't cause address error
; Supports 68000 addressing modes only.
; If instruction only has destination EA, source Areg, Dreg or immediate is generated.
feature_target_src_ea=
feature_target_dst_ea=

; addresses where test instruction is located, use for bus error prefetch testing
; automatically enables RP bus error mode, data read bus errors are skipped.
feature_target_opcode_offset=

; Memory region that generates bus error (both read and write).
; Must be inside any test memory region.
; Can be used to verify bus errors if ea above is inside this memory region.
feature_safe_memory_start=
feature_safe_memory_size=
; R = data read only bus error
; W = data write only bus error
; P = prefetch bus error
; empty or RWP = both.
; if enabled, all tests that don't generate matching bus error are skipped.
feature_safe_memory_mode=

; user stack modes
; 0 = normal even stack
; 1 = odd stack (original stack + 1)
; 2 = odd stack and skip all tests that didn't generate address error exception
; 3 = take stack from feature_target_opcode_offset
feature_usp=0

; exception vector bus error/address error test
; 0: normal
; non-zero: replace exception vectors with this value (except vectors 2 and 3)
; skips all tests that didn't generate address error
feature_exception_vectors=

; global exception disable/enable
; -<exception number> = disable listed, enable all others. <exception number> = enable only listed
; default: all enabled
exceptions=

; CCR/FPU status flags mode
; 0 = all combinations (32 CCR loops, 256 FPU loops)
; 1 = all zeros and all ones only (2 CCR loops, 32 FPU loops)
; Xcc type instruction (Bcc, DBcc etc) always forces all combinations mode
; 2 = always all zeros and all ones only
feature_flags_mode=1

; SR initial interrupt mask
feature_initial_interrupt_mask=0

; SR min interrupt mask
; Amiga: can be zero.
; Atari ST: should be 4 or larger.
; Skips all tests that would set lower interrupt mask.
feature_min_interrupt_mask=0

; Initial active interrupt level, 0 to 6. (Amiga only)
feature_initial_interrupt=0

; Interrupt test
; 1 = interrupt request is set before test.
; Tests all INTREQ bits one by one. Compatible with cycle count mode.
; 2 = test CPU IPL sampling timing.
; 3 = 2 + Set T1 immediately before test instruction
; Uses serial port to generate timing interrupt. Requires serial port TX connected to RX.
; Generates multiple extra tests.
; Used delay instruction: ROL.L D0,D0 (D0 = number of CPU clocks * 2)
; All test rounds that generate interrupt immediately before or immediately after test instruction
; has been executed are stored. Amiga only.
feature_interrupts=0

; SR extra mask.
; 0x8000 = T1
; 0x4000 = T0 (68020-68040)
; 0x2000 = S
; 0x1000 = M (68020-68060)
; Other bits are ignored.
; For example 0xa000 adds 3 extra test rounds: S=1/T1=0, S=0/T1=1 and S=1/T1=1
; For example 0x8000 adds 1 extra test round: T1=1
; Note: instructions that generate privilege violation exception will automatically add extra S=1 round.
feature_sr_mask=0x0000

; Do not check undefined flags
; Currently supported: CHK, CHK2, DIV
feature_undefined_ccr=0

; Forced register, always use this value in all tests
; D0-D7, A0-A6, FP0-FP7, SR, CCR, FPSR, FPCR, FPIAR
; reg=0x1234 or reg=100
;feature_forced_register=

; generate JIT loop test: label: <test instruction>, <store CCR>, dbf dn,label
; value: 0 = disabled, 1 = enable, 2 = enable + extra rounds with random CCR, 3 = no CCR check/store
;feature_loop_mode=0
;feature_loop_mode_register=7 (default)
;feature_loop_mode_cnt=8 (default)

; generate 68010 loop mode tests
;feature_loop_mode_68010=0
;feature_loop_mode_register=7 (default)
;feature_loop_mode_cnt=8 (default)

; 68020+ addressing modes (this makes test files much larger if other addressing modes are also enabled)
; currently does not generate any reserved mode bit combinations.
; 0 = disabled
; 1 = enabled
; 2 = enabled + do not generate any non-68020 addressing modes
feature_full_extension_format=0

; empty = all addressing modes (feature_full_extension_format=1 enables 68020+ modes)
; Dreg, Areg, Aind, Aipi, Apdi, Ad16, PC16, Ad8r, PC8r, absw, absl, imm.
; Ad8rf and PC8rf = 68020+ full extension only. For example "Aind,Aipi,imm"
; Note: FPU source EA is considered destination EA.
feature_addressing_modes_src=
feature_addressing_modes_dst=

; empty = all condition codes
; T, F, HI, LS, CC etc.. select condition codes to generate. All others will be skipped.
; Xcc instructions only.
feature_condition_codes=

; Limit test instruction size
; B = byte, W = word, L = long, empty = no size limit
; FPU only: S = single, D = double, X = extended, P = packed
feature_instruction_size=

; mnemonics separated by comma or all/fall.
; all = generate all CPU tests. tst = generate tst.b, tst.w and tst.l. tst.l = generate only tst.l
; fall = generate all FPU tests.
; branch = all branch instructions (branchj = non-stack only, branchs = stack using)
mode=

; random seed (XOR'd with internally generated static seed)
seed=

; test groups
; use key=* to restore default value

[test=Default]
enabled=0
test_rounds=2
mode=all
feature_sr_mask=0x8000

; *********************
; 68000 - 68010 presets
; *********************

; basic instruction test
; includes trace SR flag (T)
[test=BASIC]
cpu=68000-68010
enabled=0
verbose=0
feature_sr_mask=0x8000
feature_undefined_ccr=1
mode=all

; interrupt timing test
[test=IPL]
cpu=68000-68010
enabled=1
verbose=0
feature_undefined_ccr=1
feature_interrupts=2
feature_sr_mask=0x2000
#feature_addressing_modes_dst=apdi
feature_condition_codes=pl
rnd_seed=11
mode=all

; interrupt timing test with waitstates
[test=WIPL]
cpu=68000-68010
enabled=0
verbose=0
feature_undefined_ccr=1
feature_interrupts=2
feature_waitstates=2
#feature_addressing_modes_src=dreg
feature_condition_codes=
# wait state mode requires use of chip ram
test_memory_start=0xd0000
test_memory_size=0x20000
rnd_seed=10
mode=btst.b

; STOP/SR modification timing special test
; (not -cycles compatible)
[test=SR]
cpu=68000-68010
enabled=0
verbose=0
feature_undefined_ccr=1
feature_interrupts=1
feature_initial_interrupt_mask=4
feature_sr_mask=0x8000
#mode=stop,eorsr.w,andsr.w,mvsr2.w,mv2sr.w
mode=stop

; interrupt exception
; (not -cycles compatible)
[test=IRQ]
enabled=0
verbose=0
cpu=68000-68010
feature_sr_mask=0x8000
feature_interrupts=1
feature_undefined_ccr=1
mode=jsr,jmp,bsr,bcc,dbcc,nop,exg,swap,stop,mvsr2.w,mv2sr.w,andsr.w,eorsr.w,orsr.w
min_opcode_test_rounds=100

; source EA address error
[test=AESRC]
enabled=0
cpu=68000-68010
feature_target_src_ea=0x37fff1,0x7111
feature_target_dst_ea=
feature_undefined_ccr=1
mode=all

; destination EA address error (MOVE, MOVEM)
[test=AEDST]
enabled=0
cpu=68000-68010
feature_target_src_ea=
feature_target_dst_ea=0x37fff1,0x7111
verbose=0
feature_undefined_ccr=1
mode=move,movea,mvmel,mvmle

; user stack address error
[test=ODDSTK]
enabled=0
cpu=68000-68010
feature_usp=2
verbose=0
feature_undefined_ccr=1
mode=rts,rtd,rtr,jsr,bsr,link,unlk,pea

; exception vector address error
[test=ODDEXC]
enabled=0
cpu=68000-68010
feature_exception_vectors=0x000123
verbose=0
feature_undefined_ccr=1
mode=mv2sr.w,mvusp2r,mvr2usp,illegal,chk,trap,trapv,divu,divs,orsr.w

; interrupt exception with odd interrupt vectors
[test=ODDIRQ]
enabled=0
cpu=68000-68010
mode=nop,ext,swap
feature_interrupts=1
feature_undefined_ccr=1
feature_exception_vectors=0x000123

; prefetch bus error (requires extra hardware)
[test=BEPR]
enabled=0
cpu=68000-68010
feature_safe_memory_start=0x880000
feature_safe_memory_size=0x80000
feature_safe_memory_mode=P
feature_target_opcode_offset=2,4,6,8,10,12,14,16
opcode_memory_start=0x87ffee
test_memory_size=0xa0000
test_memory_size=0x100000
opcode_memory_start=0x87ffa0
feature_undefined_ccr=1
mode=all

; source EA read bus error (requires extra hardware)
[test=BESRC]
enabled=0
cpu=68000-68010
feature_safe_memory_start=0x880000
feature_safe_memory_size=0x80000
feature_safe_memory_mode=R
feature_target_src_ea=0x87fffc,0x87fffd,0x87fffe,0x87ffff,0x880000,0x880001,0x880002,0x880003,0x880004
feature_target_dst_ea=
test_memory_start=0x860000
test_memory_size=0x100000
opcode_memory_start=0x87ffa0
feature_undefined_ccr=1
mode=all

; destination EA read bus error (requires extra hardware)
[test=BEDST]
enabled=0
cpu=68000-68010
feature_safe_memory_start=0x880000
feature_safe_memory_size=0x80000
feature_safe_memory_mode=R
feature_target_src_ea=
feature_target_dst_ea=0x87fffc,0x87fffd,0x87fffe,0x87ffff,0x880000,0x880001,0x880002,0x880003,0x880004
test_memory_start=0x860000
test_memory_size=0x100000
opcode_memory_start=0x87ffa0
feature_undefined_ccr=1
mode=all

; source EA (=RMW instructions like NOT have only source EA) write bus error (requires extra hardware)
[test=BESRCW]
enabled=0
cpu=68000-68010
feature_safe_memory_start=0x900000
feature_safe_memory_size=0x80000
feature_safe_memory_mode=W
feature_target_src_ea=0x8ffffc,0x8ffffd,0x8ffffe,0x8fffff,0x900000,0x900001,0x900002,0x900003,0x900004
feature_target_dst_ea=
opcode_memory_start=0x8fffa0
test_memory_start=0x880000
test_memory_size=0x100000
mode=moves
feature_undefined_ccr=1
mode=all

; destination EA write bus error (requires extra hardware)
[test=BEDSTW]
enabled=0
cpu=68000-68010
feature_safe_memory_start=0x900000
feature_safe_memory_size=0x80000
feature_safe_memory_mode=W
feature_target_src_ea=
feature_target_dst_ea=0x8ffffc,0x8ffffd,0x8ffffe,0x8fffff,0x900000,0x900001,0x900002,0x900003,0x900004
opcode_memory_start=0x8fffa0
test_memory_start=0x880000
test_memory_size=0x100000
feature_undefined_ccr=1
mode=all


; 68010 loop mode compatible instructions
[test=LM]
enabled=0
cpu=68010
feature_loop_mode_68010=1
feature_loop_mode_cnt=3
min_opcode_test_rounds=100
feature_undefined_ccr=1
mode=all

; **************
; 68020+ presets
; **************

; basic tests
; with all SR T1, T0 and M combinations
[test=BASIC]
enabled=0
cpu=68020-68060
feature_sr_mask=0xf000
mode=all

; interrupt exception
[test=IRQ]
enabled=0
cpu=68020-68060
mode=jsr,jmp,bsr,bcc,dbcc,nop,exg,swap,stop,mvsr2,mv2sr,andsr,eorsr,orsr,illegal,trapcc,trapv,moves
min_opcode_test_rounds=100
feature_interrupts=1

; 68020+ addressing mode tests
[test=EXTSRC]
enabled=0
cpu=68020-68060
feature_addressing_modes_src=Ad8rf,PC8rf
test_rounds=4
verbose=0
min_opcode_test_rounds=5000
mode=not,move

[test=EXTDST]
enabled=0
cpu=68020-68060
feature_addressing_modes_dst=Ad8rf,PC8rf
test_rounds=4
verbose=0
min_opcode_test_rounds=5000
mode=add,move

;address error tests
[test=AE]
enabled=0
cpu=68020-68060
feature_sr_mask=0xd000
feature_exception3_instruction=2
mode=all

; user stack address error
[test=ODDSTK]
enabled=0
cpu=68020-68060
feature_sr_mask=0xd000
feature_usp=2
mode=rts,rtd,rtr,jsr,bsr,link,unlk,pea

; exception vector address error
[test=ODDEXC]
enabled=0
cpu=68020-68060
feature_sr_mask=0xd000
feature_exception_vectors=0x000123
mode=mv2sr.w,mvsr2.w,mvusp2r,mvr2usp,illegal,chk,trap,trapv,orsr.w,eorsr.w,andsr.w,divu,divs,divul,divsl

; interrupt exception with odd interrupt vectors
[test=ODDIRQ]
enabled=0
cpu=68020-68060
feature_sr_mask=0xd000
mode=ext,swap
feature_interrupts=1
feature_exception_vectors=0x000123

; ***********
; FPU presets
; ***********

; basic test
; no arithmetic exceptions, unsupported instructions or datatypes, denormals or unnormals.
[test=FBASIC]
enabled=0
verbose=1
cpu=68020-68060
fpu=68882
feature_sr_mask=0xc000
exceptions=-48,-49,-50,-51,-52,-53,-54,-55,-11
feature_instruction_size=B,W,L,S,D,X
min_opcode_test_rounds=5000
mode=fmove,fsmove,fdmove,fint,fintrz,fneg,fsneg,fdneg,fabs,fsabs,fdabs,fdiv,fsdiv,fddiv,fadd,fsadd,fdadd,fmul,fsmul,fdmul,fsgldiv,fsglmul,fsub,fssub,fdsub,fcmp,ftst,fsqrt

; logarithmic, trigonometric and misc
; no arithmetic exceptions, unsupported instructions or datatypes, denormals or unnormals.
[test=FCPX]
enabled=0
verbose=0
cpu=68020-68030
fpu=68882
exceptions=-48,-49,-50,-51,-52,-53,-54
mode=fmod,frem,fscale,fgetexp,fgetman
mode=facos,fasin,fatan,fatanh,fcos,fcosh,fetox,fetoxm1,ftwotox
mode=flog10,flogn,flognp1,fsin,fsincos,fsinh,ftan,ftanh,ftentox

; non-arithmetic instructions (FMOVEM also includes FMOVE to/from control register)
[test=FINT]
enabled=0
verbose=0
cpu=68020-68060
fpu=68882
feature_sr_mask=0xc000
mode=fmovecr,fmovem,fdbcc,fbcc,ftrapcc,fscc

; packed datatype
; no exceptions
[test=FPACK]
enabled=0
cpu=68020-68060
fpu=68882
exceptions=-48,-49,-50,-51,-52,-53,-54
feature_flags_mode=1
feature_instruction_size=P
feature_forced_register=
;mode=fall
mode=fmove,fint,fintrz,fneg,fabs,fdiv,fadd,fmul,fsgldiv,fsglmul,fsub,fcmp,ftst,fsqrt

; FPU illegal or unimplemented instructions
[test=FILLG]
enabled=0
verbose=1
cpu=68020-68060
fpu=68882
exceptions=11,55,60,61
feature_flags_mode=2
mode=fall

; ******************
; JIT tests
; ******************

[test=JITLM]
enabled=0
cpu=68020-68060
cpu_address_space=68020
feature_loop_mode=1
opcode_memory_start=-1
mode=mvmel,mvmle,link,unlk
feature_flags_mode=1
test_rounds=3
verbose=0

; basic tests
[test=JITB]
enabled=0
cpu=68020-68060
cpu_address_space=68020
feature_flags_mode=0
verbose=1
mode=all

; 68020+ addressing mode tests
[test=JITES]
enabled=0
cpu=68020-68060
feature_addressing_modes_src=Ad8rf,PC8rf
cpu_address_space=68020
feature_loop_mode=1
opcode_memory_start=-1
test_rounds=4
verbose=0
min_opcode_test_rounds=5000
mode=not,move

[test=JITED]
enabled=0
cpu=68020-68060
feature_addressing_modes_dst=Ad8rf,PC8rf
cpu_address_space=68020
feature_loop_mode=1
opcode_memory_start=-1
test_rounds=4
verbose=0
min_opcode_test_rounds=5000
mode=add,move

[test=JITX]
enabled=0
cpu=68020-68060
cpu_address_space=68020
feature_loop_mode=3
opcode_memory_start=-1
test_rounds=4
feature_flags_mode=1
verbose=0
mode=scc,dbcc,bcc