mirror of
https://github.com/LIV2/WinUAE.git
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68020+ test presets, CPU selection update.
This commit is contained in:
Toni Wilen
parent
69adbf7061
commit
dc1aeb1c42
123
cputest.cpp
123
cputest.cpp
@ -83,6 +83,7 @@ static uae_u32 feature_target_ea[MAX_TARGET_EA][3];
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static int target_ea_src_cnt, target_ea_dst_cnt, target_ea_opcode_cnt;
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static int target_ea_src_max, target_ea_dst_max, target_ea_opcode_max;
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static uae_u32 target_ea[3];
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static int maincpu[6];
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#define HIGH_MEMORY_START (addressing_mask == 0xffffffff ? 0xffff8000 : 0x00ff8000)
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@ -980,8 +981,6 @@ static void doexcstack(void)
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bool g1 = generates_group1_exception(regs.ir);
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doexcstack2();
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if (cpu_lvl >= 2)
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return;
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if (test_exception < 4)
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return;
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@ -1942,6 +1941,10 @@ static int create_ea_random(uae_u16 *opcodep, uaecptr pc, int mode, int reg, str
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uaecptr old_pc = pc;
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uae_u16 opcode = *opcodep;
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// feature_full_extension_format = 2 and 68020 addressing modes enabled: do not generate any normal addressing modes
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if (feature_full_extension_format == 2 && (ad8r[srcdst] || pc8r[srcdst]) && (mode != Ad8r && mode != PC8r))
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return -1;
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switch (mode)
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{
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case Dreg:
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@ -2082,7 +2085,7 @@ static int create_ea_random(uae_u16 *opcodep, uaecptr pc, int mode, int reg, str
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put_word_test(pc, v);
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pc += 2;
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}
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*isconstant = 32;
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*isconstant = 128;
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*eap = 1;
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}
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break;
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@ -3230,7 +3233,7 @@ static uae_u8 *save_exception(uae_u8 *p, struct instr *dp)
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static uae_u16 get_ccr_ignore(struct instr *dp, uae_u16 extra)
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{
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uae_u16 ccrignoremask = 0;
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if ((cpu_lvl == 2 || cpu_lvl == 3) && test_exception == 5) {
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if ((cpu_lvl == 2 || cpu_lvl == 3) && (test_exception == 5 || exception_extra_frame_type == 5)) {
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if ((dp->mnemo == i_DIVS) || (dp->mnemo == i_DIVL && (extra & 0x0800) && !(extra & 0x0400))) {
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// 68020/030 DIVS.W/.L + Divide by Zero: V state is not stable.
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ccrignoremask |= 2; // mask CCR=V
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@ -3637,6 +3640,9 @@ static void test_mnemo(const TCHAR *path, const TCHAR *mnemo, const TCHAR *ovrfi
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regs.regs[15] = target_usp_address;
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}
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regs.usp = regs.regs[15];
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regs.isp = super_stack_memory - 0x80;
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if (opc == 0x0e51)
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printf("");
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if (subtest_count >= 700)
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@ -3789,6 +3795,8 @@ static void test_mnemo(const TCHAR *path, const TCHAR *mnemo, const TCHAR *ovrfi
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}
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}
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uae_u16 extraword = get_word_test(opcode_memory_address + 2);
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// loop mode
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if (feature_loop_mode) {
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// dbf dn, opcode_memory_start
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@ -4347,7 +4355,7 @@ static void test_mnemo(const TCHAR *path, const TCHAR *mnemo, const TCHAR *ovrfi
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}
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}
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// SR/CCR
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uae_u32 ccrignoremask = get_ccr_ignore(dp, ((pcaddr[2] << 8) | pcaddr[3])) << 16;
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uae_u32 ccrignoremask = get_ccr_ignore(dp, extraword) << 16;
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if ((regs.sr | ccrignoremask) != last_sr) {
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dst = store_reg(dst, CT_SR, last_sr, regs.sr | ccrignoremask, -1);
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last_sr = regs.sr | ccrignoremask;
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@ -4791,6 +4799,24 @@ static bool ini_getstringx(struct ini_data *ini, const TCHAR *sections, const TC
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return ret;
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}
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static int cputoindex(int cpu)
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{
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if (cpu == 68000) {
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return 0;
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} else if (cpu == 68010) {
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return 1;
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} else if (cpu == 68020) {
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return 2;
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} else if (cpu == 68030) {
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return 3;
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} else if (cpu == 68040) {
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return 4;
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} else if (cpu == 68060) {
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return 5;
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}
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return -1;
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}
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static int test(struct ini_data *ini, const TCHAR *sections, const TCHAR *testname)
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{
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const struct cputbl *tbl = NULL;
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@ -4806,19 +4832,72 @@ static int test(struct ini_data *ini, const TCHAR *sections, const TCHAR *testna
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return 1;
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}
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currprefs.cpu_model = 68000;
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ini_getvalx(ini, sections, _T("cpu"), &currprefs.cpu_model);
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if (currprefs.cpu_model != 68000 && currprefs.cpu_model != 68010 && currprefs.cpu_model != 68020 &&
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currprefs.cpu_model != 68030 && currprefs.cpu_model != 68040 && currprefs.cpu_model != 68060) {
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wprintf(_T("Unsupported CPU model.\n"));
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return 0;
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bool cpufound = false;
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if (ini_getstringx(ini, sections, _T("cpu"), &vs)) {
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TCHAR *p = vs;
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while (p && *p) {
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TCHAR *pp1 = _tcschr(p, ',');
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TCHAR *pp2 = _tcschr(p, '-');
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if (pp1) {
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*pp1++ = 0;
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int idx = cputoindex(_tstol(p));
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if (idx < 0) {
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wprintf(_T("Invalid CPU string '%s'\n"), vs);
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return 0;
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}
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if (maincpu[idx]) {
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cpufound = true;
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break;
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}
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p = pp1;
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} else if (pp2) {
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*pp2++ = 0;
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int idx1 = cputoindex(_tstol(p));
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int idx2 = cputoindex(_tstol(pp2));
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if (idx1 < 0 || idx2 < 0) {
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wprintf(_T("Invalid CPU string '%s'\n"), vs);
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return 0;
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}
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for (int i = idx1; i <= idx2; i++) {
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if (maincpu[i]) {
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cpufound = true;
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break;
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}
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}
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if (cpufound) {
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break;
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}
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p = pp2;
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} else {
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int idx = cputoindex(_tstol(p));
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if (idx < 0) {
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wprintf(_T("Invalid CPU string '%s'\n"), vs);
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return 0;
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}
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if (maincpu[idx]) {
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cpufound = true;
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}
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break;
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}
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}
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xfree(vs);
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}
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if (!cpufound) {
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wprintf(_T("Test skipped. CPU does not match.\n"));
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return 1;
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}
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currprefs.address_space_24 = 1;
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addressing_mask = 0x00ffffff;
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v = 24;
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v = 68030;
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ini_getvalx(ini, sections, _T("cpu_address_space"), &v);
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if (v == 32 || currprefs.cpu_model >= 68030) {
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if (v < 68000) {
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if (v == 32) {
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currprefs.address_space_24 = 0;
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addressing_mask = 0xffffffff;
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}
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} else if (currprefs.cpu_model >= v) {
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currprefs.address_space_24 = 0;
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addressing_mask = 0xffffffff;
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}
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@ -4827,7 +4906,7 @@ static int test(struct ini_data *ini, const TCHAR *sections, const TCHAR *testna
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currprefs.fpu_mode = 1;
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ini_getvalx(ini, sections, _T("fpu"), &currprefs.fpu_model);
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if (currprefs.fpu_model && currprefs.cpu_model < 68020) {
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wprintf(_T("FPU requires 68020 or 68040 CPU.\n"));
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wprintf(_T("FPU requires 68020+ CPU.\n"));
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return 0;
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}
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if (currprefs.fpu_model != 0 && currprefs.fpu_model != 68881 && currprefs.fpu_model != 68882 && currprefs.fpu_model != 68040 && currprefs.fpu_model != 68060) {
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@ -5393,7 +5472,7 @@ int __cdecl main(int argc, char *argv[])
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{
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struct ini_data *ini = ini_load(_T("cputestgen.ini"), false);
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if (!ini) {
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wprintf(_T("Couldn't open cputestgen.ini"));
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wprintf(_T("Couldn't open cputestgen.ini\n"));
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return 0;
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}
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@ -5401,6 +5480,20 @@ int __cdecl main(int argc, char *argv[])
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_tcscpy(sections, INISECTION);
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sptr += _tcslen(sptr) + 1;
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int cpu;
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if (!ini_getval(ini, INISECTION, _T("cpu"), &cpu)) {
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wprintf(_T("CPU model is not set\n"));
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return 0;
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}
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int cpuidx = cputoindex(cpu);
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if (cpuidx < 0) {
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wprintf(_T("Unsupport CPU model\n"));
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return 0;
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}
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maincpu[cpuidx] = 1;
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currprefs.cpu_model = cpu;
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int idx = 0;
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for (;;) {
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TCHAR *section = NULL;
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@ -4,8 +4,10 @@
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; Always select 68020 when testing FPU instructions, even if test hardware CPU is 68040 or 68060.
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cpu=68000
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; CPU address space. 24-bit or 32-bit. If 24-bit, tester will assume upper 8-bits of addresses gets ignored.
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cpu_address_space=24
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; CPU address space.
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; If 24-bit, tester will assume upper 8-bits of addresses gets ignored.
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; 24 = 24-bit address space, 32 = 32-bit address space. 680x0 = this and higher CPU models are 32-bit.
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cpu_address_space=68030
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; FPU model (empty string or 0, 68881, 68882, 68040, 68060)
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; Enable only when testing FPU. Enabled FPU mode will slow down native test execution even when not testing FPU instructions.
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@ -43,7 +45,7 @@ test_memory_start=0x860000
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;test_memory_start=0x68800000
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;test_memory_start=0x07800000
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;test_memory_start=0x340000
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test_memory_size=0xa0000
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test_memory_size=0x40000
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; address where test instructions are located
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; if not defined: mid point of test memory
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@ -51,7 +53,7 @@ opcode_memory_start=0x87ffa0
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; number of test rounds
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; registers are re-randomized after each round if not in target ea mode.
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test_rounds=2
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test_rounds=1
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; test word or long odd data access address errors (68000/010 only)
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; 0 = do not generate address errors
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@ -140,6 +142,9 @@ feature_loop_mode_68010=0
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; 68020+ addressing modes (this makes test files much larger if other addressing modes are also enabled)
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; currently does not generate any reserved mode bit combinations.
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; 0 = disabled
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; 1 = enabled
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; 2 = enabled + do not generate any non-68020 addressing modes
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feature_full_extension_format=0
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; empty = all addressing modes (feature_full_extension_format=1 enables 68020+ modes)
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@ -163,11 +168,18 @@ mode=
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; use key=* to restore default value
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[test=Default]
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enabled=1
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enabled=0
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test_rounds=2
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mode=all
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feature_sr_mask=0x8000
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; *********************
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; 68000 - 68010 presets
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; *********************
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; basic instruction test
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[test=Basic]
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cpu=68000-68010
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enabled=0
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mode=all
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feature_sr_mask=0x8000
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@ -175,12 +187,14 @@ feature_sr_mask=0x8000
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; interrupt exception
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[test=IRQ]
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enabled=0
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cpu=68000-68010
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mode=nop,ext,swap
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feature_interrupts=1
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; source EA address error
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[test=AE_SRC]
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enabled=0
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cpu=68000-68010
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feature_target_src_ea=0x87fff1,0x7111
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feature_target_dst_ea=
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mode=all
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@ -188,6 +202,7 @@ mode=all
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; destination EA address error (MOVE, MOVEM)
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[test=AE_DST]
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enabled=0
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cpu=68000-68010
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feature_target_src_ea=
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feature_target_dst_ea=0x87fff1,0x7111
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mode=all
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@ -195,18 +210,21 @@ mode=all
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; user stack address error
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[test=ODD_STK]
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enabled=0
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cpu=68000-68010
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feature_usp=2
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mode=rts,rtd,rtr,jsr,bsr,link,unlk,pea
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; exception vector address error
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[test=ODD_EXC]
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enabled=0
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cpu=68000-68010
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feature_exception_vectors=0x000123
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mode=mv2sr.w,mvusp2r,mvr2usp,illegal,chk,trap,trapv,divu,divs,orsr.w
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; interrupt exception with odd interrupt vectors
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[test=ODD_IRQ]
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enabled=0
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cpu=68000-68010
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mode=nop,ext,swap
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feature_interrupts=1
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feature_exception_vectors=0x000123
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@ -214,6 +232,7 @@ feature_exception_vectors=0x000123
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; prefetch bus error (requires extra hardware)
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[test=BE_PR]
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enabled=0
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cpu=68000-68010
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feature_safe_memory_start=0x880000
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feature_safe_memory_size=0x80000
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feature_safe_memory_mode=P
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@ -225,6 +244,7 @@ mode=all
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; source EA read bus error (requires extra hardware)
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[test=BE_SRC]
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enabled=0
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cpu=68000-68010
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feature_safe_memory_start=0x880000
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feature_safe_memory_size=0x80000
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feature_safe_memory_mode=R
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@ -236,6 +256,7 @@ mode=all
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; destination EA read bus error (requires extra hardware)
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[test=BE_DST]
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enabled=0
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cpu=68000-68010
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feature_safe_memory_start=0x880000
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feature_safe_memory_size=0x80000
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feature_safe_memory_mode=R
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@ -247,6 +268,7 @@ mode=all
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; source EA (=RMW instructions like NOT have only source EA) write bus error (requires extra hardware)
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[test=BE_SRCW]
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enabled=0
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cpu=68000-68010
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feature_safe_memory_start=0x900000
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feature_safe_memory_size=0x80000
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feature_safe_memory_mode=W
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@ -260,6 +282,7 @@ mode=all
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; destination EA write bus error (requires extra hardware)
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[test=BE_DSTW]
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enabled=0
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cpu=68000-68010
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feature_safe_memory_start=0x900000
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feature_safe_memory_size=0x80000
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feature_safe_memory_mode=W
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@ -269,3 +292,68 @@ opcode_memory_start=0x8fffa0
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test_memory_start=0x880000
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test_memory_size=0x100000
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mode=all
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; 68010 loop mode compatible instructions
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[test=loopmode]
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enabled=0
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cpu=68010
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feature_loop_mode_68010=1
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mode=all
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; **************
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; 68020+ presets
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; **************
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; basic tests
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; with all SR T1, T0 and M combinations
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[test=Basic]
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enabled=0
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cpu=68020-68060
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feature_sr_mask=0xd000
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mode=all
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; 68020+ addressing mode tests
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[test=FFEXT_SRC]
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enabled=0
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cpu=68020-68060
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feature_full_extension_format=2
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feature_addressing_modes_src=Ad8rf,PC8rf
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test_rounds=4
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mode=not,move
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[test=FFEXT_DST]
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enabled=0
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cpu=68020-68060
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feature_full_extension_format=2
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feature_addressing_modes_dst=Ad8rf,PC8rf
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test_rounds=4
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mode=move,add
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;address error tests
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[test=AE]
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enabled=0
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cpu=68020-68060
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feature_exception3_instruction=2
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mode=all
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; user stack address error
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[test=ODD_STK]
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enabled=0
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cpu=68020-68060
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feature_usp=2
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mode=rts,rtd,rtr,jsr,bsr,link,unlk,pea
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; exception vector address error
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[test=ODD_EXC]
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enabled=0
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cpu=68020-68060
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feature_exception_vectors=0x000123
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mode=mv2sr.w,mvsr2.w,mvusp2r,mvr2usp,illegal,chk,trap,trapv,orsr.w,eorsr.w,andsr.w,divu,divs,divul,divsl
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; interrupt exception with odd interrupt vectors
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[test=ODD_IRQ]
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enabled=0
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cpu=68020-68060
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mode=nop,ext,swap
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feature_interrupts=1
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feature_exception_vectors=0x000123
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@ -156,3 +156,8 @@ Change log:
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- Multiple test sets can be generated and tested in single step.
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- Stack usage reduced, gzip decompression works with default 4096 byte stack.
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01.03.2020
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- Added 68020+ test presets.
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- CPU selection changed. CPU=680x0 line at the top of ini is now the main CPU selection field. Test is generated if CPU model matches preset's CPU and preset is active. This update allows use of same preset for multiple CPU models.
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- cpu_address_space can be also used to select which CPU model is first 32-bit addressing capable model (normally 68020 or 68030).
|
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|
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