mirror of
https://github.com/LIV2/WinUAE.git
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Fix audio timing (previous interrupt timing fix made previously fixed values incorrect)
This commit is contained in:
Toni Wilen
parent
606eabb629
commit
a5a9ccfa40
63
audio.cpp
63
audio.cpp
@ -1402,55 +1402,46 @@ static void update_volume(int nr, uae_u16 v)
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cdp->data.audvol = v;
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}
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uae_u16 audio_dmal (void)
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uae_u16 audio_dmal(void)
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{
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uae_u16 dmal = 0;
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for (int nr = 0; nr < AUDIO_CHANNELS_PAULA; nr++) {
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struct audio_channel_data *cdp = audio_channel + nr;
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if (cdp->dr)
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dmal |= 1 << (nr * 2);
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if (cdp->dsr)
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dmal |= 1 << (nr * 2 + 1);
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if (cdp->dsr)
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dmal |= 1 << (nr * 2 + 0);
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cdp->dr = cdp->dsr = false;
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}
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return dmal;
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}
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static int isirq (int nr)
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static int isirq(int nr)
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{
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return INTREQR () & (0x80 << nr);
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return INTREQR() & (0x80 << nr);
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}
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static void audio_setirq_event(uae_u32 nr)
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{
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INTREQ_0 (0x8000 | (0x80 << nr));
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}
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static void setirq (int nr, int which)
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static void setirq(int nr, int which)
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{
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#if DEBUG_AUDIO > 0
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struct audio_channel_data *cdp = audio_channel + nr;
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if (debugchannel (nr) && cdp->wlen > 1)
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write_log (_T("SETIRQ%d (%d,%d) PC=%08X\n"), nr, which, isirq (nr) ? 1 : 0, M68K_GETPC);
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#endif
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// audio interrupts are delayed by 2 cycles
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if (!currprefs.cachesize && currprefs.cpu_compatible) {
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event2_newevent_xx (-1, 2 * CYCLE_UNIT + CYCLE_UNIT / 2, nr, audio_setirq_event);
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} else {
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audio_setirq_event(nr);
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}
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// audio interrupts are delayed by 1 CCK
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INTREQ_INT(nr + 7, CYCLE_UNIT);
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}
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static void newsample (int nr, sample8_t sample)
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static void newsample(int nr, sample8_t sample)
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{
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struct audio_channel_data *cdp = audio_channel + nr;
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#if DEBUG_AUDIO > 0
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if (!debugchannel (nr))
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if (!debugchannel(nr))
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sample = 0;
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#endif
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#if DEBUG_AUDIO > 2
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if (debugchannel (nr))
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write_log (_T("SAMPLE%d: %02x\n"), nr, sample & 0xff);
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if (debugchannel(nr))
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write_log(_T("SAMPLE%d: %02x\n"), nr, sample & 0xff);
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#endif
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if (!(audio_channel_mask & (1 << nr)))
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sample = 0;
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@ -2380,7 +2371,7 @@ static void audxdat_func(uae_u32 v)
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cdp->dat_written = false;
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}
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void AUDxDAT (int nr, uae_u16 v, uaecptr addr)
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void AUDxDAT(int nr, uae_u16 v, uaecptr addr)
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{
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struct audio_channel_data *cdp = audio_channel + nr;
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int chan_ena = (dmacon & DMA_MASTER) && (dmacon & (1 << nr));
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@ -2412,13 +2403,9 @@ void AUDxDAT (int nr, uae_u16 v, uaecptr addr)
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}
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uae_u32 vv = nr | (chan_ena ? 0x80 : 0) | (v << 8);
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if (!currprefs.cachesize && (cdp->per < PERIOD_LOW * CYCLE_UNIT || currprefs.cpu_compatible)) {
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int cyc;
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int cyc = 0;
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if (chan_ena) {
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// AUDxLEN is processed after 2 cycle delay
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cyc = 2 * CYCLE_UNIT;
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} else if (cdp->state == 0) {
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cyc = 1 * CYCLE_UNIT;
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} else {
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// AUDxLEN is processed after 1 CCK delay
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cyc = 1 * CYCLE_UNIT;
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}
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if (cyc > 0) {
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@ -2430,12 +2417,12 @@ void AUDxDAT (int nr, uae_u16 v, uaecptr addr)
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audxdat_func(vv);
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}
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}
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void AUDxDAT (int nr, uae_u16 v)
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void AUDxDAT(int nr, uae_u16 v)
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{
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AUDxDAT (nr, v, 0xffffffff);
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AUDxDAT(nr, v, 0xffffffff);
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}
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uaecptr audio_getpt (int nr, bool reset)
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uaecptr audio_getpt(int nr, bool reset)
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{
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struct audio_channel_data *cdp = audio_channel + nr;
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uaecptr p = cdp->pt;
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@ -2443,14 +2430,14 @@ uaecptr audio_getpt (int nr, bool reset)
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if (reset)
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cdp->pt = cdp->lc;
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cdp->ptx_tofetch = false;
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return p;
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return p & ~1;
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}
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void AUDxLCH (int nr, uae_u16 v)
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void AUDxLCH(int nr, uae_u16 v)
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{
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struct audio_channel_data *cdp = audio_channel + nr;
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audio_activate ();
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update_audio ();
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audio_activate();
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update_audio();
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// someone wants to update PT but DSR has not yet been processed.
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// too fast CPU and some tracker players: enable DMA, CPU delay, update AUDxPT with loop position
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@ -2475,11 +2462,11 @@ void AUDxLCH (int nr, uae_u16 v)
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}
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}
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void AUDxLCL (int nr, uae_u16 v)
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void AUDxLCL(int nr, uae_u16 v)
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{
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struct audio_channel_data *cdp = audio_channel + nr;
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audio_activate ();
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update_audio ();
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audio_activate();
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update_audio();
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if (usehacks() && ((cdp->ptx_tofetch && cdp->state == 1) || cdp->ptx_written)) {
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static int warned = 100;
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cdp->ptx = cdp->lc;
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28
custom.cpp
28
custom.cpp
@ -11484,7 +11484,7 @@ static void hsync_scandoubler(int hpos)
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reset_scandoubler_sync(hpos);
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}
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static void dmal_emu(uae_u32 v)
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static void dmal_emu(uae_u32 val)
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{
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// Disk and Audio DMA bits are ignored by Agnus. Including DMA master bit.
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int hpos = current_hpos();
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@ -11495,11 +11495,13 @@ static void dmal_emu(uae_u32 v)
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return;
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}
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}
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int dmalbits = val & 3;
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int dmalpos = val >> 8;
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if (v >= 6 && v < 14) {
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v -= 6;
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int nr = v / 2;
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uaecptr pt = audio_getpt(nr, (v & 1) != 0);
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if (dmalpos >= 6 && dmalpos < 14) {
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dmalpos -= 6;
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int nr = dmalpos / 2;
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uaecptr pt = audio_getpt(nr, (dmalbits & 1) != 0);
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if (dmal_ce) {
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#ifdef DEBUGGER
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if (debug_dma) {
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@ -11523,9 +11525,9 @@ static void dmal_emu(uae_u32 v)
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}
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regs.chipset_latch_rw = last_custom_value = dat;
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AUDxDAT(nr, dat, pt);
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} else if (v >= 0 && v < 6) {
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} else if (dmalpos >= 0 && dmalpos < 6) {
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uae_u16 dat = 0;
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int w = v & 1;
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int w = (dmalbits & 3) == 3;
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// disk_fifostatus() needed in >100% disk speed modes
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if (w) {
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// write to disk
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@ -11534,7 +11536,7 @@ static void dmal_emu(uae_u32 v)
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if (dmal_ce) {
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#ifdef DEBUGGER
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if (debug_dma) {
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record_dma_read(0x26, pt, hpos, vpos, DMARECORD_DISK, v / 2);
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record_dma_read(0x26, pt, hpos, vpos, DMARECORD_DISK, dmalpos / 2);
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}
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if (memwatch_enabled) {
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debug_getpeekdma_chipram(pt, MW_MASK_DISK, 0x26, 0x20);
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@ -11563,7 +11565,7 @@ static void dmal_emu(uae_u32 v)
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if (dmal_ce) {
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#ifdef DEBUGGER
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if (debug_dma) {
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record_dma_write(0x08, dat, pt, hpos, vpos, DMARECORD_DISK, v / 2);
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record_dma_write(0x08, dat, pt, hpos, vpos, DMARECORD_DISK, dmalpos / 2);
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}
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if (memwatch_enabled) {
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debug_putpeekdma_chipram(pt, dat, MW_MASK_DISK, 0x08, 0x20);
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@ -11575,7 +11577,7 @@ static void dmal_emu(uae_u32 v)
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}
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}
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} else {
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write_log(_T("invalid DMAL position %d\n"), v);
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write_log(_T("invalid DMAL position %d\n"), dmalpos);
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}
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}
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@ -11589,7 +11591,7 @@ static void dmal_func2(uae_u32 v)
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{
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while (dmal) {
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if (dmal & 3) {
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dmal_emu(dmal_hpos + ((dmal & 2) ? 1 : 0));
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dmal_emu((dmal_hpos << 8) | (dmal & 3));
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}
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dmal_hpos += 2;
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dmal >>= 2;
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@ -11612,10 +11614,10 @@ static void events_dmal(int hpos)
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dmal_hpos += 2;
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}
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dmal_ce = true;
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event2_newevent2(hpos, dmal_hpos + ((dmal & 2) ? 1 : 0), dmal_func);
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event2_newevent2(hpos, (dmal_hpos << 8) | (dmal & 3), dmal_func);
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dmal &= ~3;
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} else {
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event2_newevent2(hpos, dmal_hpos, dmal_func2);
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event2_newevent2(hpos, 0, dmal_func2);
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}
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}
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