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Autovectored interrupts in MMU/generic CPU modes fix.

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This commit is contained in:
Toni Wilen 2023-09-20 19:29:01 +03:00
parent c06cafaff7
commit 905f799813
3 changed files with 15 additions and 15 deletions
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2
include/newcpu.h
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@ -726,7 +726,7 @@ extern void protect_roms (bool);
extern void unprotect_maprom (void);
extern bool is_hardreset(void);
extern bool is_keyboardreset(void);
extern void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr);
extern void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr, int vector_nr);
extern void Exception_build_stack_frame(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr, int format);
extern void Exception_build_68000_address_error_stack_frame(uae_u16 mode, uae_u16 opcode, uaecptr fault_addr, uaecptr pc);
extern uae_u32 exception_pc(int nr);

6
newcpu.cpp
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@ -2967,7 +2967,7 @@ static void Exception_mmu030 (int nr, uaecptr oldpc)
mmu030_data_buffer_out = 0;
Exception_build_stack_frame(last_fault_for_exception_3, currpc, MMU030_SSW_RW | MMU030_SSW_SIZE_W | (regs.s ? 6 : 2), vector_nr, 0xB);
} else {
Exception_build_stack_frame_common(oldpc, currpc, regs.mmu_ssw, vector_nr);
Exception_build_stack_frame_common(oldpc, currpc, regs.mmu_ssw, nr, vector_nr);
}
if (newpc & 1) {
@ -3036,7 +3036,7 @@ static void Exception_mmu (int nr, uaecptr oldpc)
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, vector_nr, 0x1);
}
} else {
Exception_build_stack_frame_common(oldpc, currpc, regs.mmu_ssw, vector_nr);
Exception_build_stack_frame_common(oldpc, currpc, regs.mmu_ssw, nr, vector_nr);
}
if (newpc & 1) {
@ -3306,7 +3306,7 @@ static void Exception_normal (int nr)
x_put_word (m68k_areg (regs, 7), 0x1000 + vector_nr * 4);
}
} else {
Exception_build_stack_frame_common(oldpc, currpc, regs.mmu_ssw, vector_nr);
Exception_build_stack_frame_common(oldpc, currpc, regs.mmu_ssw, nr, vector_nr);
used_exception_build_stack_frame = true;
}
} else {

22
newcpu_common.cpp
View File

@ -1610,41 +1610,41 @@ void Exception_build_stack_frame(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int
x_put_word(m68k_areg(regs, 7), regs.sr);
}
void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr)
void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr, int vector_nr)
{
if (nr == 5 || nr == 6 || nr == 7 || nr == 9) {
if (nr == 9)
oldpc = regs.trace_pc;
if (currprefs.cpu_model <= 68010)
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x0);
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, vector_nr, 0x0);
else
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x2);
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, vector_nr, 0x2);
} else if (nr == 60 || nr == 61) {
Exception_build_stack_frame(oldpc, regs.instruction_pc, regs.mmu_ssw, nr, 0x0);
Exception_build_stack_frame(oldpc, regs.instruction_pc, regs.mmu_ssw, vector_nr, 0x0);
} else if (nr >= 48 && nr <= 55) {
if (regs.fpu_exp_pre) {
if (currprefs.cpu_model == 68060 && nr == 55 && regs.fp_unimp_pend == 2) { // packed decimal real
Exception_build_stack_frame(regs.fp_ea, regs.instruction_pc, 0, nr, 0x2);
Exception_build_stack_frame(regs.fp_ea, regs.instruction_pc, 0, vector_nr, 0x2);
} else {
Exception_build_stack_frame(oldpc, regs.instruction_pc, 0, nr, 0x0);
Exception_build_stack_frame(oldpc, regs.instruction_pc, 0, vector_nr, 0x0);
}
} else { /* post-instruction */
if (currprefs.cpu_model == 68060 && nr == 55 && regs.fp_unimp_pend == 2) { // packed decimal real
Exception_build_stack_frame(regs.fp_ea, currpc, 0, nr, 0x2);
Exception_build_stack_frame(regs.fp_ea, currpc, 0, vector_nr, 0x2);
} else {
Exception_build_stack_frame(oldpc, currpc, 0, nr, 0x3);
Exception_build_stack_frame(oldpc, currpc, 0, vector_nr, 0x3);
}
}
} else if (nr == 11 && regs.fp_unimp_ins) {
regs.fp_unimp_ins = false;
if ((currprefs.cpu_model == 68060 && (currprefs.fpu_model == 0 || (regs.pcr & 2))) ||
(currprefs.cpu_model == 68040 && currprefs.fpu_model == 0)) {
Exception_build_stack_frame(regs.fp_ea, currpc, regs.instruction_pc, nr, 0x4);
Exception_build_stack_frame(regs.fp_ea, currpc, regs.instruction_pc, vector_nr, 0x4);
} else {
Exception_build_stack_frame(regs.fp_ea, currpc, regs.mmu_ssw, nr, 0x2);
Exception_build_stack_frame(regs.fp_ea, currpc, regs.mmu_ssw, vector_nr, 0x2);
}
} else {
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x0);
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, vector_nr, 0x0);
}
}