LIV2/WinUAE
1
0
Fork 0
mirror of https://github.com/LIV2/WinUAE.git synced 2025-12-06 00:12:52 +00:00
Code Issues Packages Projects Releases Wiki Activity

More PPC friendly expansion interrupt handling.

Browse Source
This commit is contained in:
Toni Wilen 2018-02-03 11:12:22 +02:00
parent 980ee2e9fd
commit 890ec92971
22 changed files with 142 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
a2065.cpp
View File

@ -23,6 +23,7 @@
#include "autoconf.h"
#include "rommgr.h"
#include "debug.h"
#include "devices.h"
#define DUMPPACKET 0
@ -393,7 +394,7 @@ static void gotfunc (void *devv, const uae_u8 *databuf, int len)
csr[0] |= CSR0_MISS;
}
pword (p + 2, rmd1);
rethink_a2065 ();
devices_rethink_all(rethink_a2065);
return;
}
@ -423,7 +424,7 @@ static void gotfunc (void *devv, const uae_u8 *databuf, int len)
}
csr[0] |= CSR0_RINT;
rethink_a2065 ();
devices_rethink_all(rethink_a2065);
}
static int getfunc (void *devv, uae_u8 *d, int *len)
@ -543,7 +544,7 @@ static void do_transmit (void)
ethernet_trigger (td, sysdata);
}
csr[0] |= CSR0_TINT;
rethink_a2065 ();
devices_rethink_all(rethink_a2065);
}
static void check_transmit(bool tdmd)
@ -571,8 +572,6 @@ void a2065_hsync_handler (void)
void rethink_a2065 (void)
{
bool was = (uae_int_requested & 4) != 0;
atomic_and(&uae_int_requested, ~4);
if (!configured)
return;
csr[0] &= ~CSR0_INTR;
@ -582,12 +581,11 @@ void rethink_a2065 (void)
if (mask & (CSR0_BABL | CSR0_MISS | CSR0_MERR | CSR0_RINT | CSR0_TINT | CSR0_IDON))
csr[0] |= CSR0_INTR;
if ((csr[0] & (CSR0_INTR | CSR0_INEA)) == (CSR0_INTR | CSR0_INEA)) {
set_special_exter(SPCFLAG_UAEINT);
atomic_or(&uae_int_requested, 4);
if (!was && log_a2065 > 2)
safe_interrupt_set(0x0008);
if (log_a2065 > 2)
write_log(_T("7990 +IRQ\n"));
}
if (log_a2065 && was && !(uae_int_requested & 4)) {
if (log_a2065) {
write_log(_T("7990 -IRQ\n"));
}
}
@ -763,7 +761,7 @@ static void chip_wput (uaecptr addr, uae_u16 v)
}
csr[0] &= ~CSR0_TDMD;
rethink_a2065 ();
devices_rethink_all(rethink_a2065);
break;
case 1:
if (csr[0] & 4) {

21
a2091.cpp
View File

@ -44,6 +44,7 @@
#include "savestate.h"
#include "cpuboard.h"
#include "rtc.h"
#include "devices.h"
#define DMAC_8727_ROM_VECTOR 0x8000
#define CDMAC_ROM_VECTOR 0x2000
@ -275,6 +276,7 @@ static struct wd_state *wd_gvps2[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct wd_state *wd_gvps2accel;
static struct wd_state *wd_comspec[MAX_DUPLICATE_EXPANSION_BOARDS];
struct wd_state *wd_cdtv;
static bool configured;
static struct wd_state *scsi_units[MAX_SCSI_UNITS + 1];
@ -325,6 +327,7 @@ static struct wd_state *allocscsi(struct wd_state **wd, struct romconfig *rc, in
}
}
}
configured = true;
return *wd;
}
@ -452,19 +455,21 @@ static bool is_dma_enabled(struct wd_state *wds)
case COMMODORE_8727:
return wds->cdmac.dmac_dma > 0;
}
return false;
return false;
}
void rethink_a2091 (void)
{
if (!configured)
return;
for (int i = 0; i < MAX_SCSI_UNITS; i++) {
if (scsi_units[i]) {
int irq = isirq(scsi_units[i]);
if (irq & 1)
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
if (irq & 2)
INTREQ_0(0x8000 | 0x2000);
#if A2091_DEBUG > 2 || A3000_DEBUG > 2
safe_interrupt_set(0x2000);
#if DEBUG > 2 || A3000_DEBUG > 2
write_log (_T("Interrupt_RETHINK:%d\n"), irq);
#endif
}
@ -477,7 +482,7 @@ static void dmac_scsi_int(struct wd_state *wd)
return;
if (!(wd->wc.auxstatus & ASR_INT))
return;
rethink_a2091();
devices_rethink_all(rethink_a2091);
}
static void dmac_a2091_xt_int(struct wd_state *wd)
@ -485,7 +490,7 @@ static void dmac_a2091_xt_int(struct wd_state *wd)
if (!wd->enabled)
return;
wd->cdmac.xt_irq = true;
rethink_a2091();
devices_rethink_all(rethink_a2091);
}
void scsi_dmac_a2091_start_dma (struct wd_state *wd)
@ -524,7 +529,7 @@ static void incsasr (struct wd_chip_state *wd, int w)
static void dmac_a2091_cint (struct wd_state *wd)
{
wd->cdmac.dmac_istr = 0;
rethink_a2091 ();
devices_rethink_all(rethink_a2091);
}
static void doscsistatus(struct wd_state *wd, uae_u8 status)
@ -1406,7 +1411,7 @@ static void wd_check_interrupt(struct wd_state *wds, bool checkonly)
{
struct wd_chip_state *wd = &wds->wc;
if (wd->intmask) {
INTREQ_0(0x8000 | wd->intmask);
safe_interrupt_set(wd->intmask);
wd->intmask = 0;
}
if (wd->auxstatus & ASR_INT)

2
akiko.cpp
View File

@ -42,7 +42,7 @@ int log_cd32 = 0;
static void irq (void)
{
if (!(intreq & 8)) {
INTREQ_0 (0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
}

2
cd32_fmv.cpp
View File

@ -288,7 +288,7 @@ static int isdebug(uaecptr addr)
static void do_irq(void)
{
if (!(intreq & 8)) {
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
}

2
cdtv.cpp
View File

@ -98,7 +98,7 @@ static void do_stch (void);
static void INT2 (void)
{
if (!(intreq & 8)) {
INTREQ_0 (0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
cd_led ^= LED_CD_ACTIVE2;
}

2
cdtvcr.cpp
View File

@ -250,7 +250,7 @@ static void cdtvcr_4510_reset(uae_u8 v)
void rethink_cdtvcr(void)
{
if ((cdtvcr_4510_ram[CDTVCR_INTREQ] & cdtvcr_4510_ram[CDTVCR_INTENA]) && !cdtvcr_4510_ram[CDTVCR_INTDISABLE]) {
INTREQ_0 (0x8000 | 0x0008);
safe_interrupt_set(0x0008);
cd_led ^= LED_CD_ACTIVE2;
}
}

2
cia.cpp
View File

@ -124,7 +124,7 @@ static int cia_interrupt_delay;
static void ICR (uae_u32 data)
{
INTREQ_0 (0x8000 | data);
safe_interrupt_set(data);
}
static void ICRA (uae_u32 data)

27
cpuboard.cpp
View File

@ -32,6 +32,7 @@
#include "idecontrollers.h"
#include "scsi.h"
#include "cpummu030.h"
#include "devices.h"
// ROM expansion board diagrom call
// 00F83B7C 3.1 A4000
@ -983,12 +984,12 @@ void cpuboard_rethink(void)
{
if (is_csmk3(&currprefs) || is_blizzardppc(&currprefs)) {
if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_SCSI_EN | P5_IRQ_SCSI))) {
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
if (currprefs.cachesize)
atomic_or(&uae_int_requested, 0x010000);
uae_ppc_wakeup_main();
} else if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_PPC_1 | P5_IRQ_PPC_2))) {
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
if (currprefs.cachesize)
atomic_or(&uae_int_requested, 0x010000);
uae_ppc_wakeup_main();
@ -1078,22 +1079,30 @@ static void cyberstormmk2_maprom(void)
map_banks_nojitdirect(&blizzardmaprom_bank, blizzardmaprom_bank.start >> 16, 524288 >> 16, 0);
}
void cyberstorm_mk3_ppc_irq_setonly(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
}
void cyberstorm_mk3_ppc_irq(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
cpuboard_rethink();
cyberstorm_mk3_ppc_irq_setonly(level);
devices_rethink_all(cpuboard_rethink);
}
void blizzardppc_irq(int level)
void blizzardppc_irq_setonly(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
cpuboard_rethink();
}
void blizzardppc_irq(int level)
{
blizzardppc_irq_setonly(level);
devices_rethink_all(cpuboard_rethink);
}
static uae_u32 REGPARAM2 blizzardio_bget(uaecptr addr)

11
devices.cpp
View File

@ -62,6 +62,7 @@
#include "videograb.h"
#include "arcadia.h"
#include "rommgr.h"
#include "newcpu.h"
#ifdef RETROPLATFORM
#include "rp.h"
#endif
@ -213,9 +214,19 @@ void devices_hsync(void)
#endif
}
void devices_rethink_all(void func(void))
{
if (ppc_state || 0) {
devices_rethink();
} else {
func();
}
}
// these really should be dynamically allocated..
void devices_rethink(void)
{
safe_interrupt_clear_all();
rethink_cias ();
#ifdef A2065
rethink_a2065 ();

13
gayle.cpp
View File

@ -34,6 +34,7 @@
#include "debug.h"
#include "autoconf.h"
#include "rommgr.h"
#include "devices.h"
#define PCMCIA_SRAM 1
#define PCMCIA_IDE 2
@ -228,7 +229,7 @@ void rethink_gayle (void)
if (currprefs.cs_ide == IDE_A4000) {
gayle_irq |= checkgayleideirq ();
if ((gayle_irq & GAYLE_IRQ_IDE) && !(intreq & 0x0008))
INTREQ_0 (0x8000 | 0x0008);
safe_interrupt_set(0x0008);
return;
}
@ -255,9 +256,9 @@ void rethink_gayle (void)
lev2 = 1;
}
if (lev2 && !(intreq & 0x0008))
INTREQ_0 (0x8000 | 0x0008);
safe_interrupt_set(0x0008);
if (lev6 && !(intreq & 0x2000))
INTREQ_0 (0x8000 | 0x2000);
safe_interrupt_set(0x2000);
}
static void gayle_cs_change (uae_u8 mask, int onoff)
@ -272,7 +273,7 @@ static void gayle_cs_change (uae_u8 mask, int onoff)
}
if (changed) {
gayle_irq |= mask;
rethink_gayle ();
devices_rethink_all(rethink_gayle);
if ((mask & GAYLE_CS_CCDET) && (gayle_irq & (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR)) != (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR)) {
if (gayle_irq & GAYLE_IRQ_RESET)
uae_reset (0, 0);
@ -299,7 +300,7 @@ static void card_trigger (int insert)
gayle_cs_change (GAYLE_CS_WR, 0);
gayle_cs_change (GAYLE_CS_BSY, 0);
}
rethink_gayle ();
devices_rethink_all(rethink_gayle);
}
static void write_gayle_cfg (uae_u8 val)
@ -990,7 +991,7 @@ void gayle_hsync(void)
if (ne2000)
ne2000->hsync(ne2000_board_state);
if (ide_interrupt_hsync(idedrive[0]) || ide_interrupt_hsync(idedrive[2]) || ide_interrupt_hsync(idedrive[4]) || checkpcmciane2000irq())
rethink_gayle();
devices_rethink_all(rethink_gayle);
}
static uaecptr from_gayle_pcmcmia(uaecptr addr)

4
idecontrollers.cpp
View File

@ -263,8 +263,8 @@ void idecontroller_rethink(void)
irq |= ide_rethink(ide_boards[i], false);
}
}
if (irq && !(intreq & 0x0008)) {
INTREQ_0(0x8000 | 0x0008);
if (irq) {
safe_interrupt_set(0x0008);
}
}

3
include/cpuboard.h
View File

@ -32,9 +32,10 @@ extern uae_u32 cyberstorm_scsi_ram_get(uaecptr addr);
extern int REGPARAM3 cyberstorm_scsi_ram_check(uaecptr addr, uae_u32 size) REGPARAM;
extern uae_u8 *REGPARAM3 cyberstorm_scsi_ram_xlate(uaecptr addr) REGPARAM;
void cyberstorm_irq(int level);
void cyberstorm_mk3_ppc_irq(int level);
void blizzardppc_irq(int level);
void cyberstorm_mk3_ppc_irq_setonly(int level);
void blizzardppc_irq_setonly(int level);
#define BOARD_MEMORY_Z2 1
#define BOARD_MEMORY_Z3 2

1
include/devices.h
View File

@ -6,6 +6,7 @@ void devices_vsync_pre(void);
void devices_vsync_post(void);
void devices_hsync(void);
void devices_rethink(void);
void devices_rethink_all(void func(void));
void devices_syncchange(void);
void devices_update_sound(double clk, double syncadjust);
void devices_update_sync(double svpos, double syncadjust);

3
include/newcpu.h
View File

@ -285,6 +285,9 @@ extern int cpu_cycles;
extern int cpucycleunit;
extern int m68k_pc_indirect;
extern void safe_interrupt_set(uae_u32 v);
extern void safe_interrupt_clear_all(void);
STATIC_INLINE void set_special_exter(uae_u32 x)
{
atomic_or(&regs.spcflags, x);

21
ncr9x_scsi.cpp
View File

@ -32,6 +32,7 @@
#include "qemuvga/scsi/scsi.h"
#include "qemuvga/scsi/esp.h"
#include "gui.h"
#include "devices.h"
#define FASTLANE_BOARD_SIZE (2 * 16777216)
#define FASTLANE_ROM_SIZE 32768
@ -248,9 +249,9 @@ void ncr9x_rethink(void)
for (int i = 0; ncr_units[i]; i++) {
if (ncr_units[i]->boardirq) {
if (ncr_units[i]->irq6)
INTREQ_0(0x8000 | 0x2000);
safe_interrupt_set(0x2000);
else
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
return;
}
}
@ -260,7 +261,7 @@ static void set_irq2(struct ncr9x_state *ncr)
{
if (ncr->chipirq && !ncr->boardirq) {
ncr->boardirq = true;
ncr9x_rethink();
devices_rethink_all(ncr9x_rethink);
}
if (!ncr->chipirq && ncr->boardirq) {
ncr->boardirq = false;
@ -273,7 +274,7 @@ static void set_irq2_dkb1200(struct ncr9x_state *ncr)
ncr->boardirq = false;
if (ncr->chipirq && !ncr->boardirq && (ncr->states[0] & 0x40)) {
ncr->boardirq = true;
ncr9x_rethink();
devices_rethink_all(ncr9x_rethink);
}
}
@ -283,7 +284,10 @@ static void set_irq2_oktagon(struct ncr9x_state *ncr)
ncr->boardirq = false;
if (ncr->chipirq && !ncr->boardirq && (ncr->states[0] & 0x80)) {
ncr->boardirq = true;
ncr9x_rethink();
devices_rethink_all(ncr9x_rethink);
}
}
static void set_irq2_alf3(struct ncr9x_state *ncr)
{
if (!(ncr->states[0] & 0x01))
@ -306,7 +310,7 @@ static void set_irq2_fastlane(struct ncr9x_state *ncr)
if (ncr->states[0] & FLSC_PB_ESI) {
if (!ncr->boardirq) {
ncr->boardirq = true;
ncr9x_rethink();
devices_rethink_all(ncr9x_rethink);
}
}
}
@ -321,7 +325,7 @@ static void set_irq2_masoboshi(struct ncr9x_state *ncr)
ncr->boardirqlatch = true;
if (1 || ncr->intena) {
ncr->boardirq = true;
ncr9x_rethink();
devices_rethink_all(ncr9x_rethink);
#if NCR_DEBUG > 1
write_log(_T("MASOBOSHI IRQ\n"));
#endif
@ -718,7 +722,8 @@ SCSIDevice *scsiesp_device_find(SCSIBus *bus, int channel, int target, int lun)
}
void scsiesp_req_cancel(SCSIRequest *req)
{
write_log(_T("scsi_req_cancel\n"));
write_log(_T("scsi_req_cancel!?\n"));
esp_request_cancelled(req);
}
#define IO_MASK 0x3f

6
ncr_scsi.cpp
View File

@ -165,17 +165,17 @@ static struct ncr_state *ncr_wildfire;
static void set_irq2(int level)
{
if (level)
INTREQ(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
void ncr_rethink(void)
{
for (int i = 0; ncr_units[i]; i++) {
if (ncr_units[i] != ncr_cs && ncr_units[i]->irq)
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
if (ncr_cs && ncr_cs->irq)
cyberstorm_mk3_ppc_irq(1);
cyberstorm_mk3_ppc_irq_setonly(1);
}
/* 720+ */

29
newcpu.cpp
View File

@ -4357,11 +4357,36 @@ static void check_uae_int_request(void)
irq = true;
}
if (uae_int_requested & 0xff0000) {
if (!cpuboard_is_ppcboard_irq())
if (!cpuboard_is_ppcboard_irq()) {
atomic_and(&uae_int_requested, ~0x010000);
}
}
if (irq)
if (irq) {
doint();
}
}
}
/* 0x0010 = generic expansion level 2
* 0x1000 = generic expansion level 6
*/
void safe_interrupt_clear_all(void)
{
atomic_and(&uae_int_requested, ~(0x0010 | 0x1000));
}
void safe_interrupt_set(uae_u32 v)
{
if (ppc_state || 0) {
set_special_exter(SPCFLAG_UAEINT);
if (v & 0x0008)
atomic_or(&uae_int_requested, 0x0010);
if (v & 0x2000)
atomic_or(&uae_int_requested, 0x1000);
} else {
if (currprefs.cpu_cycle_exact || (!(intreq & v) && !currprefs.cpu_cycle_exact)) {
INTREQ_0(0x8000 | v);
}
}
}

18
pci.cpp
View File

@ -28,6 +28,7 @@
#include "rommgr.h"
#include "cpuboard.h"
#include "autoconf.h"
#include "devices.h"
#include "qemuvga/qemuuaeglue.h"
#include "qemuvga/queue.h"
@ -156,7 +157,6 @@ void pci_hsync(void)
void pci_rethink(void)
{
atomic_and(&uae_int_requested, ~(0x10 | 0x100));
for (int i = 0; i < PCI_BRIDGE_MAX; i++) {
struct pci_bridge *pcib = bridges[i];
if (!pcib)
@ -174,7 +174,7 @@ void pci_rethink(void)
}
}
if (pcib->irq & pcib->intena) {
atomic_or(&uae_int_requested, pcib->intreq_mask);
safe_interrupt_set(pcib->intreq_mask);
}
}
}
@ -184,7 +184,7 @@ static void set_pci_irq(struct pci_bridge *pcib, struct pci_board_state *pcibs,
pcibs->config_data[5] &= ~(1 << 3);
if (active)
pcibs->config_data[5] |= (1 << 3);
pci_rethink();
devices_rethink_all(pci_rethink);
}
static void create_config_data(struct pci_board_state *s)
@ -1506,7 +1506,7 @@ bool dkb_wildfire_pci_init(struct autoconfig_info *aci)
pcib->endian_swap_io = 0;
pcib->endian_swap_memory = 0;
pcib->intena = 0xff; // controlled by bridge config bits, bit unknown.
pcib->intreq_mask = 0x100;
pcib->intreq_mask = 0x2000;
pcib->get_index = dkb_wildfire_get_index;
pcib->baseaddress = 0x80000000;
pcib->baseaddress_end = 0xffffffff;
@ -1569,7 +1569,7 @@ static bool prometheus_pci_init(struct autoconfig_info *aci)
pcib->endian_swap_io = -1;
pcib->endian_swap_memory = -1;
pcib->intena = 0xff;
pcib->intreq_mask = 0x10;
pcib->intreq_mask = 0x0008;
pcib->get_index = prometheus_get_index;
pcib->bank = &pci_bridge_bank;
pcib->bank_zorro = 3;
@ -1618,7 +1618,7 @@ static bool grex_pci_init(struct autoconfig_info *aci)
bridges[PCI_BRIDGE_GREX] = pcib;
pcib->label = _T("G-REX");
pcib->intena = 0;
pcib->intreq_mask = 0x10;
pcib->intreq_mask = 0x0008;
pcib->get_index = grex_get_index;
pcib->baseaddress = 0x80000000;
pcib->baseaddress_end = 0xffffffff;
@ -1654,7 +1654,7 @@ static bool cbvision(struct autoconfig_info *aci)
bridges[PCI_BRIDGE_XVISION] = pcib;
pcib->label = _T("CBVision");
pcib->intena = 0;
pcib->intreq_mask = 0x10;
pcib->intreq_mask = 0x0008;
pcib->get_index = xvision_get_index;
pcib->baseaddress = 0xe0000000;
pcib->baseaddress_end = 0xffffffff;
@ -1754,7 +1754,7 @@ static void mediator_pci_init_1200(struct pci_bridge *pcib)
pcib->endian_swap_io = -1;
pcib->endian_swap_memory = -1;
pcib->intena = 0;
pcib->intreq_mask = 0x10;
pcib->intreq_mask = 0x0008;
pcib->get_index = mediator_get_index_1200;
pcib->bank = &pci_bridge_bank;
pcib->bank_2 = &pci_bridge_bank_2;
@ -1832,7 +1832,7 @@ static void mediator_pci_init_4000(struct pci_bridge *pcib)
pcib->endian_swap_io = -1;
pcib->endian_swap_memory = -1;
pcib->intena = 0;
pcib->intreq_mask = 0x10;
pcib->intreq_mask = 0x0008;
pcib->get_index = mediator_get_index_4000;
pcib->bank = &pci_bridge_bank;
pcib->bank_2 = &pci_bridge_bank_2;

7
qemuvga/ne2000.cpp
View File

@ -35,6 +35,7 @@
#include "custom.h"
#include "debug.h"
#include "sana2.h"
#include "devices.h"
#include "qemuuaeglue.h"
#include "queue.h"
@ -1856,9 +1857,9 @@ void rethink_ne2000(void)
return;
if (ne->ariadne2_irq) {
if (ne->level6)
INTREQ_0(0x8000 | 0x2000);
safe_interrupt_set(0x2000);
else
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
}
@ -1877,7 +1878,7 @@ static void ariadne2_irq_callback(struct pci_board_state *pcibs, bool irq)
write_log(_T("ariadne2_irq_callback %d\n"), irq);
#endif
ne->ariadne2_irq = irq;
rethink_ne2000();
devices_rethink_all(rethink_ne2000);
}
static addrbank ariadne2_bank = {

9
scsi.cpp
View File

@ -23,6 +23,7 @@
#include "custom.h"
#include "gayle.h"
#include "cia.h"
#include "devices.h"
#define SCSI_EMU_DEBUG 0
#define RAW_SCSI_DEBUG 0
@ -1459,7 +1460,7 @@ static void aic_int(struct soft_scsi *scsi, uae_u8 mask)
scsi->regs[16 + 8] |= mask;
if ((scsi->regs[16 + 8] & scsi->regs[3]) & 0x1f) {
scsi->irq = true;
ncr80_rethink();
devices_rethink_all(ncr80_rethink);
} else {
scsi->irq = false;
}
@ -1709,9 +1710,9 @@ void ncr80_rethink(void)
x86_doirq(5);
} else {
if (soft_scsi_devices[i]->level6)
INTREQ_0(0x8000 | 0x2000);
safe_interrupt_set(0x2000);
else
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
return;
}
}
@ -1723,7 +1724,7 @@ static void ncr5380_set_irq(struct soft_scsi *scsi)
if (scsi->irq)
return;
scsi->irq = true;
ncr80_rethink();
devices_rethink_all(ncr80_rethink);
if (scsi->delayed_irq)
x_do_cycles(2 * CYCLE_UNIT);
#if NCR5380_DEBUG_IRQ

12
sndboard.cpp
View File

@ -22,6 +22,7 @@
#include "pci_hw.h"
#include "qemuvga/qemuaudio.h"
#include "rommgr.h"
#include "devices.h"
static uae_u8 *sndboard_get_buffer(int *frames);
static void sndboard_release_buffer(uae_u8 *buffer, int frames);
@ -488,7 +489,7 @@ static void uaesnd_irq(struct uaesndboard_stream *s, uae_u8 mask)
s->intreqmask |= mask;
if ((s->intenamask & mask)) {
s->intreqmask |= 0x80;
sndboard_rethink();
devices_rethink_all(sndboard_rethink);
}
}
@ -1290,7 +1291,7 @@ static bool audio_state_sndboard_toccata(int streamid)
data->toccata_irq |= STATUS_READ_RECORD_HALF;
}
if (old != data->toccata_irq) {
sndboard_rethink();
devices_rethink_all(sndboard_rethink);
#if DEBUG_TOCCATA > 2
write_log(_T("TOCCATA IRQ\n"));
#endif
@ -1423,10 +1424,11 @@ void sndboard_rethink(void)
irq |= uaesnd_rethink();
}
if (irq) {
atomic_or(&uae_int_requested, 0x200);
set_special_exter(SPCFLAG_UAEINT);
safe_interrupt_set(0x2000);
//atomic_or(&uae_int_requested, 0x200);
//set_special_exter(SPCFLAG_UAEINT);
} else {
atomic_and(&uae_int_requested, ~0x200);
//atomic_and(&uae_int_requested, ~0x200);
}
}

7
x86.cpp
View File

@ -39,6 +39,7 @@
#include "idecontrollers.h"
#include "gfxboard.h"
#include "pci_hw.h"
#include "devices.h"
#include "dosbox/dosbox.h"
#include "dosbox/mem.h"
@ -423,7 +424,7 @@ static void set_interrupt(struct x86_bridge *xb, int bit)
write_log(_T("IO_AMIGA_INTERRUPT_STATUS set bit %d\n"), bit);
#endif
xb->amiga_io[IO_AMIGA_INTERRUPT_STATUS] |= 1 << bit;
x86_bridge_rethink();
devices_rethink_all(x86_bridge_rethink);
}
/* 8237 and 8253 from fake86 with small modifications */
@ -2968,7 +2969,7 @@ void x86_bridge_rethink(void)
uae_u8 intena = xb->amiga_io[IO_INTERRUPT_MASK];
uae_u8 status = intreq & ~intena;
if (status)
INTREQ_0(0x8000 | 0x0008);
safe_interrupt_set(0x0008);
}
}
@ -3100,7 +3101,7 @@ void x86_bridge_vsync(void)
return;
if (xb->delayed_interrupt) {
x86_bridge_rethink();
devices_rethink_all(x86_bridge_rethink);
}
}