From ab00229084587b749a151b1827196511332504c4 Mon Sep 17 00:00:00 2001 From: Frode Solheim Date: Mon, 12 Oct 2015 23:24:48 +0200 Subject: [PATCH 1/2] Revert "JIT: Fix fldcw_m_indexed for x86-64" This reverts commit e71841283e993b4ed968b7b0de30a52d5a1c26b8. --- jit/codegen_x86.cpp | 3 --- jit/compemu_midfunc_x86.cpp | 5 +++-- jit/compemu_support.cpp | 21 --------------------- 3 files changed, 3 insertions(+), 26 deletions(-) diff --git a/jit/codegen_x86.cpp b/jit/codegen_x86.cpp index b5cfb05d..bb964634 100644 --- a/jit/codegen_x86.cpp +++ b/jit/codegen_x86.cpp @@ -4230,9 +4230,6 @@ LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base)) { - /* FLDCW cannot be used with x86-64-only registers */ - assert(index <= EDI_INDEX); - ADDR32 emit_byte(0xd9); emit_byte(0xa8+index); emit_long(base); diff --git a/jit/compemu_midfunc_x86.cpp b/jit/compemu_midfunc_x86.cpp index f228830f..7a6af352 100644 --- a/jit/compemu_midfunc_x86.cpp +++ b/jit/compemu_midfunc_x86.cpp @@ -2542,8 +2542,9 @@ MENDFUNC(2,fmov_rr,(FW d, FR s)) MIDFUNC(2,fldcw_m_indexed,(RR4 index, IMM base)) { - index = readreg_x86(index, 4); - raw_fldcw_m_indexed(index, base); + index=readreg(index,4); + + raw_fldcw_m_indexed(index,base); unlock2(index); } MENDFUNC(2,fldcw_m_indexed,(RR4 index, IMM base)) diff --git a/jit/compemu_support.cpp b/jit/compemu_support.cpp index 433a6437..51508613 100644 --- a/jit/compemu_support.cpp +++ b/jit/compemu_support.cpp @@ -2009,27 +2009,6 @@ static int readreg_offset(int r, int size) return readreg_general(r,size,-1,1); } -#ifdef UAE -/* Allocate midlevel register to physical x86(-64) register, but make sure - * it is one of the (32-bit) x86 general purpose registers. */ -static int readreg_x86(int r, int size) -{ - /* First, try to use the normal register allocation routine. */ - int s = readreg(r, size); -#ifdef CPU_x86_64 - if (s > EDI_INDEX) { - /* We got a x86-64-specific register */ - jit_log("Got register %d in readreg_x86, must re-assign", s); - unlock2(s); - /* It would be better to loop through live.nat and find a - * suitable register which does not need saving to memory. */ - s = readreg_specific(r, size, EDI_INDEX); - } -#endif - return s; -} -#endif - /* writereg_general(r, size, spec) * * INPUT From dc808a39c42fcb11b24ffe56190e0994f8f635e9 Mon Sep 17 00:00:00 2001 From: Frode Solheim Date: Mon, 12 Oct 2015 23:25:32 +0200 Subject: [PATCH 2/2] JIT: Better fldcw_m_indexed fix (can use all x86-64 registers) --- jit/codegen_x86.cpp | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/jit/codegen_x86.cpp b/jit/codegen_x86.cpp index bb964634..effdb08c 100644 --- a/jit/codegen_x86.cpp +++ b/jit/codegen_x86.cpp @@ -212,6 +212,36 @@ static const uae_u8 need_to_preserve[]={0,0,0,1,0,1,1,1}; #define x86_get_target() get_target() #define x86_emit_failure(MSG) jit_fail(MSG, __FILE__, __LINE__, __FUNCTION__) +static inline void x86_64_addr32(void) +{ +#ifdef CPU_x86_64 + emit_byte(0x67); +#endif +} + +static inline void x86_64_rex(bool w, uae_u32 *r, uae_u32 *x, uae_u32 *b) +{ +#ifdef CPU_x86_64 + int rex_byte = 0x40; + if (*b >= R8_INDEX) { + *b -= R8_INDEX; + rex_byte |= 1; + } + if (rex_byte != 0x40) { + emit_byte(rex_byte); + } +#endif +} + +static inline void x86_64_prefix( + bool addr32, bool w, uae_u32 *r, uae_u32 *x, uae_u32 *b) +{ + if (addr32) { + x86_64_addr32(); + } + x86_64_rex(w, r, x, b); +} + // Some mappings to mark compemu_support calls as only used by compemu // These are still mainly x86 minded. Should be more CPU independent in the future #define compemu_raw_add_l_mi(a,b) raw_add_l_mi(a,b) @@ -4230,8 +4260,9 @@ LENDFUNC(NONE,NONE,2,raw_fmov_rr,(FW d, FR s)) LOWFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base)) { + x86_64_prefix(true, false, NULL, NULL, &index); emit_byte(0xd9); - emit_byte(0xa8+index); + emit_byte(0xa8 + index); emit_long(base); } LENDFUNC(NONE,READ,2,raw_fldcw_m_indexed,(R4 index, IMM base))