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It seems SCSI chip always resets phase state after MSGACC command.

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This commit is contained in:
Toni Wilen 2020-09-26 18:05:04 +03:00
parent 0d021407af
commit 786c89d8f8
2 changed files with 19 additions and 8 deletions
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2
ncr9x_scsi.cpp
View File

@ -954,9 +954,11 @@ static void ncr9x_io_bput3(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val, i
esp_dma_enable(ncr->devobject.lsistate, ncr->dma_on);
ncr->states[0] = val;
ncr->dma_cnt = 0;
#if NCR_DEBUG
if (ncr->dma_on) {
write_log(_T("Trifecta DMA %08x %c\n"), ncr->dma_ptr, (val & 1) ? 'R' : 'W');
}
#endif
} else if (addr == 0x402) {
ncr->dma_ptr &= 0xffff00;
ncr->dma_ptr |= val;

25
qemuvga/esp.cpp
View File

@ -71,7 +71,10 @@ static void esp_raise_irq(ESPState *s)
{
if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
s->rregs[ESP_RSTAT] |= STAT_INT;
esp_raise_ext_irq(s);
#if ESPLOG
write_log("irq->1\n");
#endif
esp_raise_ext_irq(s);
}
}
@ -79,7 +82,10 @@ static void esp_lower_irq(ESPState *s)
{
if (s->rregs[ESP_RSTAT] & STAT_INT) {
s->rregs[ESP_RSTAT] &= ~STAT_INT;
esp_lower_ext_irq(s);
#if ESPLOG
write_log("irq->0\n");
#endif
esp_lower_ext_irq(s);
}
}
@ -87,6 +93,9 @@ static void fas408_raise_irq(ESPState *s)
{
if (!(s->rregs[ESP_REGS + NCR_PSTAT] & NCRPSTAT_SIRQ)) {
s->rregs[ESP_REGS + NCR_PSTAT] |= NCRPSTAT_SIRQ;
#if ESPLOG
write_log("irq408->1\n");
#endif
esp_raise_ext_irq(s);
}
}
@ -95,7 +104,10 @@ static void fas408_lower_irq(ESPState *s)
{
if (s->rregs[ESP_REGS + NCR_PSTAT] & NCRPSTAT_SIRQ) {
s->rregs[ESP_REGS + NCR_PSTAT] &= ~NCRPSTAT_SIRQ;
esp_lower_ext_irq(s);
#if ESPLOG
write_log("irq408->0\n");
#endif
esp_lower_ext_irq(s);
}
}
@ -855,11 +867,8 @@ void esp_reg_write(void *opaque, uint32_t saddr, uint64_t val)
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = 0;
//s->rregs[ESP_RFLAGS] = 0;
// Features enable
if (!(s->wregs[ESP_CFG2] & 0x40)) {
// Masoboshi driver expects phase=0!
s->rregs[ESP_RSTAT] &= ~7;
}
// Masoboshi and Trifecta drivers expects phase=0
s->rregs[ESP_RSTAT] &= ~7;
esp_raise_irq(s);
break;
case CMD_PAD: