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S3Trio64 PCI, Pixel 64 color fix.

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This commit is contained in:
Toni Wilen 2024-01-22 18:54:01 +02:00
parent cf3eb4bfe4
commit 7432d08b91
6 changed files with 69 additions and 10 deletions
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25
gfxboard.cpp
View File

@ -257,6 +257,13 @@ static const struct gfxboard boards[] =
0x00000000, 0x00400000, 0x00400000, 0x00400000, 0, 4, 3, false, false,
0, 0, NULL, &ncr_retina_z3_device, 0, GFXBOARD_BUSTYPE_DRACO
},
{
GFXBOARD_ID_PIXEL64,
_T("Pixel64 [AteoBus]"), _T("Atéo Concepts"), _T("Pixel64"),
2026, 255, 254, 0, // 255: type=$c7 flags=$40, 254: type=$c2 flags=$40 128k, 252: type=$c2 flags=$40, 128k
0x00000000, 0x00200000, 0x00200000, 0x00400000, CIRRUS_ID_CLGD5434, 2, 0, false, false,
0, 0, NULL, &gd5434_vlb_device
},
{
GFXBOARD_ID_HARLEQUIN,
_T("Harlequin [Zorro II]"), _T("ACS"), _T("Harlequin_PAL"),
@ -287,20 +294,20 @@ static const struct gfxboard boards[] =
0x00000000, 0x00400000, 0x00400000, 0x10000000, 0, 0, -1, false, false,
0, 0, NULL, &s3_virge_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_S3TRIO64_PCI,
_T("Trio64 [PCI]"), _T("S3"), _T("S3TRIO64_PCI"),
0, 0, 0, 0,
0x00000000, 0x00200000, 0x00400000, 0x10000000, 0, 0, -1, false, false,
0, 0, NULL, &s3_trio64_device, 0, GFXBOARD_BUSTYPE_PCI
},
{
GFXBOARD_ID_VGA,
_T("x86 bridgeboard VGA [ISA]"), _T("x86"), _T("VGA"),
_T("x86 Bridgeboard VGA [ISA]"), _T("x86"), _T("VGA"),
0, 0, 0, 0,
0x00000000, 0x00100000, 0x00200000, 0x00000000, CIRRUS_ID_CLGD5426, 0, 0, false, false,
ROMTYPE_x86_VGA
},
{
GFXBOARD_ID_PIXEL64,
_T("Pixel64 [AteoBus]"), _T("Atéo Concepts"), _T("Pixel64"),
2026, 255, 254, 0, // 255: type=$c7 flags=$40, 254: type=$c2 flags=$40 128k, 252: type=$c2 flags=$40, 128k
0x00000000, 0x00200000, 0x00200000, 0x00400000, CIRRUS_ID_CLGD5434, 2, 0, false, false,
0, 0, NULL, &gd5434_vlb_swapped_device
},
{
NULL
}
@ -3690,7 +3697,7 @@ static void pci_change_config(struct pci_board_state *pci)
reinit_vram(gb, pci->bar[1] + pci->bridge->memory_start_offset, false);
}
}
} else if (gb->rbc->rtgmem_type == GFXBOARD_ID_S3VIRGE_PCI) {
} else if (gb->rbc->rtgmem_type == GFXBOARD_ID_S3VIRGE_PCI || gb->rbc->rtgmem_type == GFXBOARD_ID_S3TRIO64_PCI) {
if (pci->memory_map_active) {
reinit_vram(gb, pci->bar[0] + pci->bridge->memory_start_offset, false);
}

1
include/gfxboard.h
View File

@ -85,6 +85,7 @@ int pcem_getvramsize(void);
#define GFXBOARD_ID_RETINA_Z3 22
#define GFXBOARD_ID_ALTAIS_Z3 23
#define GFXBOARD_ID_VOODOO5_PCI 24
#define GFXBOARD_ID_S3TRIO64_PCI 25
#define GFXBOARD_BUSTYPE_Z 0
#define GFXBOARD_BUSTYPE_PCI 1

22
pcem/vid_cl5429.cpp
View File

@ -2904,11 +2904,18 @@ static void *gd5434_init()
}
static void *gd5434_vlb_swapped_init()
{
gd5429_t *gd5429 = (gd5429_t *)cl_init(CL_TYPE_GD5434, "PicccoSD64", -1, 0);
gd5429_t *gd5429 = (gd5429_t *)cl_init(CL_TYPE_GD5434, "CL", -1, 0);
has_vlb = 1;
gd5429->svga.swaprb = 1;
return gd5429;
}
static void *gd5434_vlb_init()
{
gd5429_t *gd5429 = (gd5429_t *)cl_init(CL_TYPE_GD5434, "CL", -1, 0);
has_vlb = 1;
gd5429->svga.swaprb = 0;
return gd5429;
}
static void *gd5446_init()
{
PCI = 1;
@ -3214,6 +3221,19 @@ device_t gd5434_device =
gd5434_config
};
device_t gd5434_vlb_device =
{
"Cirrus Logic GD5434",
0,
gd5434_vlb_init,
gd5429_close,
gd5434_available,
gd5429_speed_changed,
gd5429_force_redraw,
gd5429_add_status_info,
gd5434_config
};
device_t gd5434_vlb_swapped_device =
{
"Cirrus Logic GD5434",

1
pcem/vid_cl5429.h
View File

@ -6,6 +6,7 @@ extern device_t gd5426_device;
extern device_t gd5428_swapped_device;
extern device_t gd5426_swapped_device;
extern device_t gd5434_vlb_swapped_device;
extern device_t gd5434_vlb_device;
extern device_t gd5446_device;
extern device_t ibm_gd5428_device;
extern device_t gd5429_device;

29
pcem/vid_s3.cpp
View File

@ -2953,6 +2953,22 @@ int s3_phoenix_trio64_available()
#endif
void *s3_trio64_init()
{
s3_t *s3 = (s3_t*)s3_init("86c764x1.bin", S3_TRIO64);
s3->id = 0xe1; /*Trio64*/
s3->id_ext = s3->id_ext_pci = 0x11;
s3->packed_mmio = 1;
s3->getclock = s3_trio64_getclock;
s3->getclock_p = s3;
s3->svga.fb_only = -1;
return s3;
}
void *s3_cybervision_init()
{
s3_t *s3 = (s3_t*)s3_init("86c764x1.bin", S3_TRIO64);
@ -3209,4 +3225,17 @@ device_t s3_cybervision_trio64_device =
NULL
};
device_t s3_trio64_device =
{
"S3Trio64",
0,
s3_trio64_init,
s3_close,
NULL,
s3_speed_changed,
s3_force_redraw,
s3_add_status_info,
NULL
};
#endif

1
pcem/vid_s3.h
View File

@ -3,3 +3,4 @@ extern device_t s3_9fx_device;
extern device_t s3_phoenix_trio32_device;
extern device_t s3_phoenix_trio64_device;
extern device_t s3_cybervision_trio64_device;
extern device_t s3_trio64_device;