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This commit is contained in:
Toni Wilen 2013-07-18 19:23:55 +03:00
parent 251b2f77af
commit 58cfd544ef
43 changed files with 1507 additions and 1741 deletions
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26
a2091.cpp
View File

@ -249,14 +249,14 @@ static void INT2 (void)
uae_int_requested |= 2;
}
static void dmac_start_dma (void)
void scsi_dmac_start_dma (void)
{
#if A3000_DEBUG > 0 || A2091_DEBUG > 0
write_log (_T("DMAC DMA started, ADDR=%08X, LEN=%08X words\n"), dmac_acr, dmac_wtc);
#endif
dmac_dma = 1;
}
static void dmac_stop_dma (void)
void scsi_dmac_stop_dma (void)
{
dmac_dma = 0;
dmac_istr &= ~ISTR_E_INT;
@ -1064,10 +1064,10 @@ static uae_u32 dmac_read_word (uaecptr addr)
break;
case 0xe0:
if (dmac_dma <= 0)
dmac_start_dma ();
scsi_dmac_start_dma ();
break;
case 0xe2:
dmac_stop_dma ();
scsi_dmac_stop_dma ();
break;
case 0xe4:
dmac_cint ();
@ -1164,10 +1164,10 @@ static void dmac_write_word (uaecptr addr, uae_u32 b)
break;
case 0xe0:
if (dmac_dma <= 0)
dmac_start_dma ();
scsi_dmac_start_dma ();
break;
case 0xe2:
dmac_stop_dma ();
scsi_dmac_stop_dma ();
break;
case 0xe4:
dmac_cint ();
@ -1364,7 +1364,7 @@ static void mbdmac_write_word (uae_u32 addr, uae_u32 val)
break;
case 0x12:
if (dmac_dma <= 0)
dmac_start_dma ();
scsi_dmac_start_dma ();
break;
case 0x16:
if (dmac_dma) {
@ -1380,7 +1380,7 @@ static void mbdmac_write_word (uae_u32 addr, uae_u32 val)
/* ISTR */
break;
case 0x3e:
dmac_stop_dma ();
scsi_dmac_stop_dma ();
break;
}
}
@ -1445,7 +1445,7 @@ static uae_u32 mbdmac_read_word (uae_u32 addr)
break;
case 0x12:
if (dmac_dma <= 0)
dmac_start_dma ();
scsi_dmac_start_dma ();
v = 0;
break;
case 0x1a:
@ -1462,7 +1462,7 @@ static uae_u32 mbdmac_read_word (uae_u32 addr)
break;
case 0x3e:
if (dmac_dma) {
dmac_stop_dma ();
scsi_dmac_stop_dma ();
dmac_istr |= ISTR_FE_FLG;
}
v = 0;
@ -1640,7 +1640,7 @@ static void *scsi_thread (void *null)
return 0;
}
static void init_scsi (void)
void init_scsi (void)
{
if (!scsi_thread_running) {
scsi_thread_running = 1;
@ -1659,6 +1659,7 @@ static void freescsi (struct scsi_data *sd)
int add_scsi_hd (int ch, struct hd_hardfiledata *hfd, struct uaedev_config_info *ci, int scsi_level)
{
init_scsi ();
freescsi (scsis[ch]);
scsis[ch] = NULL;
if (!hfd) {
@ -1674,6 +1675,7 @@ int add_scsi_hd (int ch, struct hd_hardfiledata *hfd, struct uaedev_config_info
int add_scsi_cd (int ch, int unitnum)
{
init_scsi ();
device_func_init (0);
freescsi (scsis[ch]);
scsis[ch] = scsi_alloc_cd (ch, unitnum, false);
@ -1682,6 +1684,7 @@ int add_scsi_cd (int ch, int unitnum)
int add_scsi_tape (int ch, const TCHAR *tape_directory, bool readonly)
{
init_scsi ();
freescsi (scsis[ch]);
scsis[ch] = scsi_alloc_tape (ch, tape_directory, readonly);
return scsis[ch] ? 1 : 0;
@ -1775,7 +1778,6 @@ void a3000scsi_free (void)
int a2091_add_scsi_unit (int ch, struct uaedev_config_info *ci)
{
init_scsi ();
if (ci->type == UAEDEV_CD)
return add_scsi_cd (ch, ci->device_emu_unit);
else if (ci->type == UAEDEV_TAPE)

2
akiko.cpp
View File

@ -1792,7 +1792,7 @@ static void patchrom (void)
{
int i;
if (currprefs.cpu_model > 68020 || currprefs.cachesize || currprefs.m68k_speed != 0) {
uae_u8 *p = (uae_u8*)extendedkickmemory;
uae_u8 *p = extendedkickmem_bank.baseaddr;
for (i = 0; i < 524288 - sizeof (patchdata); i++) {
if (!memcmp (p + i, patchdata, sizeof(patchdata))) {
protect_roms (false);

42
ar.cpp
View File

@ -611,38 +611,38 @@ static void action_replay_chipwrite (void);
void REGPARAM2 chipmem_lput_actionreplay1 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
m = (uae_u32 *)(chipmemory + addr);
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_wput_actionreplay1 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
m = (uae_u16 *)(chipmemory + addr);
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput_actionreplay1 (uaecptr addr, uae_u32 b)
{
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (addr >= 0x60 && addr <= 0x63 && !is_ar_pc_in_rom())
action_replay_chipwrite();
chipmemory[addr] = b;
chipmem_bank.baseaddr[addr] = b;
}
void REGPARAM2 chipmem_lput_actionreplay23 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
if (addr == 8 && action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
@ -651,9 +651,9 @@ void REGPARAM2 chipmem_wput_actionreplay23 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
if (addr == 8 && action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
@ -990,7 +990,7 @@ static void hrtmon_go (void)
hrtmon_flag = ACTION_REPLAY_ACTIVE;
set_special (SPCFLAG_ACTION_REPLAY);
if (hrtmon_zeropage)
memcpy (hrtmon_zeropage, chipmemory, 1024);
memcpy (hrtmon_zeropage, chipmem_bank.baseaddr, 1024);
if (hrtmon_custom)
memcpy (hrtmon_custom, ar_custom, 2 * 256);
for (i = 0; i < 16; i++) {
@ -1213,7 +1213,7 @@ static uae_u8 ar3patch2[] = {0x00,0xfc,0x01,0x44};
static void action_replay_patch (void)
{
int off1,off2;
uae_u8 *kickmem = kickmemory;
uae_u8 *kickmem = kickmem_bank.baseaddr;
if (armodel != 3 || !kickmem || !armemory_rom)
return;
@ -1229,10 +1229,10 @@ static void action_replay_patch (void)
}
if (off1 == 524288 - sizeof (ar3patch1) || off2 == ar_rom_file_size - sizeof (ar3patch2))
return;
armemory_rom[off2 + 0] = (uae_u8)((off1 + kickmem_start + 2) >> 24);
armemory_rom[off2 + 1] = (uae_u8)((off1 + kickmem_start + 2) >> 16);
armemory_rom[off2 + 2] = (uae_u8)((off1 + kickmem_start + 2) >> 8);
armemory_rom[off2 + 3] = (uae_u8)((off1 + kickmem_start + 2) >> 0);
armemory_rom[off2 + 0] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 24);
armemory_rom[off2 + 1] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 16);
armemory_rom[off2 + 2] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 8);
armemory_rom[off2 + 3] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 0);
write_log (_T("AR ROM patched for KS2.0+ (%x)\n"), off2);
}

20
archivers/lha/slide.cpp
View File

@ -81,7 +81,7 @@ static struct decode_option decode_set;
#if 0
static node pos, matchpos, avail, *position, *parent, *prev;
static int remainder, matchlen;
static int remainderlh, matchlen;
static unsigned char *level, *childcount;
static unsigned long dicsiz; /* t.okamoto */
static unsigned short max_hash_val;
@ -108,7 +108,7 @@ static unsigned int hval;
static int matchlen;
static unsigned int matchpos;
static unsigned int pos;
static unsigned int remainder;
static unsigned int remainderlh;
#if 0
/* ------------------------------------------------------------------------ */
@ -189,7 +189,7 @@ static void update()
n = fread_crc(&text[(unsigned)(txtsiz - dicsiz)],
(unsigned)dicsiz, infile);
remainder += n;
remainderlh += n;
encoded_origsize += n;
pos -= dicsiz;
@ -280,7 +280,7 @@ static void match_insert()
static void get_next()
{
remainder--;
remainderlh--;
if (++pos >= txtsiz - maxmatch) {
update();
#ifdef DEBUG
@ -316,22 +316,22 @@ struct interfacing *lhinterface;
encode_set.encode_start();
memset(&text[0], ' ', (long)TXTSIZ);
remainder = fread_crc(&text[dicsiz], txtsiz-dicsiz, infile);
encoded_origsize = remainder;
remainderlh = fread_crc(&text[dicsiz], txtsiz-dicsiz, infile);
encoded_origsize = remainderlh;
matchlen = THRESHOLD - 1;
pos = dicsiz;
if (matchlen > remainder) matchlen = remainder;
if (matchlen > remainderlh) matchlen = remainderlh;
hval = ((((text[dicsiz] << 5) ^ text[dicsiz + 1]) << 5)
^ text[dicsiz + 2]) & (unsigned)(HSHSIZ - 1);
insert();
while (remainder > 0 && ! unpackable) {
while (remainderlh > 0 && ! unpackable) {
lastmatchlen = matchlen; lastmatchoffset = pos - matchpos - 1;
--matchlen;
get_next(); match_insert();
if (matchlen > remainder) matchlen = remainder;
if (matchlen > remainderlh) matchlen = remainderlh;
if (matchlen > lastmatchlen || lastmatchlen < THRESHOLD) {
encode_set.output(text[pos - 1], 0);
#ifdef DEBUG
@ -365,7 +365,7 @@ struct interfacing *lhinterface;
get_next();
matchlen = THRESHOLD - 1;
match_insert();
if (matchlen > remainder) matchlen = remainder;
if (matchlen > remainderlh) matchlen = remainderlh;
}
}
encode_set.encode_end();

6
autoconf.cpp
View File

@ -222,9 +222,9 @@ static uae_u32 REGPARAM2 nullfunc (TrapContext *context)
static uae_u32 REGPARAM2 getchipmemsize (TrapContext *context)
{
m68k_dreg (regs, 1) = allocated_z3chipmem;
m68k_areg (regs, 1) = z3chipmem_start;
return allocated_chipmem;
m68k_dreg (regs, 1) = z3chipmem_bank.allocated;
m68k_areg (regs, 1) = z3chipmem_bank.start;
return chipmem_bank.allocated;
}
static uae_u32 REGPARAM2 uae_puts (TrapContext *context)

18
cdtv.cpp
View File

@ -1049,6 +1049,16 @@ static void dmac_start_dma (void)
{
if (!(dmac_cntr & CNTR_PDMD)) { // non-scsi dma
write_comm_pipe_u32 (&requests, 0x0100, 1);
} else {
scsi_dmac_start_dma ();
}
}
static void dmac_stop_dma (void)
{
if (!(dmac_cntr & CNTR_PDMD)) { // non-scsi dma
;
} else {
scsi_dmac_stop_dma ();
}
}
@ -1401,7 +1411,10 @@ static void dmac_bput2 (uaecptr addr, uae_u32 b)
break;
case 0xe2:
case 0xe3:
dmac_dma = 0;
if (dmac_dma) {
dmac_dma = 0;
dmac_stop_dma ();
}
dma_finished = 0;
break;
case 0xe4:
@ -1679,7 +1692,6 @@ void cdtv_free (void)
#ifdef ROMHACK2
extern uae_u8 *extendedkickmemory, *cardmemory;
static void romhack (void)
{
struct zfile *z;
@ -1760,6 +1772,8 @@ void cdtv_init (void)
cdtv_battram_reset ();
open_unit ();
gui_flicker_led (LED_CD, 0, -1);
if (currprefs.cs_cdtvscsi)
init_scsi ();
}
void cdtv_check_banks (void)

2
cfgfile.cpp
View File

@ -192,7 +192,7 @@ static const TCHAR *specialmonitors[] = { _T("none"), _T("autodetect"), _T("a202
static const TCHAR *rtgtype[] = {
_T("ZorroII"), _T("ZorroIII"),
_T("PicassoII"), _T("PicassoII+"),
_T("Piccolo"), _T("PiccoloSD64_Z2"), _T("PiccoloSD64_Z3"),
_T("Piccolo_Z2"), _T("Piccolo_Z3"), _T("PiccoloSD64_Z2"), _T("PiccoloSD64_Z3"),
_T("PiccoloSD64_Z2"), _T("PiccoloSD64_Z3"),
_T("Spectrum28/24_Z2"), _T("Spectrum28/24_Z3"),
_T("PicassoIV_Z2"), _T("PicassoIV_Z3"),

2
cia.cpp
View File

@ -1474,7 +1474,7 @@ addrbank cia_bank = {
cia_lget, cia_wget, cia_bget,
cia_lput, cia_wput, cia_bput,
default_xlate, default_check, NULL, _T("CIA"),
cia_lgeti, cia_wgeti, ABFLAG_IO
cia_lgeti, cia_wgeti, ABFLAG_IO, 0x3f00
};
// Gayle or Fat Gary does not enable CIA /CS lines if both CIAs are selected

6
custom.cpp
View File

@ -6533,7 +6533,7 @@ static void hsync_handler_post (bool onvsync)
cia_hsync += ((MAXVPOS_PAL * MAXHPOS_PAL * 50 * 256) / (maxhpos * (currprefs.cs_ciaatod == 2 ? 60 : 50)));
}
#endif
} else if (currprefs.cs_ciaatod == 0 && onvsync) {
} else if (currprefs.cs_ciaatod == 0 && vpos == (currprefs.ntscmode ? VSYNC_ENDLINE_NTSC : VSYNC_ENDLINE_PAL)) {
CIA_vsync_posthandler (ciavsyncs);
}
@ -6702,7 +6702,7 @@ static void hsync_handler_post (bool onvsync)
extern int volatile uaenet_int_requested;
extern int volatile uaenet_vsync_requested;
if (uaenet_int_requested || (uaenet_vsync_requested && vpos == 10)) {
INTREQ (0x8000 | 0x2000);
INTREQ (0x8000 | 0x0008);
}
}
@ -7151,7 +7151,7 @@ addrbank custom_bank = {
custom_lget, custom_wget, custom_bget,
custom_lput, custom_wput, custom_bput,
default_xlate, default_check, NULL, _T("Custom chipset"),
custom_lgeti, custom_wgeti, ABFLAG_IO
custom_lgeti, custom_wgeti, ABFLAG_IO, 0x1ff
};
static uae_u32 REGPARAM2 custom_wgeti (uaecptr addr)

194
debug.cpp
View File

@ -657,19 +657,19 @@ int notinrom (void)
static uae_u32 lastaddr (void)
{
if (currprefs.z3fastmem2_size)
return z3fastmem2_start + currprefs.z3fastmem2_size;
return z3fastmem2_bank.start + currprefs.z3fastmem2_size;
if (currprefs.z3fastmem_size)
return z3fastmem_start + currprefs.z3fastmem_size;
return z3fastmem_bank.start + currprefs.z3fastmem_size;
if (currprefs.z3chipmem_size)
return z3chipmem_start + currprefs.z3chipmem_size;
return z3chipmem_bank.start + currprefs.z3chipmem_size;
if (currprefs.mbresmem_high_size)
return a3000hmem_start + currprefs.mbresmem_high_size;
return a3000hmem_bank.start + currprefs.mbresmem_high_size;
if (currprefs.mbresmem_low_size)
return a3000lmem_start + currprefs.mbresmem_low_size;
return a3000lmem_bank.start + currprefs.mbresmem_low_size;
if (currprefs.bogomem_size)
return bogomem_start + currprefs.bogomem_size;
return bogomem_bank.start + currprefs.bogomem_size;
if (currprefs.fastmem_size)
return fastmem_start + currprefs.fastmem_size;
return fastmem_bank.start + currprefs.fastmem_size;
return currprefs.chipmem_size;
}
@ -689,7 +689,7 @@ static uaecptr nextaddr2 (uaecptr addr, int *next)
prevx = prev;
sizex = size;
size = currprefs.z3fastmem_size;
prev = z3fastmem_start;
prev = z3fastmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
@ -699,7 +699,7 @@ static uaecptr nextaddr2 (uaecptr addr, int *next)
prevx = prev;
sizex = size;
size = currprefs.z3chipmem_size;
prev = z3chipmem_start;
prev = z3chipmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
@ -709,7 +709,7 @@ static uaecptr nextaddr2 (uaecptr addr, int *next)
sizex = size;
prevx = prev;
size = currprefs.mbresmem_high_size;
prev = a3000hmem_start;
prev = a3000hmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
@ -719,7 +719,7 @@ static uaecptr nextaddr2 (uaecptr addr, int *next)
prevx = prev;
sizex = size;
size = currprefs.mbresmem_low_size;
prev = a3000lmem_start;
prev = a3000lmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
@ -729,7 +729,7 @@ static uaecptr nextaddr2 (uaecptr addr, int *next)
sizex = size;
prevx = prev;
size = currprefs.bogomem_size;
prev = bogomem_start;
prev = bogomem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
@ -739,7 +739,7 @@ static uaecptr nextaddr2 (uaecptr addr, int *next)
sizex = size;
prevx = prev;
size = currprefs.fastmem_size;
prev = fastmem_start;
prev = fastmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
@ -1160,6 +1160,8 @@ static void decode_dma_record (int hpos, int vpos, int toggle, bool logfile)
sr = _T("COP ");
else if (dr->type == DMARECORD_BLITTER)
sr = _T("BLT ");
else if (dr->type == DMARECORD_BLITTER_LINE)
sr = _T("BLL ");
else if (dr->type == DMARECORD_REFRESH)
sr = _T("RFS ");
else if (dr->type == DMARECORD_AUDIO)
@ -1726,7 +1728,7 @@ static void illg_init (void)
addr = end - 1;
}
if (currprefs.rtgmem_size)
memset (illghdebug + (p96ram_start >> 16), 3, currprefs.rtgmem_size >> 16);
memset (illghdebug + (gfxmem_bank.start >> 16), 3, currprefs.rtgmem_size >> 16);
i = 0;
while (custd[i].name) {
@ -1809,9 +1811,13 @@ static void illg_debug_do (uaecptr addr, int rwi, int size, uae_u32 val)
}
}
static int debug_mem_off (uaecptr addr)
static int debug_mem_off (uaecptr *addrp)
{
return munge24 (addr) >> 16;
uaecptr addr = *addrp;
int offset = munge24 (addr) >> 16;
addr &= debug_mem_banks[offset]->mask;
*addrp = addr;
return offset;
}
struct smc_item {
@ -2121,7 +2127,7 @@ static int mmu_hit (uaecptr addr, int size, int rwi, uae_u32 *v);
static uae_u32 REGPARAM2 mmu_lget (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 4, 0, &v))
v = debug_mem_banks[off]->lget (addr);
@ -2129,7 +2135,7 @@ static uae_u32 REGPARAM2 mmu_lget (uaecptr addr)
}
static uae_u32 REGPARAM2 mmu_wget (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 2, 0, &v))
v = debug_mem_banks[off]->wget (addr);
@ -2137,7 +2143,7 @@ static uae_u32 REGPARAM2 mmu_wget (uaecptr addr)
}
static uae_u32 REGPARAM2 mmu_bget (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit(addr, 1, 0, &v))
v = debug_mem_banks[off]->bget (addr);
@ -2145,26 +2151,26 @@ static uae_u32 REGPARAM2 mmu_bget (uaecptr addr)
}
static void REGPARAM2 mmu_lput (uaecptr addr, uae_u32 v)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
if (!mmu_hit (addr, 4, 1, &v))
debug_mem_banks[off]->lput (addr, v);
}
static void REGPARAM2 mmu_wput (uaecptr addr, uae_u32 v)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
if (!mmu_hit (addr, 2, 1, &v))
debug_mem_banks[off]->wput (addr, v);
}
static void REGPARAM2 mmu_bput (uaecptr addr, uae_u32 v)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
if (!mmu_hit (addr, 1, 1, &v))
debug_mem_banks[off]->bput (addr, v);
}
static uae_u32 REGPARAM2 debug_lget (uaecptr addr)
{
int off = debug_mem_off (addr);
uae_u32 off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->lget (addr);
memwatch_func (addr, 1, 4, &v);
@ -2172,7 +2178,7 @@ static uae_u32 REGPARAM2 debug_lget (uaecptr addr)
}
static uae_u32 REGPARAM2 mmu_lgeti (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 4, 4, &v))
v = debug_mem_banks[off]->lgeti (addr);
@ -2180,7 +2186,7 @@ static uae_u32 REGPARAM2 mmu_lgeti (uaecptr addr)
}
static uae_u32 REGPARAM2 mmu_wgeti (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 2, 4, &v))
v = debug_mem_banks[off]->wgeti (addr);
@ -2189,7 +2195,7 @@ static uae_u32 REGPARAM2 mmu_wgeti (uaecptr addr)
static uae_u32 REGPARAM2 debug_wget (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->wget (addr);
memwatch_func (addr, 1, 2, &v);
@ -2197,7 +2203,7 @@ static uae_u32 REGPARAM2 debug_wget (uaecptr addr)
}
static uae_u32 REGPARAM2 debug_bget (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->bget (addr);
memwatch_func (addr, 1, 1, &v);
@ -2205,7 +2211,7 @@ static uae_u32 REGPARAM2 debug_bget (uaecptr addr)
}
static uae_u32 REGPARAM2 debug_lgeti (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->lgeti (addr);
memwatch_func (addr, 4, 4, &v);
@ -2213,7 +2219,7 @@ static uae_u32 REGPARAM2 debug_lgeti (uaecptr addr)
}
static uae_u32 REGPARAM2 debug_wgeti (uaecptr addr)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->wgeti (addr);
memwatch_func (addr, 4, 2, &v);
@ -2221,19 +2227,19 @@ static uae_u32 REGPARAM2 debug_wgeti (uaecptr addr)
}
static void REGPARAM2 debug_lput (uaecptr addr, uae_u32 v)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
if (memwatch_func (addr, 2, 4, &v))
debug_mem_banks[off]->lput (addr, v);
}
static void REGPARAM2 debug_wput (uaecptr addr, uae_u32 v)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
if (memwatch_func (addr, 2, 2, &v))
debug_mem_banks[off]->wput (addr, v);
}
static void REGPARAM2 debug_bput (uaecptr addr, uae_u32 v)
{
int off = debug_mem_off (addr);
int off = debug_mem_off (&addr);
if (memwatch_func (addr, 2, 1, &v))
debug_mem_banks[off]->bput (addr, v);
}
@ -2251,8 +2257,8 @@ uae_u16 debug_wputpeekdma (uaecptr addr, uae_u32 v)
if (!memwatch_enabled)
return v;
if (!currprefs.z3chipmem_size)
addr &= chipmem_mask;
memwatch_func (addr & chipmem_mask, 2, 2, &v);
addr &= chipmem_bank.mask;
memwatch_func (addr & chipmem_bank.mask, 2, 2, &v);
return v;
}
uae_u16 debug_wgetpeekdma (uaecptr addr, uae_u32 v)
@ -2261,7 +2267,7 @@ uae_u16 debug_wgetpeekdma (uaecptr addr, uae_u32 v)
if (!memwatch_enabled)
return v;
if (!currprefs.z3chipmem_size)
addr &= chipmem_mask;
addr &= chipmem_bank.mask;
memwatch_func (addr, 1, 2, &vv);
return vv;
}
@ -2309,20 +2315,113 @@ void debug_lgetpeek (uaecptr addr, uae_u32 v)
struct membank_store
{
addrbank *addr;
addrbank store;
addrbank newbank;
int banknr;
};
static struct membank_store *membank_stores;
static int membank_total;
#define MEMWATCH_STORE_SLOTS 32
static void memwatch_reset (void)
{
for (int i = 0; i < membank_total; i++) {
addrbank *ab = debug_mem_banks[i];
if (!ab)
continue;
map_banks_quick (ab, i, 1, 1);
}
for (int i = 0; membank_stores[i].addr; i++) {
struct membank_store *ms = &membank_stores[i];
xfree (ms->newbank.name);
memset (ms, 0, sizeof (struct membank_store));
ms->addr = NULL;
}
memset (debug_mem_banks, 0, membank_total * sizeof (addrbank*));
}
static void memwatch_remap (uaecptr addr)
{
int mode = 0;
int i;
int banknr;
struct membank_store *ms;
addrbank *bank;
addrbank *newbank = NULL;
addr &= ~65535;
banknr = addr >> 16;
if (debug_mem_banks[banknr])
return;
bank = mem_banks[banknr];
for (i = 0 ; i < MEMWATCH_STORE_SLOTS; i++) {
ms = &membank_stores[i];
if (ms->addr == NULL)
break;
if (ms->addr == bank) {
newbank = &ms->newbank;
break;
}
}
if (i >= MEMWATCH_STORE_SLOTS)
return;
if (!newbank) {
TCHAR tmp[200];
_stprintf (tmp, _T("%s [D]"), bank->name);
ms->addr = bank;
newbank = &ms->newbank;
memcpy (newbank, bank, sizeof addrbank);
newbank->bget = mode ? mmu_bget : debug_bget;
newbank->wget = mode ? mmu_wget : debug_wget;
newbank->lget = mode ? mmu_lget : debug_lget;
newbank->bput = mode ? mmu_bput : debug_bput;
newbank->wput = mode ? mmu_wput : debug_wput;
newbank->lput = mode ? mmu_lput : debug_lput;
newbank->check = debug_check;
newbank->xlateaddr = debug_xlate;
newbank->wgeti = mode ? mmu_wgeti : debug_wgeti;
newbank->lgeti = mode ? mmu_lgeti : debug_lgeti;
newbank->name = my_strdup (tmp);
if (!newbank->mask)
newbank->mask = -1;
}
debug_mem_banks[banknr] = bank;
map_banks_quick (newbank, banknr, 1, 1);
// map aliases
for (i = 0; i < membank_total; i++) {
uaecptr addr2 = i << 16;
addrbank *ab = &get_mem_bank(addr2);
if (ab != ms->addr)
continue;
if ((addr2 & ab->mask) == (addr & bank->mask)) {
debug_mem_banks[i] = ms->addr;
map_banks_quick (newbank, i, 1, 1);
}
}
}
static void memwatch_setup (void)
{
memwatch_reset ();
for (int i = 0; i < MEMWATCH_TOTAL; i++) {
struct memwatch_node *m = &mwnodes[i];
uae_u32 size = 0;
if (!m->size)
continue;
while (size < m->size) {
memwatch_remap (m->addr + size);
size += 65536;
}
}
}
static int deinitialize_memwatch (void)
{
int i, oldmode;
int oldmode;
if (!memwatch_enabled && !mmu_enabled)
return -1;
for (i = 0; membank_stores[i].addr; i++) {
memcpy (membank_stores[i].addr, &membank_stores[i].store, sizeof (addrbank));
}
memwatch_reset ();
oldmode = mmu_enabled ? 1 : 0;
xfree (debug_mem_banks);
debug_mem_banks = NULL;
@ -2339,14 +2438,14 @@ static int deinitialize_memwatch (void)
static void initialize_memwatch (int mode)
{
membank_total = currprefs.address_space_24 ? 256 : 65536;
deinitialize_memwatch ();
debug_mem_banks = xcalloc (addrbank*, membank_total);
debug_mem_area = xcalloc (addrbank, membank_total);
membank_stores = xcalloc (struct membank_store, MEMWATCH_STORE_SLOTS);
#if 0
int i, j, as;
addrbank *a1, *a2, *oa;
deinitialize_memwatch ();
as = currprefs.address_space_24 ? 256 : 65536;
debug_mem_banks = xmalloc (addrbank*, as);
debug_mem_area = xmalloc (addrbank, as);
membank_stores = xcalloc (struct membank_store, 32);
oa = NULL;
for (i = 0; i < as; i++) {
a1 = debug_mem_banks[i] = debug_mem_area + i;
@ -2376,6 +2475,7 @@ static void initialize_memwatch (int mode)
a2->wgeti = mode ? mmu_wgeti : debug_wgeti;
a2->lgeti = mode ? mmu_lgeti : debug_lgeti;
}
#endif
if (mode)
mmu_enabled = 1;
else
@ -2510,6 +2610,7 @@ static void memwatch (TCHAR **c)
ignore_ws (c);
if (!more_params (c)) {
console_out_f (_T("Memwatch %d removed\n"), num);
memwatch_setup ();
return;
}
mwn->addr = readhex (c);
@ -2557,6 +2658,7 @@ static void memwatch (TCHAR **c)
}
if (mwn->frozen && mwn->rwi == 0)
mwn->rwi = 3;
memwatch_setup ();
memwatch_dump (num);
}

48
enforcer.cpp
View File

@ -423,9 +423,9 @@ uae_u32 REGPARAM2 chipmem_lget2 (uaecptr addr)
{
uae_u32 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_LONG (addr))
{
@ -440,9 +440,9 @@ uae_u32 REGPARAM2 chipmem_wget2(uaecptr addr)
{
uae_u16 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_WORD (addr))
{
@ -455,8 +455,8 @@ uae_u32 REGPARAM2 chipmem_wget2(uaecptr addr)
uae_u32 REGPARAM2 chipmem_bget2 (uaecptr addr)
{
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (ISILLEGAL_BYTE (addr))
{
@ -465,16 +465,16 @@ uae_u32 REGPARAM2 chipmem_bget2 (uaecptr addr)
set_special (SPCFLAG_TRAP);
}
return chipmemory[addr];
return chipmem_bank.baseaddr[addr];
}
void REGPARAM2 chipmem_lput2 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u32 *)(chipmemory + addr);
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_LONG (addr))
{
@ -492,9 +492,9 @@ void REGPARAM2 chipmem_wput2 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
m = (uae_u16 *)(chipmemory + addr);
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_WORD (addr))
{
@ -509,8 +509,8 @@ void REGPARAM2 chipmem_wput2 (uaecptr addr, uae_u32 w)
void REGPARAM2 chipmem_bput2 (uaecptr addr, uae_u32 b)
{
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (ISILLEGAL_BYTE (addr))
{
@ -520,21 +520,21 @@ void REGPARAM2 chipmem_bput2 (uaecptr addr, uae_u32 b)
}
if (ISEXEC (addr))
return;
chipmemory[addr] = b;
chipmem_bank.baseaddr[addr] = b;
}
int REGPARAM2 chipmem_check2 (uaecptr addr, uae_u32 size)
{
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
return (addr + size) <= allocated_chipmem;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
return (addr + size) <= chipmem_bank.allocated;
}
uae_u8 * REGPARAM2 chipmem_xlate2 (uaecptr addr)
{
addr -= chipmem_start & chipmem_mask;
addr &= chipmem_mask;
return chipmemory + addr;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
return chipmem_bank.baseaddr + addr;
}
uae_u32 REGPARAM2 dummy_lget2 (uaecptr addr)

602
expansion.cpp
View File

@ -370,17 +370,17 @@ static void REGPARAM2 expamem_wput (uaecptr addr, uae_u32 value)
p2 = 0;
while (!p2 && z3num < 2) {
if (z3num == 0 && currprefs.z3fastmem_size)
p2 = z3fastmem_start >> 16;
p2 = z3fastmem_bank.start >> 16;
else if (z3num == 1 && currprefs.z3fastmem2_size)
p2 = z3fastmem2_start >> 16;
p2 = z3fastmem2_bank.start >> 16;
if (!p2)
z3num++;
}
z3num++;
} else {
// Z3 P96 RAM
if (p96ram_start & 0xff000000)
p2 = p96ram_start >> 16;
if (gfxmem_bank.start & 0xff000000)
p2 = gfxmem_bank.start >> 16;
}
put_word (regs.regs[11] + 0x20, p2);
put_word (regs.regs[11] + 0x28, p2);
@ -480,83 +480,8 @@ static void expamem_init_cd32fmv (void)
* Fast Memory
*/
static uae_u32 fastmem_mask;
static uae_u32 REGPARAM3 fastmem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 fastmem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 fastmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 fastmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 fastmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 fastmem_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 fastmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 fastmem_xlate (uaecptr addr) REGPARAM;
uaecptr fastmem_start; /* Determined by the OS */
static uae_u8 *fastmemory;
static uae_u32 REGPARAM2 fastmem_lget (uaecptr addr)
{
uae_u8 *m;
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
m = fastmemory + addr;
return do_get_mem_long ((uae_u32 *)m);
}
static uae_u32 REGPARAM2 fastmem_wget (uaecptr addr)
{
uae_u8 *m;
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
m = fastmemory + addr;
return do_get_mem_word ((uae_u16 *)m);
}
static uae_u32 REGPARAM2 fastmem_bget (uaecptr addr)
{
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
return fastmemory[addr];
}
static void REGPARAM2 fastmem_lput (uaecptr addr, uae_u32 l)
{
uae_u8 *m;
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
m = fastmemory + addr;
do_put_mem_long ((uae_u32 *)m, l);
}
static void REGPARAM2 fastmem_wput (uaecptr addr, uae_u32 w)
{
uae_u8 *m;
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
m = fastmemory + addr;
do_put_mem_word ((uae_u16 *)m, w);
}
static void REGPARAM2 fastmem_bput (uaecptr addr, uae_u32 b)
{
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
fastmemory[addr] = b;
}
static int REGPARAM2 fastmem_check (uaecptr addr, uae_u32 size)
{
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
return (addr + size) <= allocated_fastmem;
}
static uae_u8 *REGPARAM2 fastmem_xlate (uaecptr addr)
{
addr -= fastmem_start & fastmem_mask;
addr &= fastmem_mask;
return fastmemory + addr;
}
MEMORY_FUNCTIONS(fastmem);
addrbank fastmem_bank = {
fastmem_lget, fastmem_wget, fastmem_bget,
@ -795,182 +720,9 @@ static addrbank filesys_bank = {
* Z3fastmem Memory
*/
static uae_u32 z3fastmem_mask, z3fastmem2_mask, z3chipmem_mask;
uaecptr z3fastmem_start, z3fastmem2_start, z3chipmem_start;
static uae_u8 *z3fastmem, *z3fastmem2, *z3chipmem;
static uae_u32 REGPARAM2 z3fastmem_lget (uaecptr addr)
{
uae_u8 *m;
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
m = z3fastmem + addr;
return do_get_mem_long ((uae_u32 *)m);
}
static uae_u32 REGPARAM2 z3fastmem_wget (uaecptr addr)
{
uae_u8 *m;
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
m = z3fastmem + addr;
return do_get_mem_word ((uae_u16 *)m);
}
static uae_u32 REGPARAM2 z3fastmem_bget (uaecptr addr)
{
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
return z3fastmem[addr];
}
static void REGPARAM2 z3fastmem_lput (uaecptr addr, uae_u32 l)
{
uae_u8 *m;
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
m = z3fastmem + addr;
do_put_mem_long ((uae_u32 *)m, l);
}
static void REGPARAM2 z3fastmem_wput (uaecptr addr, uae_u32 w)
{
uae_u8 *m;
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
m = z3fastmem + addr;
do_put_mem_word ((uae_u16 *)m, w);
}
static void REGPARAM2 z3fastmem_bput (uaecptr addr, uae_u32 b)
{
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
z3fastmem[addr] = b;
}
static int REGPARAM2 z3fastmem_check (uaecptr addr, uae_u32 size)
{
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
return (addr + size) <= allocated_z3fastmem;
}
static uae_u8 *REGPARAM2 z3fastmem_xlate (uaecptr addr)
{
addr -= z3fastmem_start & z3fastmem_mask;
addr &= z3fastmem_mask;
return z3fastmem + addr;
}
static uae_u32 REGPARAM2 z3fastmem2_lget (uaecptr addr)
{
uae_u8 *m;
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
m = z3fastmem2 + addr;
return do_get_mem_long ((uae_u32 *)m);
}
static uae_u32 REGPARAM2 z3fastmem2_wget (uaecptr addr)
{
uae_u8 *m;
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
m = z3fastmem2 + addr;
return do_get_mem_word ((uae_u16 *)m);
}
static uae_u32 REGPARAM2 z3fastmem2_bget (uaecptr addr)
{
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
return z3fastmem2[addr];
}
static void REGPARAM2 z3fastmem2_lput (uaecptr addr, uae_u32 l)
{
uae_u8 *m;
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
m = z3fastmem2 + addr;
do_put_mem_long ((uae_u32 *)m, l);
}
static void REGPARAM2 z3fastmem2_wput (uaecptr addr, uae_u32 w)
{
uae_u8 *m;
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
m = z3fastmem2 + addr;
do_put_mem_word ((uae_u16 *)m, w);
}
static void REGPARAM2 z3fastmem2_bput (uaecptr addr, uae_u32 b)
{
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
z3fastmem2[addr] = b;
}
static int REGPARAM2 z3fastmem2_check (uaecptr addr, uae_u32 size)
{
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
return (addr + size) <= allocated_z3fastmem2;
}
static uae_u8 *REGPARAM2 z3fastmem2_xlate (uaecptr addr)
{
addr -= z3fastmem2_start & z3fastmem2_mask;
addr &= z3fastmem2_mask;
return z3fastmem2 + addr;
}
static uae_u32 REGPARAM2 z3chipmem_lget (uaecptr addr)
{
uae_u8 *m;
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
m = z3chipmem + addr;
return do_get_mem_long ((uae_u32 *)m);
}
static uae_u32 REGPARAM2 z3chipmem_wget (uaecptr addr)
{
uae_u8 *m;
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
m = z3chipmem + addr;
return do_get_mem_word ((uae_u16 *)m);
}
static uae_u32 REGPARAM2 z3chipmem_bget (uaecptr addr)
{
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
return z3chipmem[addr];
}
static void REGPARAM2 z3chipmem_lput (uaecptr addr, uae_u32 l)
{
uae_u8 *m;
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
m = z3chipmem + addr;
do_put_mem_long ((uae_u32 *)m, l);
}
static void REGPARAM2 z3chipmem_wput (uaecptr addr, uae_u32 w)
{
uae_u8 *m;
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
m = z3chipmem + addr;
do_put_mem_word ((uae_u16 *)m, w);
}
static void REGPARAM2 z3chipmem_bput (uaecptr addr, uae_u32 b)
{
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
z3chipmem[addr] = b;
}
static int REGPARAM2 z3chipmem_check (uaecptr addr, uae_u32 size)
{
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
return (addr + size) <= allocated_z3chipmem;
}
static uae_u8 *REGPARAM2 z3chipmem_xlate (uaecptr addr)
{
addr -= z3chipmem_start & z3chipmem_mask;
addr &= z3chipmem_mask;
return z3chipmem + addr;
}
MEMORY_FUNCTIONS(z3fastmem);
MEMORY_FUNCTIONS(z3fastmem2);
MEMORY_FUNCTIONS(z3chipmem);
addrbank z3fastmem_bank = {
z3fastmem_lget, z3fastmem_wget, z3fastmem_bget,
@ -992,9 +744,6 @@ addrbank z3chipmem_bank = {
};
/* Z3-based UAEGFX-card */
uae_u32 gfxmem_mask; /* for memory.c */
uae_u8 *gfxmemory;
uae_u32 gfxmem_start;
/* ********************************************************** */
@ -1004,10 +753,10 @@ uae_u32 gfxmem_start;
static void expamem_map_fastcard (void)
{
fastmem_start = ((expamem_hi | (expamem_lo >> 4)) << 16);
if (fastmem_start) {
map_banks (&fastmem_bank, fastmem_start >> 16, allocated_fastmem >> 16, 0);
write_log (_T("Fastcard: mapped @$%lx: %dMB fast memory\n"), fastmem_start, allocated_fastmem >> 20);
fastmem_bank.start = ((expamem_hi | (expamem_lo >> 4)) << 16);
if (fastmem_bank.start) {
map_banks (&fastmem_bank, fastmem_bank.start >> 16, fastmem_bank.allocated >> 16, 0);
write_log (_T("Fastcard: mapped @$%lx: %dMB fast memory\n"), fastmem_bank.start, fastmem_bank.allocated >> 20);
}
}
@ -1017,13 +766,13 @@ static void expamem_init_fastcard (void)
uae_u8 pid = (currprefs.cs_a2091 || currprefs.uae_hide) ? commodore_a2091_ram : (currprefs.maprom ? 1 : 81);
expamem_init_clear ();
if (allocated_fastmem == 0x100000)
if (fastmem_bank.allocated == 0x100000)
expamem_write (0x00, Z2_MEM_1MB + add_memory + zorroII);
else if (allocated_fastmem == 0x200000)
else if (fastmem_bank.allocated == 0x200000)
expamem_write (0x00, Z2_MEM_2MB + add_memory + zorroII);
else if (allocated_fastmem == 0x400000)
else if (fastmem_bank.allocated == 0x400000)
expamem_write (0x00, Z2_MEM_4MB + add_memory + zorroII);
else if (allocated_fastmem == 0x800000)
else if (fastmem_bank.allocated == 0x800000)
expamem_write (0x00, Z2_MEM_8MB + add_memory + zorroII);
expamem_write (0x08, care_addr);
@ -1134,11 +883,11 @@ static void expamem_map_z3fastmem_2 (addrbank *bank, uaecptr *startp, uae_u32 si
static void expamem_map_z3fastmem (void)
{
expamem_map_z3fastmem_2 (&z3fastmem_bank, &z3fastmem_start, currprefs.z3fastmem_size, allocated_z3fastmem, 0);
expamem_map_z3fastmem_2 (&z3fastmem_bank, &z3fastmem_bank.start, currprefs.z3fastmem_size, z3fastmem_bank.allocated, 0);
}
static void expamem_map_z3fastmem2 (void)
{
expamem_map_z3fastmem_2 (&z3fastmem2_bank, &z3fastmem2_start, currprefs.z3fastmem2_size, allocated_z3fastmem2, 0);
expamem_map_z3fastmem_2 (&z3fastmem2_bank, &z3fastmem2_bank.start, currprefs.z3fastmem2_size, z3fastmem2_bank.allocated, 0);
}
static void expamem_init_z3fastmem_2 (addrbank *bank, uae_u32 start, uae_u32 size, uae_u32 allocated)
@ -1188,11 +937,11 @@ static void expamem_init_z3fastmem_2 (addrbank *bank, uae_u32 start, uae_u32 siz
}
static void expamem_init_z3fastmem (void)
{
expamem_init_z3fastmem_2 (&z3fastmem_bank, z3fastmem_start, currprefs.z3fastmem_size, allocated_z3fastmem);
expamem_init_z3fastmem_2 (&z3fastmem_bank, z3fastmem_bank.start, currprefs.z3fastmem_size, z3fastmem_bank.allocated);
}
static void expamem_init_z3fastmem2 (void)
{
expamem_init_z3fastmem_2 (&z3fastmem2_bank, z3fastmem2_start, currprefs.z3fastmem2_size, allocated_z3fastmem2);
expamem_init_z3fastmem_2 (&z3fastmem2_bank, z3fastmem2_bank.start, currprefs.z3fastmem2_size, z3fastmem2_bank.allocated);
}
#ifdef PICASSO96
@ -1200,43 +949,41 @@ static void expamem_init_z3fastmem2 (void)
* Fake Graphics Card (ZORRO III) - BDK
*/
uaecptr p96ram_start;
static void expamem_map_gfxcard (void)
{
gfxmem_start = (expamem_hi | (expamem_lo >> 4)) << 16;
if (gfxmem_start) {
map_banks (&gfxmem_bank, gfxmem_start >> 16, allocated_gfxmem >> 16, allocated_gfxmem);
write_log (_T("%sUAEGFX-card: mapped @$%lx, %d MB RTG RAM\n"), currprefs.rtgmem_type ? _T("Z3") : _T("Z2"), gfxmem_start, allocated_gfxmem / 0x100000);
gfxmem_bank.start = (expamem_hi | (expamem_lo >> 4)) << 16;
if (gfxmem_bank.start) {
map_banks (&gfxmem_bank, gfxmem_bank.start >> 16, gfxmem_bank.allocated >> 16, gfxmem_bank.allocated);
write_log (_T("%sUAEGFX-card: mapped @$%lx, %d MB RTG RAM\n"), currprefs.rtgmem_type ? _T("Z3") : _T("Z2"), gfxmem_bank.baseaddr, gfxmem_bank.allocated / 0x100000);
}
}
static void expamem_init_gfxcard (bool z3)
{
int code = (allocated_gfxmem == 0x100000 ? Z2_MEM_1MB
: allocated_gfxmem == 0x200000 ? Z2_MEM_2MB
: allocated_gfxmem == 0x400000 ? Z2_MEM_4MB
: allocated_gfxmem == 0x800000 ? Z2_MEM_8MB
: allocated_gfxmem == 0x1000000 ? Z3_MEM_16MB
: allocated_gfxmem == 0x2000000 ? Z3_MEM_32MB
: allocated_gfxmem == 0x4000000 ? Z3_MEM_64MB
: allocated_gfxmem == 0x8000000 ? Z3_MEM_128MB
: allocated_gfxmem == 0x10000000 ? Z3_MEM_256MB
: allocated_gfxmem == 0x20000000 ? Z3_MEM_512MB
int code = (gfxmem_bank.allocated == 0x100000 ? Z2_MEM_1MB
: gfxmem_bank.allocated == 0x200000 ? Z2_MEM_2MB
: gfxmem_bank.allocated == 0x400000 ? Z2_MEM_4MB
: gfxmem_bank.allocated == 0x800000 ? Z2_MEM_8MB
: gfxmem_bank.allocated == 0x1000000 ? Z3_MEM_16MB
: gfxmem_bank.allocated == 0x2000000 ? Z3_MEM_32MB
: gfxmem_bank.allocated == 0x4000000 ? Z3_MEM_64MB
: gfxmem_bank.allocated == 0x8000000 ? Z3_MEM_128MB
: gfxmem_bank.allocated == 0x10000000 ? Z3_MEM_256MB
: gfxmem_bank.allocated == 0x20000000 ? Z3_MEM_512MB
: Z3_MEM_1GB);
int subsize = (allocated_gfxmem == 0x100000 ? Z3_SS_MEM_1MB
: allocated_gfxmem == 0x200000 ? Z3_SS_MEM_2MB
: allocated_gfxmem == 0x400000 ? Z3_SS_MEM_4MB
: allocated_gfxmem == 0x800000 ? Z3_SS_MEM_8MB
int subsize = (gfxmem_bank.allocated == 0x100000 ? Z3_SS_MEM_1MB
: gfxmem_bank.allocated == 0x200000 ? Z3_SS_MEM_2MB
: gfxmem_bank.allocated == 0x400000 ? Z3_SS_MEM_4MB
: gfxmem_bank.allocated == 0x800000 ? Z3_SS_MEM_8MB
: Z3_SS_MEM_SAME);
if (allocated_gfxmem < 0x1000000 && z3)
if (gfxmem_bank.allocated < 0x1000000 && z3)
code = Z3_MEM_16MB; /* Z3 physical board size is always at least 16M */
expamem_init_clear ();
expamem_write (0x00, (z3 ? zorroIII : zorroII) | code);
expamem_write (0x08, care_addr | (z3 ? (force_z3 | (allocated_gfxmem > 0x800000 ? ext_size: subsize)) : 0));
expamem_write (0x08, care_addr | (z3 ? (force_z3 | (gfxmem_bank.allocated > 0x800000 ? ext_size: subsize)) : 0));
expamem_write (0x04, 96);
expamem_write (0x10, uae_id >> 8);
@ -1269,18 +1016,18 @@ static size_t fast_filepos, z3_filepos, z3_filepos2, z3_fileposchip, p96_filepos
void free_fastmemory (void)
{
if (fastmemory)
mapped_free (fastmemory);
fastmemory = 0;
if (fastmem_bank.baseaddr)
mapped_free (fastmem_bank.baseaddr);
fastmem_bank.baseaddr = 0;
}
static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, uae_u8 **memory, uae_u32 *allocated, uae_u32 *mask, int max, const TCHAR *name)
static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, addrbank *bank, int max, const TCHAR *name)
{
int alloc = *currpsize;
*allocated = 0;
*memory = NULL;
*mask = 0;
bank->allocated = 0;
bank->baseaddr = NULL;
bank->mask = 0;
if (!alloc)
return false;
@ -1288,11 +1035,11 @@ static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, ua
while (alloc >= max * 1024 * 1024) {
uae_u8 *mem = mapped_malloc (alloc, name);
if (mem) {
*memory = mem;
bank->baseaddr = mem;
*currpsize = alloc;
*changedpsize = alloc;
*mask = alloc - 1;
*allocated = alloc;
bank->mask = alloc - 1;
bank->allocated = alloc;
return true;
}
write_log (_T("Out of memory for %s, %d bytes.\n"), name, alloc);
@ -1313,100 +1060,92 @@ static void allocate_expamem (void)
currprefs.rtgmem_type = changed_prefs.rtgmem_type;
currprefs.z3chipmem_size = changed_prefs.z3chipmem_size;
z3chipmem_start = currprefs.z3fastmem_start;
z3fastmem_start = currprefs.z3fastmem_start;
z3chipmem_bank.start = currprefs.z3fastmem_start;
z3fastmem_bank.start = currprefs.z3fastmem_start;
if (currprefs.z3chipmem_size)
z3fastmem_start += currprefs.z3chipmem_size + 16 * 1024 * 1024;
z3fastmem2_start = z3fastmem_start + currprefs.z3fastmem_size;
z3fastmem_bank.start += currprefs.z3chipmem_size + 16 * 1024 * 1024;
z3fastmem2_bank.start = z3fastmem_bank.start + currprefs.z3fastmem_size;
if (allocated_fastmem != currprefs.fastmem_size) {
if (fastmem_bank.allocated != currprefs.fastmem_size) {
free_fastmemory ();
allocated_fastmem = currprefs.fastmem_size;
fastmem_mask = allocated_fastmem - 1;
fastmem_bank.allocated = currprefs.fastmem_size;
fastmem_bank.mask = fastmem_bank.allocated - 1;
if (allocated_fastmem) {
fastmemory = mapped_malloc (allocated_fastmem, _T("fast"));
if (fastmemory == 0) {
if (fastmem_bank.allocated) {
fastmem_bank.baseaddr = mapped_malloc (fastmem_bank.allocated, _T("fast"));
if (fastmem_bank.baseaddr == 0) {
write_log (_T("Out of memory for fastmem card.\n"));
allocated_fastmem = 0;
fastmem_bank.allocated = 0;
}
}
memory_hardreset (1);
}
if (allocated_z3fastmem != currprefs.z3fastmem_size) {
if (z3fastmem)
mapped_free (z3fastmem);
mapped_malloc_dynamic (&currprefs.z3fastmem_size, &changed_prefs.z3fastmem_size, &z3fastmem, &allocated_z3fastmem, &z3fastmem_mask, 1, _T("z3"));
if (z3fastmem_bank.allocated != currprefs.z3fastmem_size) {
if (z3fastmem_bank.baseaddr)
mapped_free (z3fastmem_bank.baseaddr);
mapped_malloc_dynamic (&currprefs.z3fastmem_size, &changed_prefs.z3fastmem_size, &z3fastmem_bank, 1, _T("z3"));
memory_hardreset (1);
}
if (allocated_z3fastmem2 != currprefs.z3fastmem2_size) {
if (z3fastmem2)
mapped_free (z3fastmem2);
z3fastmem2 = 0;
if (z3fastmem2_bank.allocated != currprefs.z3fastmem2_size) {
if (z3fastmem2_bank.baseaddr)
mapped_free (z3fastmem2_bank.baseaddr);
z3fastmem2_bank.baseaddr = 0;
allocated_z3fastmem2 = currprefs.z3fastmem2_size;
z3fastmem2_mask = allocated_z3fastmem2 - 1;
z3fastmem2_bank.allocated = currprefs.z3fastmem2_size;
z3fastmem2_bank.mask = z3fastmem2_bank.allocated - 1;
if (allocated_z3fastmem2) {
z3fastmem2 = mapped_malloc (allocated_z3fastmem2, _T("z3_2"));
if (z3fastmem2 == 0) {
if (z3fastmem2_bank.allocated) {
z3fastmem2_bank.baseaddr = mapped_malloc (z3fastmem2_bank.allocated, _T("z3_2"));
if (z3fastmem2_bank.baseaddr == 0) {
write_log (_T("Out of memory for 32 bit fast memory #2.\n"));
allocated_z3fastmem2 = 0;
z3fastmem2_bank.allocated = 0;
}
}
memory_hardreset (1);
}
if (allocated_z3chipmem != currprefs.z3chipmem_size) {
if (z3chipmem)
mapped_free (z3chipmem);
mapped_malloc_dynamic (&currprefs.z3chipmem_size, &changed_prefs.z3chipmem_size, &z3chipmem, &allocated_z3chipmem, &z3chipmem_mask, 16, _T("z3_chip"));
if (z3chipmem_bank.allocated != currprefs.z3chipmem_size) {
if (z3chipmem_bank.baseaddr)
mapped_free (z3chipmem_bank.baseaddr);
mapped_malloc_dynamic (&currprefs.z3chipmem_size, &changed_prefs.z3chipmem_size, &z3chipmem_bank, 16, _T("z3_chip"));
memory_hardreset (1);
}
#ifdef PICASSO96
if (allocated_gfxmem != currprefs.rtgmem_size) {
if (gfxmemory)
mapped_free (gfxmemory);
mapped_malloc_dynamic (&currprefs.rtgmem_size, &changed_prefs.rtgmem_size, &gfxmemory, &allocated_gfxmem, &gfxmem_mask, 1, currprefs.rtgmem_type ? _T("z3_gfx") : _T("z2_gfx"));
if (gfxmem_bank.allocated != currprefs.rtgmem_size) {
if (gfxmem_bank.baseaddr)
mapped_free (gfxmem_bank.baseaddr);
mapped_malloc_dynamic (&currprefs.rtgmem_size, &changed_prefs.rtgmem_size, &gfxmem_bank, 1, currprefs.rtgmem_type ? _T("z3_gfx") : _T("z2_gfx"));
memory_hardreset (1);
}
#endif
z3fastmem_bank.baseaddr = z3fastmem;
z3fastmem2_bank.baseaddr = z3fastmem2;
z3chipmem_bank.baseaddr = z3chipmem;
fastmem_bank.baseaddr = fastmemory;
#ifdef PICASSO96
gfxmem_bank.baseaddr = gfxmemory;
#endif
#ifdef SAVESTATE
if (savestate_state == STATE_RESTORE) {
if (allocated_fastmem > 0) {
restore_ram (fast_filepos, fastmemory);
map_banks (&fastmem_bank, fastmem_start >> 16, currprefs.fastmem_size >> 16,
allocated_fastmem);
if (fastmem_bank.allocated > 0) {
restore_ram (fast_filepos, fastmem_bank.baseaddr);
map_banks (&fastmem_bank, fastmem_bank.start >> 16, currprefs.fastmem_size >> 16,
fastmem_bank.allocated);
}
if (allocated_z3fastmem > 0) {
restore_ram (z3_filepos, z3fastmem);
map_banks (&z3fastmem_bank, z3fastmem_start >> 16, currprefs.z3fastmem_size >> 16,
allocated_z3fastmem);
if (z3fastmem_bank.allocated > 0) {
restore_ram (z3_filepos, z3fastmem_bank.baseaddr);
map_banks (&z3fastmem_bank, z3fastmem_bank.start >> 16, currprefs.z3fastmem_size >> 16,
z3fastmem_bank.allocated);
}
if (allocated_z3fastmem2 > 0) {
restore_ram (z3_filepos2, z3fastmem2);
map_banks (&z3fastmem2_bank, z3fastmem2_start >> 16, currprefs.z3fastmem2_size >> 16,
allocated_z3fastmem2);
if (z3fastmem2_bank.allocated > 0) {
restore_ram (z3_filepos2, z3fastmem2_bank.baseaddr);
map_banks (&z3fastmem2_bank, z3fastmem2_bank.start >> 16, currprefs.z3fastmem2_size >> 16,
z3fastmem2_bank.allocated);
}
if (allocated_z3chipmem > 0) {
restore_ram (z3_fileposchip, z3chipmem);
map_banks (&z3chipmem_bank, z3chipmem_start >> 16, currprefs.z3chipmem_size >> 16,
allocated_z3fastmem2);
if (z3chipmem_bank.allocated > 0) {
restore_ram (z3_fileposchip, z3chipmem_bank.baseaddr);
map_banks (&z3chipmem_bank, z3chipmem_bank.start >> 16, currprefs.z3chipmem_size >> 16,
z3chipmem_bank.allocated);
}
#ifdef PICASSO96
if (allocated_gfxmem > 0 && gfxmem_start > 0) {
restore_ram (p96_filepos, gfxmemory);
map_banks (&gfxmem_bank, gfxmem_start >> 16, currprefs.rtgmem_size >> 16,
allocated_gfxmem);
if (gfxmem_bank.allocated > 0 && gfxmem_bank.start > 0) {
restore_ram (p96_filepos, gfxmem_bank.baseaddr);
map_banks (&gfxmem_bank, gfxmem_bank.start >> 16, currprefs.rtgmem_size >> 16,
gfxmem_bank.allocated);
}
#endif
}
@ -1507,8 +1246,8 @@ static void expamem_init_gfxboard_registers (void)
void p96memstart (void)
{
/* make sure there is always empty space between Z3 and P96 RAM */
p96ram_start = currprefs.z3fastmem_start + ((currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size + 0xffffff) & ~0xffffff);
if (p96ram_start == currprefs.z3fastmem_start + currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size &&
p96ram_start = currprefs.z3fastmem_bank.start + ((currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size + 0xffffff) & ~0xffffff);
if (p96ram_start == currprefs.z3fastmem_bank.start + currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size &&
(currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size < 512 * 1024 * 1024 || currprefs.rtgmem_size < 128 * 1024 * 1024))
p96ram_start += 0x1000000;
}
@ -1542,7 +1281,7 @@ void expamem_reset (void)
}
if (need_uae_boot_rom () == 0)
do_mount = 0;
if (fastmemory != NULL && currprefs.chipmem_size <= 2 * 1024 * 1024) {
if (fastmem_bank.baseaddr != NULL && currprefs.chipmem_size <= 2 * 1024 * 1024) {
if (currprefs.fastmem_autoconfig) {
fastmem_bank.name = _T("Fast memory");
card_name[cardno] = _T("Z2Fast");
@ -1550,7 +1289,7 @@ void expamem_reset (void)
card_map[cardno++] = expamem_map_fastcard;
} else {
fastmem_bank.name = _T("Fast memory (non-autoconfig)");
map_banks (&fastmem_bank, 0x00200000 >> 16, allocated_fastmem >> 16, 0);
map_banks (&fastmem_bank, 0x00200000 >> 16, fastmem_bank.allocated >> 16, 0);
}
}
@ -1601,7 +1340,7 @@ void expamem_reset (void)
}
#endif
#ifdef PICASSO96
if (currprefs.rtgmem_type == GFXBOARD_UAE_Z2 && gfxmemory != NULL) {
if (currprefs.rtgmem_type == GFXBOARD_UAE_Z2 && gfxmem_bank.baseaddr != NULL) {
card_name[cardno] = _T("Z2RTG");
card_init[cardno] = expamem_init_gfxcard_z2;
card_map[cardno++] = expamem_map_gfxcard;
@ -1621,21 +1360,21 @@ void expamem_reset (void)
#endif
/* Z3 boards last */
if (z3fastmem != NULL) {
if (z3fastmem_bank.baseaddr != NULL) {
z3num = 0;
card_name[cardno] = _T("Z3Fast");
card_init[cardno] = expamem_init_z3fastmem;
card_map[cardno++] = expamem_map_z3fastmem;
map_banks (&z3fastmem_bank, z3fastmem_start >> 16, currprefs.z3fastmem_size >> 16, allocated_z3fastmem);
if (z3fastmem2 != NULL) {
map_banks (&z3fastmem_bank, z3fastmem_bank.start >> 16, currprefs.z3fastmem_size >> 16, z3fastmem_bank.allocated);
if (z3fastmem2_bank.baseaddr != NULL) {
card_name[cardno] = _T("Z3Fast2");
card_init[cardno] = expamem_init_z3fastmem2;
card_map[cardno++] = expamem_map_z3fastmem2;
map_banks (&z3fastmem2_bank, z3fastmem2_start >> 16, currprefs.z3fastmem2_size >> 16, allocated_z3fastmem2);
map_banks (&z3fastmem2_bank, z3fastmem2_bank.start >> 16, currprefs.z3fastmem2_size >> 16, z3fastmem2_bank.allocated);
}
}
if (z3chipmem != NULL)
map_banks (&z3chipmem_bank, z3chipmem_start >> 16, currprefs.z3chipmem_size >> 16, allocated_z3chipmem);
if (z3chipmem_bank.baseaddr != NULL)
map_banks (&z3chipmem_bank, z3chipmem_bank.start >> 16, currprefs.z3chipmem_size >> 16, z3chipmem_bank.allocated);
#ifdef NCR
if (currprefs.cs_a4091) {
card_name[cardno] = _T("A4091");
@ -1644,7 +1383,7 @@ void expamem_reset (void)
}
#endif
#ifdef PICASSO96
if (currprefs.rtgmem_type == GFXBOARD_UAE_Z3 && gfxmemory != NULL) {
if (currprefs.rtgmem_type == GFXBOARD_UAE_Z3 && gfxmem_bank.baseaddr != NULL) {
card_name[cardno] = _T("Z3RTG");
card_init[cardno] = expamem_init_gfxcard_z3;
card_map[cardno++] = expamem_map_gfxcard;
@ -1676,29 +1415,29 @@ void expansion_init (void)
{
if (savestate_state != STATE_RESTORE) {
allocated_fastmem = 0;
fastmem_mask = fastmem_start = 0;
fastmemory = 0;
fastmem_bank.allocated = 0;
fastmem_bank.mask = fastmem_bank.start = 0;
fastmem_bank.baseaddr = NULL;
#ifdef PICASSO96
allocated_gfxmem = 0;
gfxmem_mask = gfxmem_start = 0;
gfxmemory = 0;
gfxmem_bank.allocated = 0;
gfxmem_bank.mask = gfxmem_bank.start = 0;
gfxmem_bank.baseaddr = NULL;
#endif
#ifdef CATWEASEL
catweasel_mask = catweasel_start = 0;
#endif
allocated_z3fastmem = 0;
z3fastmem_mask = z3fastmem_start = 0;
z3fastmem = 0;
allocated_z3fastmem2 = 0;
z3fastmem2_mask = z3fastmem2_start = 0;
z3fastmem2 = 0;
allocated_z3chipmem = 0;
z3chipmem_mask = z3chipmem_start = 0;
z3chipmem = 0;
z3fastmem_bank.allocated = 0;
z3fastmem_bank.mask = z3fastmem_bank.start = 0;
z3fastmem_bank.baseaddr = NULL;
z3fastmem2_bank.allocated = 0;
z3fastmem2_bank.mask = z3fastmem2_bank.start = 0;
z3fastmem2_bank.baseaddr = NULL;
z3chipmem_bank.allocated = 0;
z3chipmem_bank.mask = z3chipmem_bank.start = 0;
z3chipmem_bank.baseaddr = NULL;
}
#ifdef FILESYS
@ -1720,30 +1459,23 @@ void expansion_init (void)
void expansion_cleanup (void)
{
if (fastmemory)
mapped_free (fastmemory);
fastmemory = 0;
if (z3fastmem)
mapped_free (z3fastmem);
z3fastmem = 0;
if (z3fastmem2)
mapped_free (z3fastmem2);
z3fastmem2 = 0;
if (z3chipmem)
mapped_free (z3chipmem);
z3chipmem = 0;
mapped_free (fastmem_bank.baseaddr);
fastmem_bank.baseaddr = NULL;
mapped_free (z3fastmem_bank.baseaddr);
z3fastmem_bank.baseaddr = NULL;
mapped_free (z3fastmem2_bank.baseaddr);
z3fastmem2_bank.baseaddr = NULL;
mapped_free (z3chipmem_bank.baseaddr);
z3chipmem_bank.baseaddr = NULL;
#ifdef PICASSO96
if (gfxmemory)
mapped_free (gfxmemory);
gfxmemory = 0;
mapped_free (gfxmem_bank.baseaddr);
gfxmem_bank.baseaddr = NULL;
#endif
#ifdef FILESYS
if (filesysory)
mapped_free (filesysory);
filesysory = 0;
mapped_free (filesysory);
filesysory = NULL;
#endif
#ifdef CATWEASEL
@ -1751,18 +1483,20 @@ void expansion_cleanup (void)
#endif
}
static void clear_bank (addrbank *ab)
{
if (!ab->baseaddr || !ab->allocated)
return;
memset (ab->baseaddr, 0, ab->allocated > 0x800000 ? 0x800000 : ab->allocated);
}
void expansion_clear (void)
{
if (fastmemory)
memset (fastmemory, 0, allocated_fastmem);
if (z3fastmem)
memset (z3fastmem, 0, allocated_z3fastmem > 0x800000 ? 0x800000 : allocated_z3fastmem);
if (z3fastmem2)
memset (z3fastmem2, 0, allocated_z3fastmem2 > 0x800000 ? 0x800000 : allocated_z3fastmem2);
if (z3chipmem)
memset (z3chipmem, 0, allocated_z3chipmem > 0x800000 ? 0x800000 : allocated_z3chipmem);
if (gfxmemory)
memset (gfxmemory, 0, allocated_gfxmem);
clear_bank (&fastmem_bank);
clear_bank (&z3fastmem_bank);
clear_bank (&z3fastmem2_bank);
clear_bank (&z3chipmem_bank);
clear_bank (&gfxmem_bank);
}
#ifdef SAVESTATE
@ -1771,24 +1505,24 @@ void expansion_clear (void)
uae_u8 *save_fram (int *len)
{
*len = allocated_fastmem;
return fastmemory;
*len = fastmem_bank.allocated;
return fastmem_bank.baseaddr;
}
uae_u8 *save_zram (int *len, int num)
{
if (num < 0) {
*len = allocated_z3chipmem;
return z3chipmem;
*len = z3chipmem_bank.allocated;
return z3chipmem_bank.baseaddr;
}
*len = num ? allocated_z3fastmem2 : allocated_z3fastmem;
return num ? z3fastmem2 : z3fastmem;
*len = num ? z3fastmem2_bank.allocated : z3fastmem_bank.allocated;
return num ? z3fastmem2_bank.baseaddr : z3fastmem_bank.baseaddr;
}
uae_u8 *save_pram (int *len)
{
*len = allocated_gfxmem;
return gfxmemory;
*len = gfxmem_bank.allocated;
return gfxmem_bank.baseaddr;
}
void restore_fram (int len, size_t filepos)
@ -1823,9 +1557,9 @@ uae_u8 *save_expansion (int *len, uae_u8 *dstptr)
uae_u8 *dst = t, *dstbak = t;
if (dstptr)
dst = dstbak = dstptr;
save_u32 (fastmem_start);
save_u32 (z3fastmem_start);
save_u32 (gfxmem_start);
save_u32 (fastmem_bank.start);
save_u32 (z3fastmem_bank.start);
save_u32 (gfxmem_bank.start);
save_u32 (rtarea_base);
*len = 4 + 4 + 4 + 4;
return dstbak;
@ -1833,9 +1567,9 @@ uae_u8 *save_expansion (int *len, uae_u8 *dstptr)
uae_u8 *restore_expansion (uae_u8 *src)
{
fastmem_start = restore_u32 ();
z3fastmem_start = restore_u32 ();
gfxmem_start = restore_u32 ();
fastmem_bank.start = restore_u32 ();
z3fastmem_bank.start = restore_u32 ();
gfxmem_bank.start = restore_u32 ();
rtarea_base = restore_u32 ();
if (rtarea_base != 0 && rtarea_base != RTAREA_DEFAULT && rtarea_base != RTAREA_BACKUP)
rtarea_base = 0;

4
filesys.cpp
View File

@ -6563,14 +6563,14 @@ static void dump_partinfo (struct hardfiledata *hfd, uae_u8 *pp)
s = au ((char*)pp + 37);
pp += 128;
dostype = rl (pp + 64);
size = ((uae_u64)rl (pp + 4)) * 4 * rl (pp + 12) * rl (pp + 20) * (rl (pp + 40) - rl (pp + 36) + 1);
spb = rl (pp + 16);
blocksize = rl (pp + 4) * 4;
surfaces = rl (pp + 12);
spb = rl (pp + 16);
spt = rl (pp + 20);
reserved = rl (pp + 24);
lowcyl = rl (pp + 36);
highcyl = rl (pp + 40);
size = ((uae_u64)blocksize) * surfaces * spt * (highcyl - lowcyl + 1);
write_log (_T("Partition '%s' Dostype=%08X (%s) Flags: %08X\n"), s, dostype, dostypes (dostype), flags);
write_log (_T("BlockSize: %d, Surfaces: %d, SectorsPerBlock %d\n"),

566
gfxboard.cpp
View File

@ -17,11 +17,15 @@
#include "newcpu.h"
#include "picasso96.h"
#include "statusline.h"
#include "rommgr.h"
#include "zfile.h"
#include "gfxboard.h"
#include "qemuvga/qemuuaeglue.h"
#include "qemuvga/vga.h"
#define GFXBOARD_AUTOCONFIG_SIZE 131072
#define BOARD_REGISTERS_SIZE 0x00010000
#define BOARD_MANUFACTURER_PICASSO 2167
@ -33,7 +37,10 @@
#define PICASSOIV_REG 0x00600000
#define PICASSOIV_IO 0x00200000
#define PICASSOIV_VRAM 0x01000000
#define PICASSOIV_ROM_OFFSET 0x0200
#define PICASSOIV_FLASH_OFFSET 0x8000
#define PICASSOIV_FLASH_BANK 0x8000
#define PICASSOIV_MAX_FLASH (GFXBOARD_AUTOCONFIG_SIZE - 32768)
#define BOARD_MANUFACTURER_PICCOLO 2195
#define BOARD_MODEL_MEMORY_PICCOLO 5
@ -45,6 +52,8 @@
#define BOARD_MODEL_MEMORY_SPECTRUM 1
#define BOARD_MODEL_REGISTERS_SPECTRUM 2
extern addrbank gfxboard_bank_special;
struct gfxboard
{
TCHAR *name;
@ -57,59 +66,64 @@ struct gfxboard
int banksize;
int chiptype;
bool z3;
bool irq;
int irq;
bool swap;
};
#define PICASSOIV 10
#define PICASSOIV 11
static struct gfxboard boards[] =
{
{
_T("Picasso II"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
0x00020000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, false, false
0x00020000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, 0, false
},
{
_T("Picasso II+"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
0x00100000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, true, false
0x00100000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, 2, false
},
{
_T("Piccolo"),
_T("Piccolo Zorro II"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, true, true
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, 6, true
},
{
_T("Piccolo Zorro III"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, true, 6, true
},
{
_T("Piccolo SD64 Zorro II"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
0x00000000, 0x00200000, 0x00400000, 0x00200000, CIRRUS_ID_CLGD5434, false, true, true
0x00000000, 0x00200000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5434, false, 6, true
},
{
_T("Piccolo SD64 Zorro III"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
0x00000000, 0x00200000, 0x00400000, 0x01000000, CIRRUS_ID_CLGD5434, true, true, true
0x00000000, 0x00200000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5434, true, 6, true
},
{
_T("Spectrum 28/24 Zorro II"),
BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, true, true
0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, 6, true
},
{
_T("Spectrum 28/24 Zorro III"),
BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
0x00000000, 0x00100000, 0x00200000, 0x01000000, CIRRUS_ID_CLGD5428, true, true, true
0x00000000, 0x00100000, 0x00200000, 0x01000000, CIRRUS_ID_CLGD5428, true, 6, true
},
{
_T("Picasso IV Zorro II"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, BOARD_MODEL_REGISTERS_PICASSOIV,
0x00000000, 0x00400000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5446, false, true, true
0x00000000, 0x00400000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5446, false, 6, true
},
{
// REG:00600000 IO:00200000 VRAM:01000000
_T("Picasso IV Zorro III"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, 0,
0x00000000, 0x00400000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5446, true, true, true
0x00000000, 0x00400000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5446, true, 6, true
}
};
@ -118,7 +132,8 @@ static int configured_mem, configured_regs;
static struct gfxboard *board;
static uae_u32 memory_mask;
static uae_u8 automemory[256];
static uae_u8 *automemory;
static int picassoiv_bank;
static CirrusVGAState vga;
static uae_u8 *vram;
static uae_u32 gfxboardmem_start;
@ -128,10 +143,14 @@ static int fullrefresh;
static bool modechanged;
static uae_u8 *gfxboard_surface, *vram_address, *fakesurface_surface;
static bool gfxboard_vblank;
static bool blit_cpu_to_vram;
static bool gfxboard_intena;
static bool vram_enabled, vram_offset_enabled;
static hwaddr vram_offset[2];
static const MemoryRegionOps *vgaio, *vgablitram;
static const MemoryRegion *vgaioregion, *vgavramregion;
static uae_u32 vgaioregionptr, vgavramregionptr, vgabank0regionptr, vgabank1regionptr;
static const MemoryRegionOps *vgaio, *vgaram, *vgalowram;
static MemoryRegion vgaioregion, vgavramregion;
static void init_board (void)
{
@ -140,20 +159,29 @@ static void init_board (void)
fakesurface_surface = xmalloc (uae_u8, 4 * 10000);
if (currprefs.rtgmem_type == PICASSOIV)
vramsize = 16 * 1024 * 1024;
vram_offset[0] = vram_offset[1] = 0;
vram_enabled = true;
vram_offset_enabled = false;
vram = mapped_malloc (vramsize, board->z3 ? _T("z3_gfx") : _T("z2_gfx"));
vga.vga.vram_size_mb = currprefs.rtgmem_size >> 20;
vgaioregion.opaque = &vgaioregionptr;
vgavramregion.opaque = &vgavramregionptr;
vga.vga.vram.opaque = &vgavramregionptr;
vga_common_init(&vga.vga);
cirrus_init_common(&vga, board->chiptype, 0, NULL, NULL);
picasso_allocatewritewatch (currprefs.rtgmem_size);
}
static void gfxboard_setmode (void)
static bool gfxboard_setmode (void)
{
int bpp, width, height;
bpp = vga.vga.get_bpp (&vga.vga);
vga.vga.get_resolution (&vga.vga, &width, &height);
if (bpp == 0)
bpp = 8;
if (width <= 16 || height <= 16)
return false;
picasso96_state.Width = width;
picasso96_state.Height = height;
picasso96_state.BytesPerPixel = bpp / 8;
@ -161,6 +189,7 @@ static void gfxboard_setmode (void)
write_log (_T("GFXBOARD %dx%dx%d\n"), width, height, bpp);
gfx_set_picasso_modeinfo (width, height, bpp, RGBFB_NONE);
fullrefresh = 2;
return true;
}
static bool gfxboard_checkchanged (void)
@ -168,7 +197,10 @@ static bool gfxboard_checkchanged (void)
int bpp, width, height;
bpp = vga.vga.get_bpp (&vga.vga);
vga.vga.get_resolution (&vga.vga, &width, &height);
if (bpp == 0)
bpp = 8;
if (width <= 16 || height <= 16)
return false;
if (picasso96_state.Width != width ||
picasso96_state.Height != height ||
picasso96_state.BytesPerPixel != bpp / 8)
@ -243,8 +275,9 @@ void gfxboard_vsync_handler (void)
if (!configured_mem || !configured_regs)
return;
if ((modechanged || gfxboard_checkchanged ()) && monswitch) {
gfxboard_setmode ();
if (monswitch && (modechanged || gfxboard_checkchanged ())) {
if (!gfxboard_setmode ())
return;
init_hz_p96 ();
modechanged = false;
picasso_requested_on = true;
@ -280,9 +313,12 @@ void gfxboard_vsync_handler (void)
gfxboard_surface = NULL;
// Vertical Sync End Register, 0x10 = Clear Vertical Interrupt.
if (board->irq && (vga.vga.cr[0x11] & 0x10)) {
if (board->irq && gfxboard_intena && (vga.vga.cr[0x11] & 0x10)) {
gfxboard_vblank = true;
INTREQ (0x8000 | 0x0008);
if (board->irq == 2)
INTREQ (0x8000 | 0x0008);
else
INTREQ (0x8000 | 0x2000);
}
if (fullrefresh > 0)
@ -299,6 +335,75 @@ void dpy_gfx_update(QemuConsole *con, int x, int y, int w, int h)
picasso_invalidate (x, y, w, h);
}
void memory_region_init_alias(MemoryRegion *mr,
const char *name,
MemoryRegion *orig,
hwaddr offset,
uint64_t size)
{
if (!stricmp(name, "vga.bank0")) {
mr->opaque = &vgabank0regionptr;
} else if (!stricmp(name, "vga.bank1")) {
mr->opaque = &vgabank1regionptr;
}
}
static void remap_vram (hwaddr offset0, hwaddr offset1, bool enabled)
{
#ifdef JIT
if (currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong))
flush_icache (0, 3);
#endif
vram_offset[0] = offset0;
vram_offset[1] = offset1;
#if 0
if (vram_enabled != enabled)
write_log (_T("VRAM state=%d\n"), enabled);
#endif
vram_enabled = enabled && (vga.vga.sr[0x07] & 0x01);
#if 0
vram_enabled = false;
#endif
// offset==0 and offset1==0x8000: linear vram mapping
vram_offset_enabled = offset0 != 0 || offset1 != 0x8000;
#if 0
if (vram_offset_enabled)
write_log (_T("VRAM offset %08x and %08x\n"), offset0, offset1);
#endif
}
void memory_region_set_alias_offset(MemoryRegion *mr,
hwaddr offset)
{
if (mr->opaque == &vgabank0regionptr) {
if (offset != vram_offset[0]) {
//write_log (_T("vgavramregion0 %08x\n"), offset);
remap_vram (offset, vram_offset[1], vram_enabled);
}
} else if (mr->opaque == &vgabank1regionptr) {
if (offset != vram_offset[1]) {
//write_log (_T("vgavramregion1 %08x\n"), offset);
remap_vram (vram_offset[0], offset, vram_enabled);
}
} else if (mr->opaque == &vgaioregionptr) {
write_log (_T("vgaioregion %d\n"), offset);
} else {
write_log (_T("unknown region %d\n"), offset);
}
}
void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
{
if (mr->opaque == &vgabank0regionptr || mr->opaque == &vgabank1regionptr) {
if (enabled != vram_enabled) {
//write_log (_T("enable vgavramregion %d\n"), enabled);
remap_vram (vram_offset[0], vram_offset[1], enabled);
}
} else if (mr->opaque == &vgaioregionptr) {
write_log (_T("enable vgaioregion %d\n"), enabled);
} else {
write_log (_T("enable unknown region %d\n"), enabled);
}
}
void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
hwaddr size, unsigned client)
{
@ -306,11 +411,11 @@ void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
hwaddr size, unsigned client)
{
if (mr != vgavramregion)
if (mr->opaque != &vgavramregionptr)
return false;
if (fullrefresh)
return true;
return picasso_is_vram_dirty (addr + p96ram_start, size);
return picasso_is_vram_dirty (addr + gfxmem_bank.start, size);
}
static QEMUResetHandler *reset_func;
@ -329,12 +434,8 @@ static void bput_regtest (uaecptr addr, uae_u8 v)
if (!(vga.vga.cr[0x11] & 0x10))
gfxboard_vblank = false;
}
if (vga.cirrus_srcptr != vga.cirrus_srcptr_end && !blit_cpu_to_vram) {
blit_cpu_to_vram = true;
#ifdef JIT
if (currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong))
flush_icache (0, 3);
#endif
if (!(vga.vga.sr[0x07] & 0x01) && vram_enabled) {
remap_vram (vram_offset[0], vram_offset[1], false);
}
}
@ -354,16 +455,9 @@ static uae_u8 bget_regtest (uaecptr addr, uae_u8 v)
return v;
}
static void checkblitend (void)
{
if (vga.cirrus_srcptr == vga.cirrus_srcptr_end) {
blit_cpu_to_vram = false;
}
}
void *memory_region_get_ram_ptr(MemoryRegion *mr)
{
if (mr == vgavramregion)
if (mr->opaque == &vgavramregionptr)
return vram;
return NULL;
}
@ -373,7 +467,7 @@ void memory_region_init_ram(MemoryRegion *mr,
uint64_t size)
{
if (!stricmp (name, "vga.vram")) {
vgavramregion = mr;
vgavramregion.opaque = mr->opaque;
}
}
@ -385,9 +479,11 @@ void memory_region_init_io(MemoryRegion *mr,
{
if (!stricmp (name, "cirrus-io")) {
vgaio = ops;
vgaioregion = mr;
mr->opaque = vgaioregion.opaque;
} else if (!stricmp (name, "cirrus-linear-io")) {
vgaram = ops;
} else if (!stricmp (name, "cirrus-low-memory")) {
vgablitram = ops;
vgalowram = ops;
}
}
@ -396,96 +492,155 @@ int is_surface_bgr(DisplaySurface *surface)
return board->swap;
}
static uaecptr fixaddr (uaecptr addr, int mask)
{
if (vram_offset_enabled && vram_enabled) {
#ifdef JIT
special_mem |= mask;
#endif
if (addr & 0x8000) {
addr += vram_offset[1] & ~0x8000;
} else {
addr += vram_offset[0];
}
}
addr &= memory_mask;
return addr;
}
static const MemoryRegionOps *getvgabank (uaecptr *paddr)
{
uaecptr addr = *paddr;
addr &= memory_mask;
*paddr = addr;
// if (!(vga.vga.sr[0x07] & 0x01))
if (addr < 0x10000)
return vgalowram;
return vgaram;
}
static uae_u32 REGPARAM2 gfxboard_lget_mem (uaecptr addr)
{
#if 0
#ifdef JIT
special_mem |= S_READ;
#endif
return vgavram->read (&vga, addr, 4);
#else
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
addr &= memory_mask;
m = vram + addr;
return do_get_mem_long ((uae_u32 *)m);
if (!vram_enabled) {
const MemoryRegionOps *bank = getvgabank (&addr);
uae_u32 v;
#ifdef JIT
special_mem |= S_READ;
#endif
addr &= memory_mask;
v = bank->read (&vga, addr + 0, 1) << 24;
v |= bank->read (&vga, addr + 1, 1) << 16;
v |= bank->read (&vga, addr + 2, 1) << 8;
v |= bank->read (&vga, addr + 3, 1) << 0;
return v;
} else {
addr = fixaddr (addr, S_READ);
m = vram + addr;
return do_get_mem_long ((uae_u32 *)m);
}
}
static uae_u32 REGPARAM2 gfxboard_wget_mem (uaecptr addr)
{
#if 0
#ifdef JIT
special_mem |= S_READ;
#endif
return vgavram->read (&vga, addr, 2);
#else
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
addr &= memory_mask;
m = vram + addr;
return do_get_mem_word ((uae_u16 *)m);
if (!vram_enabled) {
const MemoryRegionOps *bank = getvgabank (&addr);
uae_u32 v;
#ifdef JIT
special_mem |= S_READ;;
#endif
v = bank->read (&vga, addr + 0, 1) << 8;
v |= bank->read (&vga, addr + 1, 1) << 0;
return v;
} else {
addr = fixaddr (addr, S_READ);
m = vram + addr;
return do_get_mem_word ((uae_u16 *)m);
}
}
static uae_u32 REGPARAM2 gfxboard_bget_mem (uaecptr addr)
{
#if 0
#ifdef JIT
special_mem |= S_READ;
#endif
return vgavram->read (&vga, addr, 1);
#else
addr -= gfxboardmem_start & memory_mask;
addr &= memory_mask;
return vram[addr];
if (!vram_enabled) {
const MemoryRegionOps *bank = getvgabank (&addr);
uae_u32 v;
#ifdef JIT
special_mem |= S_READ;;
#endif
v = bank->read (&vga, addr + 0, 1);
return v;
} else {
addr = fixaddr (addr, S_READ);
return vram[addr];
}
}
#define MEMDEBUG 0
#define MEMDEBUGMASK 0xffffff
#define MEMDEBUGTEST 0x1fc000
static void REGPARAM2 gfxboard_lput_mem (uaecptr addr, uae_u32 l)
{
if (blit_cpu_to_vram) {
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
#if MEMDEBUG
if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && l)
write_log (_T("%08X L %08X\n"), addr, l);
#endif
if (!vram_enabled) {
const MemoryRegionOps *bank = getvgabank (&addr);
#ifdef JIT
special_mem |= S_WRITE;
#endif
vgablitram->write (&vga, 0, l >> 24, 1);
vgablitram->write (&vga, 0, l >> 16, 1);
vgablitram->write (&vga, 0, l >> 8, 1);
vgablitram->write (&vga, 0, l >> 0, 1);
checkblitend ();
bank->write (&vga, addr + 0, l >> 24, 1);
bank->write (&vga, addr + 1, l >> 16, 1);
bank->write (&vga, addr + 2, l >> 8, 1);
bank->write (&vga, addr + 3, l >> 0, 1);
} else {
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
addr &= memory_mask;
addr = fixaddr (addr, S_WRITE);
m = vram + addr;
do_put_mem_long ((uae_u32 *) m, l);
}
}
static void REGPARAM2 gfxboard_wput_mem (uaecptr addr, uae_u32 w)
{
if (blit_cpu_to_vram) {
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
#if MEMDEBUG
if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && w)
write_log (_T("%08X W %04X\n"), addr, w & 0xffff);
#endif
if (!vram_enabled) {
const MemoryRegionOps *bank = getvgabank (&addr);
#ifdef JIT
special_mem |= S_WRITE;
#endif
vgablitram->write (&vga, 0, w >> 8, 1);
vgablitram->write (&vga, 0, w >> 0, 1);
checkblitend ();
bank->write (&vga, addr + 0, w >> 8, 1);
bank->write (&vga, addr + 1, w >> 0, 1);
} else {
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
addr &= memory_mask;
addr = fixaddr (addr, S_WRITE);
m = vram + addr;
do_put_mem_word ((uae_u16 *)m, w);
}
}
static void REGPARAM2 gfxboard_bput_mem (uaecptr addr, uae_u32 b)
{
if (blit_cpu_to_vram) {
addr -= gfxboardmem_start & memory_mask;
#if MEMDEBUG
if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && b)
write_log (_T("%08X B %02X\n"), addr, b & 0xff);
#endif
if (!vram_enabled) {
const MemoryRegionOps *bank = getvgabank (&addr);
#ifdef JIT
special_mem |= S_WRITE;
#endif
vgablitram->write (&vga, 0, b, 1);
checkblitend ();
bank->write (&vga, addr, b, 1);
} else {
addr -= gfxboardmem_start & memory_mask;
addr &= memory_mask;
addr = fixaddr (addr, S_WRITE);
vram[addr] = b;
}
}
@ -510,7 +665,7 @@ static uae_u32 REGPARAM2 gfxboard_bget_mem_autoconfig (uaecptr addr)
special_mem |= S_READ;
#endif
addr &= 65535;
if (addr < 0x40)
if (addr < GFXBOARD_AUTOCONFIG_SIZE)
v = automemory[addr];
return v;
}
@ -525,20 +680,23 @@ static void REGPARAM2 gfxboard_wput_mem_autoconfig (uaecptr addr, uae_u32 b)
b &= 0xffff;
addr &= 65535;
if (addr == 0x44) {
put_word (regs.regs[11] + 0x20, p96ram_start >> 16);
put_word (regs.regs[11] + 0x28, p96ram_start >> 16);
put_word (regs.regs[11] + 0x20, gfxmem_bank.start >> 16);
put_word (regs.regs[11] + 0x28, gfxmem_bank.start >> 16);
gfxboard_bank_memory.bget = gfxboard_bget_mem;
gfxboard_bank_memory.bput = gfxboard_bput_mem;
gfxboard_bank_memory.wput = gfxboard_wput_mem;
if (currprefs.rtgmem_type == PICASSOIV) {
map_banks (&gfxboard_bank_memory, (p96ram_start + PICASSOIV_VRAM) >> 16, (board->banksize - PICASSOIV_VRAM) >> 16, currprefs.rtgmem_size);
map_banks (&gfxboard_bank_registers, (p96ram_start + PICASSOIV_IO) >> 16, BOARD_REGISTERS_SIZE >> 16, BOARD_REGISTERS_SIZE);
map_banks (&gfxboard_bank_memory, (gfxmem_bank.start + PICASSOIV_VRAM) >> 16, (board->banksize - PICASSOIV_VRAM) >> 16, currprefs.rtgmem_size);
map_banks (&gfxboard_bank_registers, (gfxmem_bank.start + PICASSOIV_REG) >> 16, BOARD_REGISTERS_SIZE >> 16, BOARD_REGISTERS_SIZE);
map_banks (&gfxboard_bank_special, gfxmem_bank.start >> 16, (PICASSOIV_FLASH_BANK * 4) >> 16, PICASSOIV_FLASH_BANK * 4);
picassoiv_bank = 0;
init_board ();
} else {
map_banks (&gfxboard_bank_memory, p96ram_start >> 16, board->banksize >> 16, currprefs.rtgmem_size);
map_banks (&gfxboard_bank_memory, gfxmem_bank.start >> 16, board->banksize >> 16, currprefs.rtgmem_size);
}
write_log (_T("%s autoconfigured at 0x%04X0000\n"), gfxboard_bank_memory.name, p96ram_start >> 16);
configured_mem = p96ram_start >> 16;
gfxboardmem_start = p96ram_start;
write_log (_T("%s autoconfigured at 0x%04X0000\n"), gfxboard_bank_memory.name, gfxmem_bank.start >> 16);
configured_mem = gfxmem_bank.start >> 16;
gfxboardmem_start = gfxmem_bank.start;
expamem_next ();
return;
}
@ -578,16 +736,43 @@ static void REGPARAM2 gfxboard_bput_mem_autoconfig (uaecptr addr, uae_u32 b)
}
}
static uaecptr mungeaddr (uaecptr addr)
static uaecptr mungeaddr (uaecptr addr, bool write)
{
addr &= 65535;
if (addr >= 0x2000)
if (addr >= 0x2000) {
if (addr == 0x46e8) {
// wakeup register
return 0;
}
write_log (_T("GFXBOARD: %d unknown IO address %x\n"), write, addr);
return 0;
if (addr >= 0x1000)
}
if (addr >= 0x1000) {
if (board->manufacturer == BOARD_MANUFACTURER_PICASSO) {
if (addr == 0x1001) {
gfxboard_intena = true;
return 0;
}
if (addr == 0x1000) {
gfxboard_intena = false;
return 0;
}
}
if ((addr & 0xfff) < 0x3b0) {
write_log (_T("GFXBOARD: %d unknown IO address %x\n"), write, addr);
return 0;
}
addr++;
}
addr &= 0x0fff;
if (addr < 0x3b0)
if (addr == 0x102) {
// POS102
return 0;
}
if (addr < 0x3b0) {
write_log (_T("GFXBOARD: %d unknown IO address %x\n"), write, addr);
return 0;
}
addr -= 0x3b0;
return addr;
}
@ -598,7 +783,7 @@ static uae_u32 REGPARAM2 gfxboard_lget_regs (uaecptr addr)
#ifdef JIT
special_mem |= S_READ;
#endif
addr = mungeaddr (addr);
addr = mungeaddr (addr, false);
if (addr)
v = vgaio->read (&vga, addr, 4);
return v;
@ -609,7 +794,7 @@ static uae_u32 REGPARAM2 gfxboard_wget_regs (uaecptr addr)
#ifdef JIT
special_mem |= S_READ;
#endif
addr = mungeaddr (addr);
addr = mungeaddr (addr, false);
if (addr) {
uae_u8 v1, v2;
v1 = vgaio->read (&vga, addr + 0, 1);
@ -629,7 +814,7 @@ static uae_u32 REGPARAM2 gfxboard_bget_regs (uaecptr addr)
addr &= 65535;
if (addr >= 0x8000)
return 0;
addr = mungeaddr (addr);
addr = mungeaddr (addr, false);
if (addr) {
v = vgaio->read (&vga, addr, 1);
v = bget_regtest (addr, v);
@ -643,7 +828,7 @@ static void REGPARAM2 gfxboard_lput_regs (uaecptr addr, uae_u32 l)
special_mem |= S_WRITE;
#endif
//write_log (_T("GFX LONG PUT IO %04X = %04X\n"), addr & 65535, l);
addr = mungeaddr (addr);
addr = mungeaddr (addr, true);
if (addr)
vgaio->write (&vga, addr, l, 4);
}
@ -653,7 +838,7 @@ static void REGPARAM2 gfxboard_wput_regs (uaecptr addr, uae_u32 w)
special_mem |= S_WRITE;
#endif
//write_log (_T("GFX WORD PUT IO %04X = %04X\n"), addr & 65535, w & 0xffff);
addr = mungeaddr (addr);
addr = mungeaddr (addr, true);
if (addr) {
vgaio->write (&vga, addr + 0, (w >> 8) & 0xff, 1);
bput_regtest (addr + 0, (w >> 8) & 0xff);
@ -684,11 +869,12 @@ static void REGPARAM2 gfxboard_bput_regs (uaecptr addr, uae_u32 b)
case BOARD_MANUFACTURER_PICCOLO:
case BOARD_MANUFACTURER_SPECTRUM:
monswitch = (b & 0x20) != 0;
gfxboard_intena = (b & 0x40) != 0;
break;
}
return;
}
addr = mungeaddr (addr);
addr = mungeaddr (addr, true);
if (addr) {
vgaio->write (&vga, addr, b & 0xff, 1);
bput_regtest (addr, b);
@ -702,7 +888,7 @@ static uae_u32 REGPARAM2 gfxboard_bget_regs_autoconfig (uaecptr addr)
special_mem |= S_READ;
#endif
addr &= 65535;
if (addr < 0x40)
if (addr < GFXBOARD_AUTOCONFIG_SIZE)
v = automemory[addr];
return v;
}
@ -757,10 +943,11 @@ void gfxboard_reset (void)
fakesurface_surface = NULL;
configured_mem = 0;
configured_regs = 0;
gfxboard_bank_registers.bget = gfxboard_bget_regs_autoconfig;
gfxboard_bank_registers.bput = gfxboard_bput_regs_autoconfig;
gfxboard_bank_memory.bget = gfxboard_bget_mem_autoconfig;
gfxboard_bank_memory.bput = gfxboard_bput_mem_autoconfig;
monswitch = false;
oldswitch = false;
modechanged = false;
gfxboard_vblank = false;
gfxboard_intena = false;
if (board) {
if (board->z3)
gfxboard_bank_memory.wput = gfxboard_wput_mem_autoconfig;
@ -771,17 +958,83 @@ void gfxboard_reset (void)
addrbank gfxboard_bank_memory = {
gfxboard_lget_mem, gfxboard_wget_mem, gfxboard_bget_mem,
gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem_autoconfig,
gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem,
gfxboard_xlate, gfxboard_check, NULL, NULL,
gfxboard_lget_mem, gfxboard_wget_mem, ABFLAG_RAM
};
addrbank gfxboard_bank_registers = {
gfxboard_lget_regs, gfxboard_wget_regs, gfxboard_bget_regs,
gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs_autoconfig,
gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs,
default_xlate, default_check, NULL, NULL,
dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE
};
static uae_u32 REGPARAM2 gfxboards_lget_regs (uaecptr addr)
{
uae_u32 v = 0xffffffff;
#ifdef JIT
special_mem |= S_READ;
#endif
return v;
}
static uae_u32 REGPARAM2 gfxboards_wget_regs (uaecptr addr)
{
uae_u16 v = 0xffff;
#ifdef JIT
special_mem |= S_READ;
#endif
return v;
}
static uae_u32 REGPARAM2 gfxboards_bget_regs (uaecptr addr)
{
uae_u8 v = 0xff;
#ifdef JIT
special_mem |= S_READ;
#endif
addr &= 0x1ffff;
if (picassoiv_bank) {
write_log (_T("PicassoIV bget %08x\n"), addr);
return 0;
} else {
if (addr < PICASSOIV_FLASH_OFFSET) {
v = automemory[addr];
return v;
}
addr -= PICASSOIV_FLASH_OFFSET;
addr /= 2;
v = automemory[addr + PICASSOIV_FLASH_OFFSET];
return v;
}
}
static void REGPARAM2 gfxboards_lput_regs (uaecptr addr, uae_u32 l)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
static void REGPARAM2 gfxboards_wput_regs (uaecptr addr, uae_u32 w)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
}
static void REGPARAM2 gfxboards_bput_regs (uaecptr addr, uae_u32 b)
{
#ifdef JIT
special_mem |= S_WRITE;
#endif
write_log (_T("PicassoIV bput %08x %02X\n"), addr, b & 0xff);
if ((addr & 65535) == 0)
picassoiv_bank = b;
}
addrbank gfxboard_bank_special = {
gfxboards_lget_regs, gfxboards_wget_regs, gfxboards_bget_regs,
gfxboards_lput_regs, gfxboards_wput_regs, gfxboards_bput_regs,
default_xlate, default_check, NULL, _T("Picasso IV Flash"),
dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE
};
bool gfxboard_is_z3 (int type)
{
if (type == GFXBOARD_UAE_Z2)
@ -792,12 +1045,21 @@ bool gfxboard_is_z3 (int type)
return board->z3;
}
bool gfxboard_need_byteswap (int type)
{
if (type < 2)
return false;
board = &boards[type - 2];
return board->swap;
}
int gfxboard_get_vram_min (int type)
{
if (type < 2)
return -1;
board = &boards[type - 2];
return board->vrammax; //board->vrammin;
return board->vrammax;
//return board->vrammin;
}
int gfxboard_get_vram_max (int type)
@ -816,23 +1078,35 @@ bool gfxboard_is_registers (int type)
return board->model_registers != 0;
}
static void gfxboard_init (void)
{
if (!automemory)
automemory = xmalloc (uae_u8, GFXBOARD_AUTOCONFIG_SIZE);
memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
}
void gfxboard_init_memory (void)
{
int vram = currprefs.rtgmem_size;
uae_u8 flags;
memset (automemory, 0xff, sizeof automemory);
uae_u8 z2_flags, z3_flags, type;
gfxboard_init ();
memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
flags = 0x05;
z2_flags = 0x05;
z3_flags = 0x06;
vram /= 0x00100000;
while (vram > 1) {
flags++;
z2_flags++;
z3_flags++;
vram >>= 1;
}
if (board->z3) {
ew (0x00, 0x00 | 0x08 | 0x80); // 16M Z3
ew (0x08, flags | 0x10);
type = 0x00 | 0x08 | 0x80; // 16M Z3
ew (0x08, z3_flags | 0x10 | 0x20);
} else {
ew (0x00, flags | 0x08 | 0xc0);
type = z2_flags | 0x08 | 0xc0;
}
ew (0x04, board->model_memory);
ew (0x10, board->manufacturer >> 8);
@ -844,8 +1118,47 @@ void gfxboard_init_memory (void)
ew (0x20, ser >> 8); /* ser.no. Byte 2 */
ew (0x24, ser >> 0); /* ser.no. Byte 3 */
if (currprefs.rtgmem_type == PICASSOIV) {
struct zfile *rom;
rom = read_rom_name (_T("roms/picasso_iv_boot.rom"));
if (rom) {
uae_u8 b;
int size = 0;
int offset = PICASSOIV_ROM_OFFSET;
/* rom vector */
type |= 0x10;
ew (0x28, PICASSOIV_ROM_OFFSET >> 8);
ew (0x2c, PICASSOIV_ROM_OFFSET);
while (zfile_fread (&b, 1, 1, rom)) {
automemory[offset] = b;
automemory[offset + 2] = b << 4;
offset += 4;
size++;
}
zfile_fclose (rom);
write_log (_T("PICASSOIV: %d byte boot rom loaded\n"), size);
} else {
write_log (_T("PICASSOIV: boot rom not found\n"));
}
rom = read_rom_name (_T("roms/picasso_iv_flash_7.4.rom"));
if (rom) {
int size;
size = zfile_fread (&automemory[PICASSOIV_FLASH_OFFSET], 1, PICASSOIV_MAX_FLASH, rom);
zfile_fclose (rom);
write_log (_T("PICASSOIV: %d byte flash rom loaded\n"), size);
} else {
write_log (_T("PICASSOIV: flash rom not found\n"));
}
}
ew (0x00, type);
gfxboard_bank_memory.name = board->name;
gfxboard_bank_registers.name = board->name;
gfxboard_bank_memory.bget = gfxboard_bget_mem_autoconfig;
gfxboard_bank_memory.bput = gfxboard_bput_mem_autoconfig;
map_banks (&gfxboard_bank_memory, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
}
@ -853,7 +1166,7 @@ void gfxboard_init_registers (void)
{
if (!board->model_registers)
return;
memset (automemory, 0xff, sizeof automemory);
memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
ew (0x00, 0xc0 | 0x01); // 64k Z2
ew (0x04, board->model_registers);
ew (0x10, board->manufacturer >> 8);
@ -865,5 +1178,8 @@ void gfxboard_init_registers (void)
ew (0x20, ser >> 8); /* ser.no. Byte 2 */
ew (0x24, ser >> 0); /* ser.no. Byte 3 */
gfxboard_bank_registers.bget = gfxboard_bget_regs_autoconfig;
gfxboard_bank_registers.bput = gfxboard_bput_regs_autoconfig;
map_banks (&gfxboard_bank_registers, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
}

4
include/a2091.h
View File

@ -2,6 +2,10 @@
extern addrbank dmaca2091_bank;
extern void init_scsi (void);
extern void scsi_dmac_start_dma (void);
extern void scsi_dmac_stop_dma (void);
extern void a2091_init (void);
extern void a2091_free (void);
extern void a2091_reset (void);

2
include/akiko.h
View File

@ -10,6 +10,4 @@ extern void akiko_free (void);
extern void AKIKO_hsync_handler (void);
extern void akiko_mute (int);
extern uae_u8 *extendedkickmemory;
extern void rethink_akiko (void);

2
include/autoconf.h
View File

@ -29,7 +29,7 @@ extern uaecptr makedatatable (uaecptr resid, uaecptr resname, uae_u8 type, uae_s
extern void align (int);
extern volatile int uae_int_requested;
extern volatile int uae_int_requested, uaenet_int_requested;
extern void set_uae_int_flag (void);
#define RTS 0x4e75

2
include/custom.h
View File

@ -114,6 +114,8 @@ extern uae_u16 INTREQR (void);
#define VBLANK_SPRITE_NTSC 20
#define VBLANK_HZ_PAL 50
#define VBLANK_HZ_NTSC 60
#define VSYNC_ENDLINE_PAL 5
#define VSYNC_ENDLINE_NTSC 6
#define EQU_ENDLINE_PAL 8
#define EQU_ENDLINE_NTSC 10

1
include/filesys.h
View File

@ -71,6 +71,7 @@ struct hardfiledata {
};
#define HFD_FLAGS_REALDRIVE 1
#define HFD_FLAGS_REALDRIVEPARTITION 2
struct hd_hardfiledata {
struct hardfiledata hfd;

2
include/gfxboard.h
View File

@ -1,6 +1,5 @@
extern addrbank gfxboard_bank_memory;
extern addrbank gfxboard_bank_memory_blit;
extern addrbank gfxboard_bank_registers;
extern void gfxboard_init_memory (void);
@ -12,6 +11,7 @@ extern bool gfxboard_is_z3 (int);
extern bool gfxboard_is_registers (int);
extern int gfxboard_get_vram_min (int);
extern int gfxboard_get_vram_max (int);
extern bool gfxboard_need_byteswap (int type);
extern double gfxboard_get_vsync (void);
extern void gfxboard_refresh (void);

123
include/memory.h
View File

@ -38,16 +38,7 @@ typedef uae_u8 *(REGPARAM3 *xlate_func)(uaecptr) REGPARAM;
typedef int (REGPARAM3 *check_func)(uaecptr, uae_u32) REGPARAM;
extern uae_u8 *address_space, *good_address_map;
extern uae_u8 *chipmemory;
extern uae_u32 allocated_chipmem;
extern uae_u32 allocated_fastmem;
extern uae_u32 allocated_bogomem;
extern uae_u32 allocated_gfxmem;
extern uae_u32 allocated_z3fastmem, allocated_z3fastmem2, allocated_z3chipmem;
extern uae_u32 max_z3fastmem;
extern uae_u32 allocated_a3000mem;
extern uae_u32 allocated_cardmem;
extern uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode);
extern void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v);
@ -57,14 +48,10 @@ extern void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v);
#undef DIRECT_MEMFUNCS_SUCCESSFUL
#include "machdep/maccess.h"
#define chipmem_start 0x00000000
#define bogomem_start 0x00C00000
#define cardmem_start 0x00E00000
#define kickmem_start 0x00F80000
extern uaecptr z3fastmem_start, z3fastmem2_start, z3chipmem_start;
extern uaecptr p96ram_start;
extern uaecptr fastmem_start;
extern uaecptr a3000lmem_start, a3000hmem_start;
#define chipmem_start_addr 0x00000000
#define bogomem_start_addr 0x00C00000
#define cardmem_start_addr 0x00E00000
#define kickmem_start_addr 0x00F80000
extern bool ersatzkickfile;
extern bool cloanto_rom, kickstart_rom;
@ -99,6 +86,9 @@ typedef struct {
/* for instruction opcode/operand fetches */
mem_get_func lgeti, wgeti;
int flags;
uae_u32 mask;
uae_u32 start;
uae_u32 allocated;
} addrbank;
#define CE_MEMBANK_FAST 0
@ -107,6 +97,89 @@ typedef struct {
#define CE_MEMBANK_FAST16BIT 3
extern uae_u8 ce_banktype[65536], ce_cachable[65536];
#define MEMORY_LGET(name) \
static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
return do_get_mem_long ((uae_u32 *)m); \
}
#define MEMORY_WGET(name) \
static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
return do_get_mem_word ((uae_u16 *)m); \
}
#define MEMORY_BGET(name) \
static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
{ \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
return name ## _bank.baseaddr[addr]; \
}
#define MEMORY_LPUT(name) \
static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
do_put_mem_long ((uae_u32 *)m, l); \
}
#define MEMORY_WPUT(name) \
static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
{ \
uae_u8 *m; \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
m = name ## _bank.baseaddr + addr; \
do_put_mem_word ((uae_u16 *)m, w); \
}
#define MEMORY_BPUT(name) \
static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
{ \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
name ## _bank.baseaddr[addr] = b; \
}
#define MEMORY_CHECK(name) \
static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
{ \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
return (addr + size) <= name ## _bank.allocated; \
}
#define MEMORY_XLATE(name) \
static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
{ \
addr -= name ## _bank.start & name ## _bank.mask; \
addr &= name ## _bank.mask; \
return name ## _bank.baseaddr + addr; \
}
#define MEMORY_FUNCTIONS(name) \
MEMORY_LGET(name); \
MEMORY_WGET(name); \
MEMORY_BGET(name); \
MEMORY_LPUT(name); \
MEMORY_WPUT(name); \
MEMORY_BPUT(name); \
MEMORY_CHECK(name); \
MEMORY_XLATE(name);
extern uae_u8 *filesysory;
extern uae_u8 *rtarea;
@ -126,6 +199,16 @@ extern addrbank gayle2_bank;
extern addrbank mbres_bank;
extern addrbank akiko_bank;
extern addrbank cardmem_bank;
extern addrbank bogomem_bank;
extern addrbank z3fastmem_bank;
extern addrbank z3fastmem2_bank;
extern addrbank z3chipmem_bank;
extern addrbank a3000lmem_bank;
extern addrbank a3000hmem_bank;
extern addrbank extendedkickmem_bank;
extern addrbank extendedkickmem2_bank;
extern addrbank custmem1_bank;
extern addrbank custmem2_bank;
extern void rtarea_init (void);
extern void rtarea_init_mem (void);
@ -134,9 +217,6 @@ extern void expamem_init (void);
extern void expamem_reset (void);
extern void expamem_next (void);
extern uae_u32 gfxmem_start;
extern uae_u8 *gfxmemory;
extern uae_u32 gfxmem_mask;
extern uae_u16 last_custom_value1;
/* Default memory access functions */
@ -173,6 +253,7 @@ extern uae_u8 *baseaddr[MEMORY_BANKS];
extern void memory_init (void);
extern void memory_cleanup (void);
extern void map_banks (addrbank *bank, int first, int count, int realsize);
extern void map_banks_quick (addrbank *bank, int first, int count, int realsize);
extern void map_banks_cond (addrbank *bank, int first, int count, int realsize);
extern void map_overlay (int chip);
extern void memory_hardreset (int);
@ -309,8 +390,6 @@ extern void REGPARAM3 chipmem_bput (uaecptr, uae_u32) REGPARAM;
extern uae_u32 REGPARAM3 chipmem_agnus_wget (uaecptr) REGPARAM;
extern void REGPARAM3 chipmem_agnus_wput (uaecptr, uae_u32) REGPARAM;
extern uae_u32 chipmem_mask, kickmem_mask;
extern uae_u8 *kickmemory;
extern addrbank dummy_bank;
/* 68020+ Chip RAM DMA contention emulation */

5
jit/compemu_support.cpp
View File

@ -4891,11 +4891,10 @@ static void align_target(uae_u32 a)
*target++=0x90;
}
extern uae_u8* kickmemory;
STATIC_INLINE int isinrom(uae_u32 addr)
{
return (addr>=(uae_u32)kickmemory &&
addr<(uae_u32)kickmemory+8*65536);
return (addr>=(uae_u32)kickmem_bank.baseaddr &&
addr<(uae_u32)kickmem_bank.baseaddr+8*65536);
}
static void flush_all(void)

1221
memory.cpp
View File

File diff suppressed because it is too large Load Diff

14
moduleripper.cpp
View File

@ -49,19 +49,19 @@ void moduleripper (void)
buf = p = xmalloc (uae_u8, size);
if (!buf)
return;
memcpy (p, chipmemory, currprefs.chipmem_size);
memcpy (p, chipmem_bank.baseaddr, currprefs.chipmem_size);
p += currprefs.chipmem_size;
mc (p, fastmem_start, currprefs.fastmem_size);
mc (p, fastmem_bank.start, currprefs.fastmem_size);
p += currprefs.fastmem_size;
mc (p, bogomem_start, currprefs.bogomem_size);
mc (p, bogomem_bank.start, currprefs.bogomem_size);
p += currprefs.bogomem_size;
mc (p, a3000lmem_start, currprefs.mbresmem_low_size);
mc (p, a3000lmem_bank.start, currprefs.mbresmem_low_size);
p += currprefs.mbresmem_low_size;
mc (p, a3000hmem_start, currprefs.mbresmem_high_size);
mc (p, a3000hmem_bank.start, currprefs.mbresmem_high_size);
p += currprefs.mbresmem_high_size;
mc (p, z3fastmem_start, currprefs.z3fastmem_size);
mc (p, z3fastmem_bank.start, currprefs.z3fastmem_size);
p += currprefs.z3fastmem_size;
mc (p, z3fastmem_start + currprefs.z3fastmem_size, currprefs.z3fastmem2_size);
mc (p, z3fastmem_bank.start + currprefs.z3fastmem_size, currprefs.z3fastmem2_size);
p += currprefs.z3fastmem2_size;
got = 0;

2
ncr_scsi.cpp
View File

@ -389,7 +389,7 @@ static void REGPARAM2 ncr_wput (uaecptr addr, uae_u32 w)
write_log (_T("ncr_wput %04X=%04X PC=%08X\n"), addr, w & 65535, M68K_GETPC);
#endif
if (addr == 0x44 && !configured) {
uae_u32 value = (p96ram_start + ((currprefs.rtgmem_size + 0xffffff) & ~0xffffff)) >> 16;
uae_u32 value = (gfxmem_bank.start + ((currprefs.rtgmem_size + 0xffffff) & ~0xffffff)) >> 16;
chipmem_wput (regs.regs[11] + 0x20, value);
chipmem_wput (regs.regs[11] + 0x28, value);
map_banks (&ncr_bank, value, BOARD_SIZE >> 16, 0);

17
newcpu.cpp
View File

@ -3809,17 +3809,10 @@ STATIC_INLINE int do_specialties (int cycles)
while (regs.spcflags & SPCFLAG_STOP) {
if (uae_int_requested) {
if (uae_int_requested || uaenet_int_requested) {
INTREQ_f (0x8008);
set_special (SPCFLAG_INT);
}
{
extern int volatile uaenet_int_requested;
if (uaenet_int_requested) {
INTREQ_f (0x8000 | 0x2000);
set_special (SPCFLAG_INT);
}
}
{
extern void bsdsock_fake_int_handler (void);
extern int volatile bsd_int_requested;
@ -3862,7 +3855,7 @@ STATIC_INLINE int do_specialties (int cycles)
return 1;
}
if (!uae_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP)) {
if (!uae_int_requested && !uaenet_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP)) {
/* sleep 1ms if STOP-instruction is executed
* but only if we have free frametime left to prevent slowdown
*/
@ -4212,7 +4205,7 @@ void exec_nostats (void)
cpu_cycles = adjust_cycles (cpu_cycles);
do_cycles (cpu_cycles);
if (end_block (opcode) || r->spcflags || uae_int_requested)
if (end_block (opcode) || r->spcflags || uae_int_requested || uaenet_int_requested)
return; /* We will deal with the spcflags in the caller */
}
}
@ -4253,7 +4246,7 @@ void execute_normal (void)
total_cycles += cpu_cycles;
pc_hist[blocklen].specmem = special_mem;
blocklen++;
if (end_block (opcode) || blocklen >= MAXRUN || r->spcflags || uae_int_requested) {
if (end_block (opcode) || blocklen >= MAXRUN || r->spcflags || uae_int_requested || uaenet_int_requested) {
compile_block (pc_hist, blocklen, total_cycles);
return; /* We will deal with the spcflags in the caller */
}
@ -4269,7 +4262,7 @@ static void m68k_run_jit (void)
for (;;) {
((compiled_handler*)(pushall_call_handler))();
/* Whenever we return from that, we should check spcflags */
if (uae_int_requested) {
if (uae_int_requested || uaenet_int_requested) {
INTREQ_f (0x8008);
set_special (SPCFLAG_INT);
}

6
od-win32/hardfile_win32.cpp
View File

@ -55,6 +55,7 @@ struct uae_driveinfo {
int removablemedia;
int nomedia;
int dangerous;
bool partitiondrive;
int readonly;
int cylinders, sectors, heads;
};
@ -469,6 +470,8 @@ int hdf_open_target (struct hardfiledata *hfd, const TCHAR *pname)
hfd->offset = udi->offset;
hfd->physsize = hfd->virtsize = udi->size;
hfd->ci.blocksize = udi->bytespersector;
if (udi->partitiondrive)
hfd->flags |= HFD_FLAGS_REALDRIVEPARTITION;
if (hfd->offset == 0 && !hfd->drive_empty) {
int sf = safetycheck (hfd->handle->h, udi->device_path, 0, hfd->cache, hfd->ci.blocksize);
if (sf > 0)
@ -924,7 +927,7 @@ static int hdf_write_2 (struct hardfiledata *hfd, void *buffer, uae_u64 offset,
if (hfd->handle_valid == HDF_HANDLE_WIN32) {
TCHAR *name = hfd->emptyname == NULL ? _T("<unknown>") : hfd->emptyname;
if (offset == 0) {
if (!hfd->handle->firstwrite && (hfd->flags & HFD_FLAGS_REALDRIVE)) {
if (!hfd->handle->firstwrite && (hfd->flags & HFD_FLAGS_REALDRIVE) && !(hfd->flags & HFD_FLAGS_REALDRIVEPARTITION)) {
hfd->handle->firstwrite = true;
if (ismounted (hfd->device_name, hfd->handle->h)) {
gui_message (_T("\"%s\"\n\nBlock zero write attempt but drive has one or more mounted PC partitions or WinUAE does not have Administrator privileges. Erase the drive or unmount all PC partitions first."), name);
@ -1307,6 +1310,7 @@ static BOOL GetDevicePropertyFromName(const TCHAR *DevicePath, DWORD Index, DWOR
write_log (_T("used\n"));
_stprintf (udi->device_name, _T(":P#%d_%s"), pi->PartitionNumber, orgname);
udi->dangerous = -5;
udi->partitiondrive = true;
udi++;
(*index2)++;
safepart = 1;

20
od-win32/mman.cpp
View File

@ -627,6 +627,8 @@ void mapped_free (uae_u8 *mem)
{
shmpiece *x = shm_start;
if (mem == NULL)
return;
if (mem == filesysory) {
while(x) {
if (mem == x->native_address) {
@ -742,35 +744,35 @@ void *shmat (int shmid, void *shmaddr, int shmflg)
got = TRUE;
p96special = TRUE;
shmaddr = natmem_offset + start;
p96ram_start = start;
gfxmem_bank.start = start;
if (start + currprefs.rtgmem_size < 10 * 1024 * 1024)
size += BARRIER;
} else if(!_tcscmp (shmids[shmid].name, _T("ramsey_low"))) {
shmaddr=natmem_offset + a3000lmem_start;
if (!a3000hmem_start)
shmaddr=natmem_offset + a3000lmem_bank.start;
if (!a3000hmem_bank.start)
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("ramsey_high"))) {
shmaddr=natmem_offset + a3000hmem_start;
shmaddr=natmem_offset + a3000hmem_bank.start;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3"))) {
shmaddr=natmem_offset + z3fastmem_start;
shmaddr=natmem_offset + z3fastmem_bank.start;
if (!currprefs.z3fastmem2_size)
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3_2"))) {
shmaddr=natmem_offset + z3fastmem_start + currprefs.z3fastmem_size;
shmaddr=natmem_offset + z3fastmem_bank.start + currprefs.z3fastmem_size;
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3_chip"))) {
shmaddr=natmem_offset + z3chipmem_start;
shmaddr=natmem_offset + z3chipmem_bank.start;
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3_gfx"))) {
got = TRUE;
p96special = TRUE;
p96ram_start = p96mem_offset - natmem_offset;
shmaddr = natmem_offset + p96ram_start;
gfxmem_bank.start = p96mem_offset - natmem_offset;
shmaddr = natmem_offset + gfxmem_bank.start;
size += BARRIER;
} else if(!_tcscmp (shmids[shmid].name, _T("bogo"))) {
shmaddr=natmem_offset+0x00C00000;

107
od-win32/picasso96_win.cpp
View File

@ -102,10 +102,6 @@ int p96hsync_counter, full_refresh;
#endif
#define P96TRACE2(x) do { write_log x; } while(0)
static void REGPARAM2 gfxmem_lputx (uaecptr, uae_u32) REGPARAM;
static void REGPARAM2 gfxmem_wputx (uaecptr, uae_u32) REGPARAM;
static void REGPARAM2 gfxmem_bputx (uaecptr, uae_u32) REGPARAM;
static uae_u8 all_ones_bitmap, all_zeros_bitmap; /* yuk */
struct picasso96_state_struct picasso96_state;
@ -555,7 +551,7 @@ static int renderinfo_is_current_screen (struct RenderInfo *ri)
{
if (! picasso_on)
return 0;
if (ri->Memory != gfxmemory + (picasso96_state.Address - gfxmem_start))
if (ri->Memory != gfxmem_bank.baseaddr + (picasso96_state.Address - gfxmem_bank.start))
return 0;
return 1;
}
@ -715,7 +711,7 @@ static bool rtg_render (void)
;
} else {
if (uaegfx) {
flushed = picasso_flushpixels (p96ram_start + natmem_offset, picasso96_state.XYOffset - gfxmem_start);
flushed = picasso_flushpixels (gfxmem_bank.start + natmem_offset, picasso96_state.XYOffset - gfxmem_bank.start);
} else {
gfxboard_vsync_handler ();
}
@ -1033,7 +1029,7 @@ void picasso_refresh (void)
unsigned int width, height;
/* blit the stuff from our static frame-buffer to the gfx-card */
ri.Memory = gfxmemory + (picasso96_state.Address - gfxmem_start);
ri.Memory = gfxmem_bank.baseaddr + (picasso96_state.Address - gfxmem_bank.start);
ri.BytesPerRow = picasso96_state.BytesPerRow;
ri.RGBFormat = picasso96_state.RGBFormat;
@ -1849,7 +1845,7 @@ static uae_u32 REGPARAM2 picasso_FindCard (TrapContext *ctx)
{
uaecptr AmigaBoardInfo = m68k_areg (regs, 0);
/* NOTES: See BoardInfo struct definition in Picasso96 dev info */
if (!uaegfx_active || !gfxmem_start)
if (!uaegfx_active || !gfxmem_bank.start)
return 0;
if (uaegfx_base) {
put_long (uaegfx_base + CARD_BOARDINFO, AmigaBoardInfo);
@ -1857,10 +1853,10 @@ static uae_u32 REGPARAM2 picasso_FindCard (TrapContext *ctx)
picasso96_alloc2 (ctx);
}
boardinfo = AmigaBoardInfo;
if (allocated_gfxmem && !picasso96_state.CardFound) {
if (gfxmem_bank.allocated && !picasso96_state.CardFound) {
/* Fill in MemoryBase, MemorySize */
put_long (AmigaBoardInfo + PSSO_BoardInfo_MemoryBase, gfxmem_start);
put_long (AmigaBoardInfo + PSSO_BoardInfo_MemorySize, allocated_gfxmem - reserved_gfxmem);
put_long (AmigaBoardInfo + PSSO_BoardInfo_MemoryBase, gfxmem_bank.start);
put_long (AmigaBoardInfo + PSSO_BoardInfo_MemorySize, gfxmem_bank.allocated - reserved_gfxmem);
picasso96_state.CardFound = 1; /* mark our "card" as being found */
return -1;
} else
@ -2039,7 +2035,7 @@ void picasso_getwritewatch (void)
{
ULONG ps;
writewatchcount = gwwbufsize;
if (GetWriteWatch (WRITE_WATCH_FLAG_RESET, p96ram_start + natmem_offset, (gwwbufsize - 1) * gwwpagesize, gwwbuf, &writewatchcount, &ps)) {
if (GetWriteWatch (WRITE_WATCH_FLAG_RESET, gfxmem_bank.start + natmem_offset, (gwwbufsize - 1) * gwwpagesize, gwwbuf, &writewatchcount, &ps)) {
write_log (_T("picasso_getwritewatch %d\n"), GetLastError ());
writewatchcount = 0;
return;
@ -2072,11 +2068,11 @@ static void init_alloc (TrapContext *ctx, int size)
picasso96_amem = get_long (uaegfx_base + CARD_RESLIST);
} else if (uaegfx_active) {
reserved_gfxmem = size;
picasso96_amem = gfxmem_start + allocated_gfxmem - size;
picasso96_amem = gfxmem_bank.start + gfxmem_bank.allocated - size;
}
picasso96_amemend = picasso96_amem + size;
write_log (_T("P96 RESINFO: %08X-%08X (%d,%d)\n"), picasso96_amem, picasso96_amemend, size / PSSO_ModeInfo_sizeof, size);
picasso_allocatewritewatch (allocated_gfxmem);
picasso_allocatewritewatch (gfxmem_bank.allocated);
}
static int p96depth (int depth)
@ -2124,7 +2120,7 @@ static void picasso96_alloc2 (TrapContext *ctx)
xfree (newmodes);
newmodes = NULL;
picasso96_amem = picasso96_amemend = 0;
if (allocated_gfxmem == 0)
if (gfxmem_bank.allocated == 0)
return;
misscnt = 0;
newmodes = xmalloc (struct PicassoResolution, MAX_PICASSO_MODES);
@ -2356,7 +2352,7 @@ static void addmode (uaecptr AmigaBoardInfo, uaecptr *amem, struct LibResolution
for (depth = 8; depth <= 32; depth++) {
if (!p96depth (depth))
continue;
if(allocated_gfxmem >= w * h * (depth + 7) / 8) {
if(gfxmem_bank.allocated >= w * h * (depth + 7) / 8) {
FillBoardInfo (*amem, res, w, h, depth);
*amem += PSSO_ModeInfo_sizeof;
}
@ -2573,7 +2569,7 @@ static void init_picasso_screen (void)
picasso_refresh ();
}
init_picasso_screen_called = 1;
mman_ResetWatch (p96ram_start + natmem_offset, allocated_gfxmem);
mman_ResetWatch (gfxmem_bank.start + natmem_offset, gfxmem_bank.allocated);
}
@ -4026,8 +4022,8 @@ static void copyall (uae_u8 *src, uae_u8 *dst, int pwidth, int pheight, int srcb
uae_u8 *getrtgbuffer (int *widthp, int *heightp, int *pitch, int *depth, uae_u8 *palette)
{
uae_u8 *src = p96ram_start + natmem_offset;
int off = picasso96_state.XYOffset - gfxmem_start;
uae_u8 *src = gfxmem_bank.start + natmem_offset;
int off = picasso96_state.XYOffset - gfxmem_bank.start;
int width, height, pixbytes;
uae_u8 *dst;
int convert;
@ -4244,74 +4240,11 @@ bool picasso_flushpixels (uae_u8 *src, int off)
return lock != 0;
}
static uae_u32 REGPARAM2 gfxmem_lgetx (uaecptr addr)
{
uae_u32 *m;
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
m = (uae_u32 *)(gfxmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 gfxmem_wgetx (uaecptr addr)
{
uae_u16 *m;
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
m = (uae_u16 *)(gfxmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 gfxmem_bgetx (uaecptr addr)
{
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
return gfxmemory[addr];
}
static void REGPARAM2 gfxmem_lputx (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
m = (uae_u32 *)(gfxmemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 gfxmem_wputx (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
m = (uae_u16 *)(gfxmemory + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 gfxmem_bputx (uaecptr addr, uae_u32 b)
{
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
gfxmemory[addr] = b;
}
static int REGPARAM2 gfxmem_check (uaecptr addr, uae_u32 size)
{
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
return (addr + size) < allocated_gfxmem;
}
static uae_u8 *REGPARAM2 gfxmem_xlate (uaecptr addr)
{
addr -= gfxmem_start & gfxmem_mask;
addr &= gfxmem_mask;
return gfxmemory + addr;
}
MEMORY_FUNCTIONS(gfxmem);
addrbank gfxmem_bank = {
gfxmem_lgetx, gfxmem_wgetx, gfxmem_bgetx,
gfxmem_lputx, gfxmem_wputx, gfxmem_bputx,
gfxmem_lget, gfxmem_wget, gfxmem_bget,
gfxmem_lput, gfxmem_wput, gfxmem_bput,
gfxmem_xlate, gfxmem_check, NULL, _T("RTG RAM"),
dummy_lgeti, dummy_wgeti, ABFLAG_RAM
};
@ -4643,7 +4576,7 @@ static uaecptr uaegfx_card_install (TrapContext *ctx, uae_u32 extrasize)
uaecptr findcardfunc, initcardfunc;
uaecptr exec = get_long (4);
if (uaegfx_old || !gfxmem_start)
if (uaegfx_old || !gfxmem_bank.start)
return NULL;
uaegfx_resid = ds (_T("UAE Graphics Card 3.3"));
@ -4745,7 +4678,7 @@ uae_u32 picasso_demux (uae_u32 arg, TrapContext *ctx)
case 31: return picasso_InvertRect (ctx);
case 32: return picasso_BlitPlanar2Direct (ctx);
//case 34: return picasso_WaitVerticalSync (ctx);
case 35: return allocated_gfxmem ? 1 : 0;
case 35: return gfxmem_bank.allocated ? 1 : 0;
case 36: return picasso_SetSprite (ctx);
case 37: return picasso_SetSpritePosition (ctx);
case 38: return picasso_SetSpriteImage (ctx);

3
od-win32/picasso96_win.h
View File

@ -540,9 +540,6 @@ struct picasso96_state_struct
extern void InitPicasso96 (void);
extern uae_u32 gfxmem_mask;
extern uae_u8 *gfxmemory;
extern int uaegfx_card_found;
extern struct picasso96_state_struct picasso96_state;

4
od-win32/srcrelease.cmd
View File

@ -173,7 +173,7 @@ zip -9 -r winuaesrc *
copy winuaesrc.zip d:\amiga\winuaepackets\winuaesrc%1.zip
move winuaesrc.zip d:\amiga
cd c:\projects\winuae\src\od-win32
zip -9 winuaedebug%1 winuae_msvc10\release\winuae.pdb winuae_msvc10\fullrelease\winuae.pdb
zip -9 winuaedebug%1 winuae_msvc11\release\winuae.pdb winuae_msvc11\fullrelease\winuae.pdb
move winuaedebug%1.zip d:\amiga\winuaepackets\debug\
copy winuae_msvc10\fullrelease\winuae.pdb d:\amiga\dump
copy winuae_msvc11\fullrelease\winuae.pdb d:\amiga\dump
copy d:\amiga\winuae.exe d:\amiga\dump

2
od-win32/win32.cpp
View File

@ -2997,6 +2997,8 @@ void target_fixup_options (struct uae_prefs *p)
p->rtg_hardwareinterrupt = false;
p->rtg_hardwaresprite = false;
p->win32_rtgmatchdepth = false;
if (gfxboard_need_byteswap (p->rtgmem_type))
p->color_mode = 5;
}
}

4
od-win32/win32.h
View File

@ -19,11 +19,11 @@
#define LANG_DLL 1
#if WINUAEPUBLICBETA
#define WINUAEBETA _T("1")
#define WINUAEBETA _T("2")
#else
#define WINUAEBETA _T("")
#endif
#define WINUAEDATE MAKEBD(2013, 7, 7)
#define WINUAEDATE MAKEBD(2013, 7, 18)
#define WINUAEEXTRA _T("")
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")

3
od-win32/win32gui.cpp
View File

@ -142,7 +142,7 @@ static int gui_size_changed;
static int filterstackpos = 2 * MAX_FILTERSHADERS;
static const int defaultaspectratios[] = {
4, 3, 16, 10, 15, 9, 27, 16, 128, 75, 16, 9, 256, 135, 21, 9, 16, 3,
5, 4, 4, 3, 16, 10, 15, 9, 27, 16, 128, 75, 16, 9, 256, 135, 21, 9, 16, 3,
-1
};
static int getaspectratioindex (int ar)
@ -7456,6 +7456,7 @@ static INT_PTR CALLBACK ExpansionDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LP
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Picasso II Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Picasso II+ Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo Zorro III"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo SD64 Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo SD64 Zorro III"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Spectrum28/24 Zorro II"));

11
od-win32/winuae_msvc11/winuae_msvc.vcxproj
View File

@ -45,7 +45,7 @@
<UseOfMfc>false</UseOfMfc>
<CharacterSet>Unicode</CharacterSet>
<WholeProgramOptimization>true</WholeProgramOptimization>
<PlatformToolset>v110_xp</PlatformToolset>
<PlatformToolset>v120_xp</PlatformToolset>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>Application</ConfigurationType>
@ -617,7 +617,7 @@
<FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
<OmitFramePointers>true</OmitFramePointers>
<WholeProgramOptimization>true</WholeProgramOptimization>
<AdditionalIncludeDirectories>..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<AdditionalIncludeDirectories>..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<PreprocessorDefinitions>WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<StringPooling>true</StringPooling>
<ExceptionHandling>Sync</ExceptionHandling>
@ -648,13 +648,13 @@
<Culture>0x0409</Culture>
</ResourceCompile>
<Link>
<AdditionalDependencies>ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;winio.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;libpng15.lib;lglcd.lib;wpcap.lib;packet.lib;openal32.lib;wintab32.lib;portaudio_x86.lib;vfw32.lib;wtsapi32.lib;avrt.lib;enet.lib;prowizard.lib;lzmalib.lib;libFLAC_static.lib;Avrt.lib;hid.lib;%(AdditionalDependencies)</AdditionalDependencies>
<AdditionalDependencies>ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;winio.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;libpng15.lib;lglcd.lib;wpcap.lib;packet.lib;openal32.lib;wintab32.lib;portaudio_x86.lib;vfw32.lib;wtsapi32.lib;avrt.lib;enet.lib;prowizard.lib;lzmalib.lib;libFLAC_static.lib;Avrt.lib;hid.lib;Iphlpapi.lib;luastatic.lib;%(AdditionalDependencies)</AdditionalDependencies>
<OutputFile>$(OutDir)$(TargetName)$(TargetExt)</OutputFile>
<SuppressStartupBanner>true</SuppressStartupBanner>
<AdditionalLibraryDirectories>%(AdditionalLibraryDirectories);$(SolutionDir)\..\lib\</AdditionalLibraryDirectories>
<AdditionalManifestDependencies>%(AdditionalManifestDependencies)</AdditionalManifestDependencies>
<IgnoreSpecificDefaultLibraries>%(IgnoreSpecificDefaultLibraries)</IgnoreSpecificDefaultLibraries>
<DelayLoadDLLs>wpcap.dll;packet.dll;d3dx9_43.dll;openal32.dll;wintab32.dll;portaudio_x86.dll;ws2_32.dll;msacm32.dll;wtsapi32.dll;dsound.dll;wininet.dll;avrt.dll;ddraw.dll;%(DelayLoadDLLs)</DelayLoadDLLs>
<DelayLoadDLLs>wpcap.dll;packet.dll;d3dx9_43.dll;openal32.dll;wintab32.dll;portaudio_x86.dll;ws2_32.dll;msacm32.dll;wtsapi32.dll;dsound.dll;wininet.dll;avrt.dll;ddraw.dll;Iphlpapi.dll;%(DelayLoadDLLs)</DelayLoadDLLs>
<GenerateDebugInformation>true</GenerateDebugInformation>
<ProgramDatabaseFile>.\FullRelease/winuae.pdb</ProgramDatabaseFile>
<SubSystem>Windows</SubSystem>
@ -662,7 +662,7 @@
<StackCommitSize>2621440</StackCommitSize>
<LargeAddressAware>true</LargeAddressAware>
<OptimizeReferences>true</OptimizeReferences>
<EnableCOMDATFolding>true</EnableCOMDATFolding>
<EnableCOMDATFolding>false</EnableCOMDATFolding>
<LinkTimeCodeGeneration>UseLinkTimeCodeGeneration</LinkTimeCodeGeneration>
<RandomizedBaseAddress>true</RandomizedBaseAddress>
<FixedBaseAddress>false</FixedBaseAddress>
@ -670,6 +670,7 @@
<TargetMachine>MachineX86</TargetMachine>
<MinimumRequiredVersion>5.01</MinimumRequiredVersion>
<ImageHasSafeExceptionHandlers>false</ImageHasSafeExceptionHandlers>
<SetChecksum>true</SetChecksum>
</Link>
<Manifest>
<AdditionalManifestFiles>../resources/winuae.exe.manifest</AdditionalManifestFiles>

93
od-win32/winuaechangelog.txt
View File

@ -1,6 +1,99 @@
- restore only single input target to default.
Beta 1:
- Hardware Cirrus Logic based SVGA Zorro II/III RTG board emulation.
- SLIRP user mode NAT emulation.
- Added SCSI tape emulation. Amix tape based install works, also tested with
Quarterback and Diavolo.
- lua scripting support added from fs-uae. Very minimal at the moment.
- SCSI HD/CD/TAPE statefile compatibility improved.
- SCSI emulation compatibility improved, Amix use of WD Select and Transfer
used wrong data size when direction was from WD to device and command was not
write command, for example MODE SELECT.
- Show custom chip mode as interlace/not interlaced decision now more closely matches
real hardware behavior. (No, it isn't as simple as BPLCON0 LACE bit set/not set)
- Show also device type (HDF, CD, TAPE) in Harddrives panel.
- Joystick axis dead-zone fix, wired xbox 360 d-pad missed events, it didn't affect
wireless version. (261b2)
- Top and/or bottom border showed graphics garbage if AGA sprites outside of bitplane
area feature was enabled and in use and screen mode was HAM. (Tint / Black Lotus)
- Dragging and dropping archive/file to WB tried (unsuccesfully) replace already
existing normal directory harddrive if dropped file and directory harddrive had same
base path.
- Renamed CPU cycle exact speed multipliers and added 1x speed (1:1 CPU/DMA clock sync)
- It was impossible to select RTG aspect ratio select box Automatic value.
- Display panel depth select box was not updated if new resolution had more or less
depth choices than previously selected resolution.
- Mouse was captured even if "Start mouse uncaptured" was ticked and booting to RTG mode.
- Amiga side does not anymore see .lnk extension if it is valid Windows shortcut softlink.
- Enabling JIT for the first time in GUI now always forces JIT Direct mode.
- If blitter was started one cycle before final D write (Cycle which is always unused by
blitter), new blit's 2 cycle startup incorrectly accepted DMA cycles that were not free.
(Day of Reckoning / Digital)
- Bitplane DMA incorrectly stole sprite DMA in some situations (Plastic Passion / Upfront)
- Sync clock when resuming from sleep/hibernate (if clock sync option is ticked)
SLIRP notes:
- Available for A2065 and uaenet.device (uaenet unit 0 = slirp, 1 = first WinPCap device)
- Does not need any drivers, uses normal WinSock API.
- NAT, outbound connections only.
- TCP and UDP only (no ICMP or other ethernet frame types)
- DHCP supported.
- Manual settings: IP 10.0.2.15, Gateway 10.0.2.2, DNS 10.0.2.3, Mask 255.255.255.0.
Hardware graphics board emulation notes:
- Currently emulates following Cirrus Logic GD542X/543X based boards:
- Picasso II
- Picasso II+
- Piccolo
- Piccolo SD 64 (Zorro II and III)
- Spectrum 28/24 (Zorro II and III)
- Picasso IV may be implemented in future.
- Uses QEMU Cirrus Logic SVGA graphics chip emulation.
- Picasso 96 and CyberGraphX v4 tested.
- Works with non-AmigaOS operating systems that don't support UAEGFX RTG board.
- Vertical blank timing uses GUI configured refresh rate value, display sync settings programmed
to VGA chip are completely ignored.
- Only single VRAM size supported which is hardware supported max VRAM. Smaller VRAM requires
emulating of VRAM aliasing and banking stuff that drivers use for VRAM size detection. It would
become too Direct mode JIT unfriendly. Future "more compatible but slower" option is possible.
SCSI Tape notes:
- Tape path can point to directory, archive or plain file.
- Directory: all files in directory are included in virtual tape, ordered in whatever
order OS returns the directory (unless index.tape is found), emulated file mark
is between each file. Subdirectories are ignored.
- Archive: All files in archive are included, including subdirectories.
- Plain single file: tape only contains selected single file.
- If directory or archive and index.tape is found, it is assumed to contain order of
files in virtual tape, plain file name strings separated by line feeds.
- Writing is also supported if path points to a directory. Creates files named
xxxxx.tape where xxxxx is file number.
- Tape ERASE command only deletes files that have extension .tape to prevent
accidental data loss. Subdirectories are also ignored.
- Can be connected to SCSI hardware emulation (SCSI0-6) or uaescsi.device (UAE),
uaescsi.device unit number is always 4 or larger (if 4 was already used by
some CD device).
- Tape change on the fly is supported.
lua scripting:
- very minimal and basic at the moment.
- lua=<path to script> in config file, multiple files supported.
- lua/default.lua is loaded by default.
- supported UAE-specific functions:
uae_log, uae_read_u8, uae_read_u16, uae_peek_u16, uae_write_u8, uae_write_u16
uae_read_config, uae_write_config.
- lua functions:
on_uae_vsync (every vsync)
on_uae_config_changed (any config value has changed)
2.6.1
Beta 4:

27
qemuvga/cirrus_vga.cpp
View File

@ -28,7 +28,7 @@
*/
#if 0
#include "hw/hw.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci.h"6
#include "ui/console.h"
#include "vga_int.h"
#include "hw/loader.h"
@ -44,7 +44,9 @@
*/
//#define DEBUG_CIRRUS
//#define DEBUG_VGA_REG
//#define DEBUG_BITBLT
#define TARGET_FMT_plx "%x"
/***************************************
*
@ -976,8 +978,10 @@ static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
if (((old_value & CIRRUS_BLT_RESET) != 0) &&
((reg_value & CIRRUS_BLT_RESET) == 0)) {
cirrus_bitblt_reset(s);
} else if (((old_value & CIRRUS_BLT_START) == 0) &&
((reg_value & CIRRUS_BLT_START) != 0)) {
}
// Blitter will start if old = CIRRUS_BLT_RESET and new = CIRRUS_BLT_START. TW.
if (((old_value & CIRRUS_BLT_START) == 0) &&
((reg_value & (CIRRUS_BLT_START | CIRRUS_BLT_RESET)) == CIRRUS_BLT_START)) {
cirrus_bitblt_start(s);
}
}
@ -1087,7 +1091,7 @@ static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
int width, height;
width = (s->cr[0x01] + 1) * 8;
/* TW: if 16 bit mdoe but SR7 bit 7 == 0: 2x width and palette mode */
/* TW: if 16 bit mode but SR7 bit 7 == 0: 2x width and palette mode */
if ((cs->cirrus_hidden_dac_data & 0x80) == 0) {
switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
@ -1333,7 +1337,7 @@ static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
if (s->cirrus_hidden_dac_lockindex == 4) {
s->cirrus_hidden_dac_data = reg_value;
s->vga.gr[5] |= 0x40;
//s->vga.gr[5] |= 0x40; /* TW */
#if defined(DEBUG_CIRRUS)
@ -1368,9 +1372,11 @@ static int cirrus_vga_read_palette(CirrusVGAState * s)
static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
{
// if (s->vga.dac_write_index < 8)
// write_log ("PAL: %d %d: %02X\n", s->vga.dac_write_index, s->vga.dac_sub_index, reg_value);
s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
#ifdef DEBUG_CIRRUS
if (s->vga.dac_write_index < 16)
write_log ("PAL: %d %d: %02X\n", s->vga.dac_write_index, s->vga.dac_sub_index, reg_value);
#endif
s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
if (++s->vga.dac_sub_index == 3) {
if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
@ -1422,8 +1428,9 @@ static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
static void
cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
{
#if defined(DEBUG_BITBLT) && 0
write_log("gr%02x: %02x\n", reg_index, reg_value);
#if defined(DEBUG_CIRRUS)
if (reg_index > 1 && reg_index < 0x10)
write_log("gr%02x: %02x\n", reg_index, reg_value);
#endif
switch (reg_index) {
case 0x00: // Standard VGA, BGCOLOR 0x000000ff

14
qemuvga/qemuuaeglue.cpp
View File

@ -12,13 +12,6 @@ void memory_region_transaction_commit(void)
void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, hwaddr size)
{
}
void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
{
}
void memory_region_set_alias_offset(MemoryRegion *mr,
hwaddr offset)
{
}
void memory_region_add_subregion(MemoryRegion *mr,
hwaddr offset,
MemoryRegion *subregion)
@ -37,13 +30,6 @@ void memory_region_del_subregion(MemoryRegion *mr,
void memory_region_destroy(MemoryRegion *mr)
{
}
void memory_region_init_alias(MemoryRegion *mr,
const char *name,
MemoryRegion *orig,
hwaddr offset,
uint64_t size)
{
}
void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
{
}

5
qemuvga/vga.cpp
View File

@ -1679,6 +1679,11 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
disp_width = width;
shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
// cirrus hack TW
if (s->sr[7] & 1)
shift_control = 2;
double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
if (shift_control != 1) {
multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)

6
sana2.cpp
View File

@ -335,7 +335,7 @@ static int initint (TrapContext *ctx)
put_long (p + 10, ROM_netdev_resid);
put_long (p + 18, tmp1);
m68k_areg (regs, 1) = p;
m68k_dreg (regs, 0) = 13; /* EXTER */
m68k_dreg (regs, 0) = 3; /* PORTS */
dw (0x4a80); /* TST.L D0 */
dw (0x4e75); /* RTS */
CallLib (ctx, get_long (4), -168); /* AddIntServer */
@ -1435,6 +1435,7 @@ static uae_u32 REGPARAM2 uaenet_int_handler (TrapContext *ctx)
if (handleread (ctx, pdev, request, p->data, p->len, command)) {
if (log_net)
write_log (_T("-> %p Accepted, CMD_READ, REQ=%08X LEN=%d\n"), p, request, p->len);
ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
dev->packetsreceived++;
gotit = 1;
@ -1460,6 +1461,7 @@ static uae_u32 REGPARAM2 uaenet_int_handler (TrapContext *ctx)
if (log_net)
write_log (_T("-> %p Accepted, S2_READORPHAN, REQ=%08X LEN=%d\n"), p, request, p->len);
handleread (ctx, pdev, request, p->data, p->len, command);
ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
dev->packetsreceived++;
dev->unknowntypesreceived++;
@ -1515,6 +1517,7 @@ static uae_u32 REGPARAM2 uaenet_int_handler (TrapContext *ctx)
dev->online_micro = get_long (pdev->tempbuf + 4);
checkevents (dev, S2EVENT_ONLINE, 0);
dev->online = 1;
ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
uaenet_vsync_requested--;
} else if (command == CMD_FLUSH) {
@ -1522,6 +1525,7 @@ static uae_u32 REGPARAM2 uaenet_int_handler (TrapContext *ctx)
if (dev->ar->next == NULL) {
if (log_net)
write_log (_T("CMD_FLUSH replied %08x\n"), request);
ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
uaenet_vsync_requested--;
} else {

2
savestate.cpp
View File

@ -1261,7 +1261,7 @@ void savestate_rewind (void)
p = restore_p96 (p);
#endif
len = restore_u32_func (&p);
memcpy (chipmemory, p, currprefs.chipmem_size > len ? len : currprefs.chipmem_size);
memcpy (chipmem_bank.baseaddr, p, currprefs.chipmem_size > len ? len : currprefs.chipmem_size);
p += len;
len = restore_u32_func (&p);
memcpy (save_bram (&dummy), p, currprefs.bogomem_size > len ? len : currprefs.bogomem_size);

2
scsi.cpp
View File

@ -89,7 +89,7 @@ void scsi_clear_sense(struct scsi_data *sd)
}
static void showsense(struct scsi_data *sd)
{
#if 1
#if 0
write_log (_T("REQUEST SENSE %d, "), sd->data_len);
for (int i = 0; i < sd->data_len; i++) {
if (i > 0)

6
uaelib.cpp
View File

@ -221,9 +221,9 @@ static uae_u32 emulib_GetUaeConfig (uaecptr place)
int i, j;
put_long (place, version);
put_long (place + 4, allocated_chipmem);
put_long (place + 8, allocated_bogomem);
put_long (place + 12, allocated_fastmem);
put_long (place + 4, chipmem_bank.allocated);
put_long (place + 8, bogomem_bank.allocated);
put_long (place + 12, fastmem_bank.allocated);
put_long (place + 16, currprefs.gfx_framerate);
put_long (place + 20, currprefs.produce_sound);
put_long (place + 24, currprefs.jports[0].id | (currprefs.jports[1].id << 8));