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DCE Typhoon MK 2.

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This commit is contained in:
Toni Wilen 2018-04-23 22:00:47 +03:00
parent 2807400085
commit 14367a04fa
7 changed files with 103 additions and 48 deletions
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54
cpuboard.cpp
View File

@ -309,6 +309,10 @@ static bool is_mtec_ematrix530(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530);
}
static bool is_dce_typhoon2(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_DCE, BOARD_DCE_SUB_TYPHOON2);
}
static bool is_fusionforty(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_RCS, BOARD_RCS_SUB_FUSIONFORTY);
@ -792,24 +796,24 @@ static uae_u32 REGPARAM2 blizzardea_bget(uaecptr addr)
} else {
v = blizzardea_bank.baseaddr[addr];
}
} else if (is_mtec_ematrix530(&currprefs)) {
} else if (is_mtec_ematrix530(&currprefs) || is_dce_typhoon2(&currprefs)) {
v = blizzardea_bank.baseaddr[addr];
if ((addr & 0xf800) == 0xe800) {
if ((addr & 3) < 2) {
map_banks(&dummy_bank, 0x10000000 >> 16, 0x8000000 >> 16, 0);
if (custmem1_bank.allocated_size) {
map_banks(&custmem1_bank, (0x18000000 - custmem1_bank.allocated_size) >> 16, custmem1_bank.allocated_size >> 16, 0);
if (custmem1_bank.allocated_size < 128 * 1024 * 1024) {
map_banks(&custmem1_bank, (0x18000000 - 2 * custmem1_bank.allocated_size) >> 16, custmem1_bank.allocated_size >> 16, 0);
if (cpuboardmem1_bank.allocated_size) {
map_banks(&cpuboardmem1_bank, (0x18000000 - cpuboardmem1_bank.allocated_size) >> 16, cpuboardmem1_bank.allocated_size >> 16, 0);
if (cpuboardmem1_bank.allocated_size < 128 * 1024 * 1024) {
map_banks(&cpuboardmem1_bank, (0x18000000 - 2 * cpuboardmem1_bank.allocated_size) >> 16, cpuboardmem1_bank.allocated_size >> 16, 0);
}
}
}
if ((addr & 3) >= 2) {
map_banks(&dummy_bank, 0x18000000 >> 16, 0x8000000 >> 16, 0);
if (custmem2_bank.allocated_size) {
map_banks(&custmem2_bank, 0x18000000 >> 16, custmem2_bank.allocated_size >> 16, 0);
if (custmem2_bank.allocated_size < 128 * 1024 * 1024) {
map_banks(&custmem2_bank, (0x18000000 + custmem2_bank.allocated_size) >> 16, custmem2_bank.allocated_size >> 16, 0);
if (cpuboardmem2_bank.allocated_size) {
map_banks(&cpuboardmem2_bank, 0x18000000 >> 16, cpuboardmem2_bank.allocated_size >> 16, 0);
if (cpuboardmem2_bank.allocated_size < 128 * 1024 * 1024) {
map_banks(&cpuboardmem2_bank, (0x18000000 + cpuboardmem2_bank.allocated_size) >> 16, cpuboardmem2_bank.allocated_size >> 16, 0);
}
}
}
@ -864,17 +868,17 @@ static void REGPARAM2 blizzardea_bput(uaecptr addr, uae_u32 b)
addr |= csmk2_flashaddressing;
flash_write(flashrom, addr, b);
}
} else if (is_mtec_ematrix530(&currprefs)) {
} else if (is_mtec_ematrix530(&currprefs) || is_dce_typhoon2(&currprefs)) {
if ((addr & 0xf800) == 0xe800) {
if ((addr & 3) < 2) {
map_banks(&dummy_bank, 0x10000000 >> 16, 0x8000000 >> 16, 0);
if (custmem1_bank.allocated_size)
map_banks(&custmem1_bank, (0x18000000 - custmem1_bank.allocated_size) >> 16, custmem1_bank.allocated_size >> 16, 0);
if (cpuboardmem1_bank.allocated_size)
map_banks(&cpuboardmem1_bank, (0x18000000 - cpuboardmem1_bank.allocated_size) >> 16, cpuboardmem1_bank.allocated_size >> 16, 0);
}
if ((addr & 3) >= 2) {
map_banks(&dummy_bank, 0x18000000 >> 16, 0x8000000 >> 16, 0);
if (custmem2_bank.allocated_size)
map_banks(&custmem2_bank, 0x18000000 >> 16, custmem2_bank.allocated_size >> 16, 0);
if (cpuboardmem2_bank.allocated_size)
map_banks(&cpuboardmem2_bank, 0x18000000 >> 16, cpuboardmem2_bank.allocated_size >> 16, 0);
}
}
}
@ -1635,7 +1639,7 @@ void cpuboard_map(void)
}
}
if (is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs) || is_apollo(&currprefs)) {
if (is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs) || is_apollo(&currprefs) || is_dce_typhoon2(&currprefs)) {
if (cpuboardmem1_bank.allocated_size) {
map_banks(&cpuboardmem1_bank, cpuboardmem1_bank.start >> 16, cpuboardmem1_bank.allocated_size >> 16, 0);
}
@ -1785,13 +1789,13 @@ static void cpuboard_init_2(void)
cpuboardmem1_bank.reserved_size = 0;
cpuboardmem2_bank.reserved_size = 0;
if (is_kupke(&currprefs) || is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs)) {
if (is_kupke(&currprefs) || is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs) || is_dce_typhoon2(&currprefs)) {
// plain 64k autoconfig, nothing else.
blizzardea_bank.reserved_size = 65536;
blizzardea_bank.mask = blizzardea_bank.reserved_size - 1;
mapped_malloc(&blizzardea_bank);
if (is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs)) {
if (is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs) || is_dce_typhoon2(&currprefs)) {
cpuboardmem1_bank.start = 0x18000000 - cpuboard_size;
cpuboardmem1_bank.reserved_size = cpuboard_size;
cpuboardmem1_bank.mask = cpuboardmem1_bank.reserved_size - 1;
@ -2369,7 +2373,7 @@ bool cpuboard_autoconfig_init(struct autoconfig_info *aci)
case BOARD_MTEC:
switch (p->cpuboard_subtype)
{
case BOARD_MTEC_SUB_EMATRIX530:
case BOARD_MTEC_SUB_EMATRIX530:
romtype = ROMTYPE_CB_EMATRIX;
break;
}
@ -2501,8 +2505,16 @@ bool cpuboard_autoconfig_init(struct autoconfig_info *aci)
break;
case BOARD_DCE:
romtype = ROMTYPE_CB_SX32PRO;
break;
switch (p->cpuboard_subtype)
{
case BOARD_DCE_SUB_SX32PRO:
romtype = ROMTYPE_CB_SX32PRO;
break;
case BOARD_DCE_SUB_TYPHOON2:
romtype = ROMTYPE_CB_TYPHOON2;
break;
}
break;
case BOARD_HARDITAL:
switch (p->cpuboard_subtype)
@ -2594,7 +2606,7 @@ bool cpuboard_autoconfig_init(struct autoconfig_info *aci)
blizzardea_bank.baseaddr[i * 2 + 0] = b;
blizzardea_bank.baseaddr[i * 2 + 1] = 0xff;
}
} else if (is_mtec_ematrix530(p)) {
} else if (is_mtec_ematrix530(p) || is_dce_typhoon2(p)) {
earom_size = 65536;
for (int i = 0; i < 32768; i++) {
uae_u8 b = 0xff;

10
expansion.cpp
View File

@ -6033,6 +6033,16 @@ static const struct cpuboardsubtype dceboard_sub[] = {
BOARD_MEMORY_CUSTOM_32,
64 * 1024 * 1024
},
{
_T("Typhoon MK2"),
_T("typhoon2"),
ROMTYPE_CB_TYPHOON2, 0,
typhoon2scsi_add_scsi_unit, EXPANSIONTYPE_SCSI,
BOARD_MEMORY_CUSTOM_32,
128 * 1024 * 1024,
0,
typhoon2scsi_init, NULL, BOARD_AUTOCONFIG_Z2, 1
},
{
NULL
}

2
include/cpuboard.h
View File

@ -55,6 +55,8 @@ void blizzardppc_irq_setonly(int id, int level);
#define BOARD_COMMODORE_SUB_A26x0 0
#define BOARD_DCE 3
#define BOARD_DCE_SUB_SX32PRO 0
#define BOARD_DCE_SUB_TYPHOON2 1
#define BOARD_DKB 4
#define BOARD_DKB_SUB_12x0 0

2
include/ncr9x_scsi.h
View File

@ -19,6 +19,7 @@ extern void golemfast_add_scsi_unit(int ch, struct uaedev_config_info *ci, struc
extern void scram5394_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern void rapidfire_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern void alf3_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern void typhoon2scsi_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern bool ncr_fastlane_autoconfig_init(struct autoconfig_info *aci);
extern bool ncr_oktagon_autoconfig_init(struct autoconfig_info *aci);
@ -28,6 +29,7 @@ extern bool ncr_multievolution_init(struct autoconfig_info *aci);
extern bool ncr_scram5394_init(struct autoconfig_info *aci);
extern bool ncr_rapidfire_init(struct autoconfig_info *aci);
extern bool ncr_alf3_autoconfig_init(struct autoconfig_info *aci);
extern bool typhoon2scsi_init(struct autoconfig_info *aci);
extern void cpuboard_ncr9x_scsi_put(uaecptr, uae_u32);
extern uae_u32 cpuboard_ncr9x_scsi_get(uaecptr);

1
include/rommgr.h
View File

@ -47,6 +47,7 @@ extern int decode_cloanto_rom_do (uae_u8 *mem, int size, int real_size);
#define ROMTYPE_CB_TQM 0x0004001a
#define ROMTYPE_CB_FALCON40 0x0004001b
#define ROMTYPE_CB_A1230S2 0x0004001c
#define ROMTYPE_CB_TYPHOON2 0x0004001d
#define ROMTYPE_FREEZER 0x00080000
#define ROMTYPE_AR 0x00080001

78
ncr9x_scsi.cpp
View File

@ -166,6 +166,7 @@ static struct ncr9x_state *ncr_masoboshi_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr9x_state *ncr_dkb1200_scsi;
static struct ncr9x_state *ncr_ematrix530_scsi;
static struct ncr9x_state *ncr_multievolution_scsi;
static struct ncr9x_state *ncr_typhoon2_scsi;
static struct ncr9x_state *ncr_golemfast_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr9x_state *ncr_scram5394_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr9x_state *ncr_rapidfire_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
@ -1067,7 +1068,7 @@ static void ncr9x_io_bput3(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val, i
write_log(_T("DKB IO %08X PUT %02x %08x\n"), addr, val & 0xff, M68K_GETPC);
return;
}
} else if (ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530)) {
} else if (ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530) || ISCPUBOARD(BOARD_DCE, BOARD_DCE_SUB_TYPHOON2)) {
if ((addr & 0xf000) >= 0xe000) {
if ((addr & 0x3ff) <= 7) {
if (ncr->fakedma_data_offset < ncr->fakedma_data_size) {
@ -1405,7 +1406,7 @@ static uae_u32 ncr9x_io_bget3(struct ncr9x_state *ncr, uaecptr addr, int *reg)
write_log(_T("DKB IO GET %08x %08x\n"), addr, M68K_GETPC);
return 0;
}
} else if (ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530)) {
} else if (ISCPUBOARD(BOARD_MTEC, BOARD_MTEC_SUB_EMATRIX530) || ISCPUBOARD(BOARD_DCE, BOARD_DCE_SUB_TYPHOON2)) {
if ((addr & 0xf000) >= 0xe000) {
if ((addr & 0x3ff) <= 7) {
if (ncr->fakedma_data_offset >= ncr->fakedma_data_size) {
@ -2052,41 +2053,59 @@ bool ncr_dkb_autoconfig_init(struct autoconfig_info *aci)
return true;
}
bool ncr_ematrix_autoconfig_init(struct autoconfig_info *aci)
bool typhoon2scsi_init(struct autoconfig_info *aci)
{
struct zfile *z = read_device_from_romconfig(aci->rc, ROMTYPE_CB_EMATRIX);
uae_u8 *rom = xcalloc(uae_u8, 65536);
if (z) {
int i;
memset(rom, 0xff, 65536);
zfile_fseek(z, 32768, SEEK_SET);
for (i = 0; i < (sizeof aci->autoconfig_raw) / 2; i++) {
uae_u8 b;
zfile_fread(&b, 1, 1, z);
aci->autoconfig_raw[i * 2] = b;
}
for (;;) {
uae_u8 b;
if (!zfile_fread(&b, 1, 1, z))
break;
rom[i * 2] = b;
i++;
}
zfile_fclose(z);
}
load_rom_rc(aci->rc, ROMTYPE_CB_TYPHOON2, 32768, 32768, rom, 65536, LOADROM_EVENONLY_ODDONE);
memcpy(aci->autoconfig_raw, aci->rc->autoboot_disabled ? rom + 256 : rom, 128);
if (!aci->doinit) {
xfree(rom);
return true;
}
struct ncr9x_state *ncr = getscsi(aci->rc);
if (!ncr)
if (!ncr) {
xfree(rom);
return false;
}
xfree(ncr->rom);
ncr->rom = NULL;
ncr->rom = rom;
ncr->enabled = true;
memcpy(ncr->acmemory, aci->autoconfig_raw, sizeof aci->autoconfig_raw);
ncr->rom_start = 0;
ncr->rom_offset = 0;
ncr->rom_end = 0x8000;
ncr->io_start = 0x8000;
ncr->io_end = 0x10000;
ncr->bank = &ncr9x_bank_generic;
ncr->board_mask = 65535;
ncr9x_reset_board(ncr);
aci->addrbank = ncr->bank;
return true;
}
bool ncr_ematrix_autoconfig_init(struct autoconfig_info *aci)
{
uae_u8 *rom = xcalloc(uae_u8, 65536);
load_rom_rc(aci->rc, ROMTYPE_CB_EMATRIX, 32768, 32768, rom, 65536, LOADROM_EVENONLY_ODDONE);
memcpy(aci->autoconfig_raw, aci->rc->autoboot_disabled ? rom + 256 : rom, 128);
if (!aci->doinit) {
xfree(rom);
return true;
}
struct ncr9x_state *ncr = getscsi(aci->rc);
if (!ncr) {
xfree(rom);
return false;
}
xfree(ncr->rom);
ncr->rom = rom;
ncr->enabled = true;
memcpy(ncr->acmemory, aci->autoconfig_raw, sizeof aci->autoconfig_raw);
@ -2352,4 +2371,11 @@ void rapidfire_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romco
esp_dma_enable(ncr_rapidfire_scsi[ci->controller_type_unit]->devobject.lsistate, 1);
}
void typhoon2scsi_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
{
ncr9x_add_scsi_unit(&ncr_typhoon2_scsi, ch, ci, rc);
ncr9x_esp_scsi_init(ncr_typhoon2_scsi, fake_dma_read_ematrix, fake_dma_write_ematrix, set_irq2, 0);
esp_dma_enable(ncr_typhoon2_scsi->devobject.lsistate, 1);
}
#endif

4
rommgr.cpp
View File

@ -95,7 +95,7 @@ struct romdata *getromdatabypath (const TCHAR *path)
return NULL;
}
#define NEXT_ROM_ID 236
#define NEXT_ROM_ID 237
#define ALTROM(id,grp,num,size,flags,crc32,a,b,c,d,e) \
{ _T("X"), 0, 0, 0, 0, 0, size, id, 0, 0, flags, (grp << 16) | num, 0, NULL, crc32, a, b, c, d, e },
@ -451,6 +451,8 @@ static struct romdata roms[] = {
0xb2dae8c4, 0xcdfe2d96, 0xe44d4f8d, 0x3833a5e8, 0xb6c832fd, 0xc7b341a9, NULL, NULL },
{ _T("M-Tec E-Matrix 530"), 0, 0, 0, 0, _T("EMATRIX530\0"), 65536, 144, 0, 0, ROMTYPE_CB_EMATRIX, 0, 0, NULL,
0x3942d827, 0x5aaf118f, 0x61fc3083, 0x1435b87c, 0x8bdab6a4, 0x59b4ee22, NULL, NULL },
{ _T("Typhoon MK2"), 0, 0, 0, 0, _T("TYPHOON2\0"), 65536, 236, 0, 0, ROMTYPE_CB_TYPHOON2, 0, 0, NULL,
0xf5edf7e2, 0xf62bab24, 0xeaa91a16, 0x07d838af, 0x7b5fef4d, 0x05c58edc, NULL, NULL },
{ _T("SX32 Pro"), 0, 0, 0, 0, _T("SX32PRO\0"), 65536, 160, 0, 0, ROMTYPE_CB_SX32PRO, 0, 0, NULL,
0xbfd68a88, 0x84a50880, 0x76917549, 0xadf33b16, 0x8a869adb, 0x9e5a6fac, NULL, NULL },
{ _T("IVS Vector 4.14"), 4, 14, 4, 14, _T("VECTOR030\0"), 65536, 166, 0, 0, ROMTYPE_CB_VECTOR, 0, 0, NULL,