LIV2/VGA-6502
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Fix incorrect vertical sync polarity

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This commit is contained in:
Matt Harlum 2020-10-21 22:51:50 +02:00
parent 70280e96f7
commit 4781dba6bf
1 changed files with 3 additions and 3 deletions
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6
VHDL/VGA6502/vga6502.vhd
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@ -132,7 +132,7 @@ begin
if LATCH = '0' then
FF_CURSOR <= M_CURSOR;
FF_BLANK <= VIDEN;
FF_VSYNC <= M_VSYNC;
FF_VSYNC <= M_VSYNC XOR REG_MODE; /* Positive VSYNC for 640x400 mode */
FF_HSYNC <= M_HSYNC;
else
FF_CURSOR <= FF_CURSOR;
@ -278,9 +278,9 @@ process(H_END)
begin
if falling_edge(H_END) then
if (V_CNTR < V_SW) then
M_VSYNC <= '1';
else
M_VSYNC <= '0';
else
M_VSYNC <= '1';
end if;
end if;
end process;