mirror of
https://github.com/LIV2/RIPPLE-IDE.git
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64 lines
1.5 KiB
Makefile
64 lines
1.5 KiB
Makefile
PROJECT=RIPPLE
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PART=XC9572XL-10-VQ64
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WORKDIR=tmp
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SERIAL=0
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PRODID=72
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DEFINES=makedefines SERIAL=32'h${SERIAL} PRODID=${PRODID}
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CABLE=usb21
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CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper -optimize speed -pterms 21
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.PHONY: all clean timing
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all: $(PROJECT).jed timing
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$(PROJECT).prj: *.v
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-$(shell rm -f $@)
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-$(foreach source,$^,$(shell echo verilog work $(source) >> $@))
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$(WORKDIR)/$(PROJECT).ngc: *.v $(PROJECT).prj
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-@mkdir $(WORKDIR)
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@sed -r "s#^(-ofn).*#\1 ..\/$@#g;s#^(-ifn).*#\1 ../$(PROJECT).prj#g;s#^(-define).*#\1 {$(DEFINES)}#g" template.xst > $@.xst
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cd $(WORKDIR) && xst -ifn ../$@.xst -ofn $(PROJECT)-xst.log
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$(WORKDIR)/%.ngd: $(WORKDIR)/%.ngc $(PROJECT).ucf
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cd $(WORKDIR) && ngdbuild -p $(PART) -uc ../$(PROJECT).ucf ../$< ../$@
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$(WORKDIR)/%.rpt $(WORKDIR)/%.vm6: $(WORKDIR)/%.ngd $(PROJECT).ucf
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cd $(WORKDIR) && cpldfit $(CPLDFITFLAGS) -p $(PART) ../$< | egrep -v "^CS: block|^$$"
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cp $(WORKDIR)/$(PROJECT).rpt .
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%.jed: $(WORKDIR)/%.vm6
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hprep6 -i $<
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cp $@ ../Binary/
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fit: $(WORKDIR)/$(PROJECT).vm6
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%.tim: $(WORKDIR)/%.vm6
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cd $(WORKDIR) && taengine -l ../$@ -f $(PROJECT)
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timing: $(PROJECT).tim
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%.tim: $(WORKDIR)/%.vm6
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cd $(WORKDIR) && taengine -l ../$@ -f $(PROJECT)
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timing: $(PROJECT).tim
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clean:
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-rm -rvf tmp
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-rm *.jed
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-rm *.prj
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flash: $(PROJECT).jed
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@echo "setMode -bs\n"\
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"setCable -p $(CABLE)\n"\
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"identify\n"\
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"assignfile -p 1 -file $<\n"\
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"erase -p 1\n"\
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"program -p 1\n"\
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"verify -p 1" | LD_PRELOAD=/opt/Xilinx/usb-driver/libusb-driver.so impact -batch
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