mirror of
https://github.com/LIV2/RIPPLE-IDE.git
synced 2025-12-06 04:32:42 +00:00
Use allocated RIPPLE product id
This commit is contained in:
parent
1de917e2a8
commit
c39d84a8c9
@ -1,5 +1,5 @@
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Programmer Jedec Bit Map
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Date Extracted: Sat Nov 18 19:39:01 2023
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Date Extracted: Fri Dec 15 18:32:43 2023
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QF46656*
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QP64*
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@ -249,8 +249,8 @@ L0005312 00000000 00000011 00000000 00000011*
|
||||
L0005344 00000000 00000011 00000000 00000011*
|
||||
L0005376 00000000 00000011 00000001 00000011*
|
||||
L0005408 00000000 00000011 00000001 00000011*
|
||||
L0005440 00000000 00000011 00000001 00001011*
|
||||
L0005472 000000 000000 000000 000100*
|
||||
L0005440 00000000 00000011 00000001 00000011*
|
||||
L0005472 000000 000000 000000 000110*
|
||||
L0005496 000000 000000 000000 000000*
|
||||
L0005520 000000 000000 000000 000000*
|
||||
L0005544 000000 000000 000000 000000*
|
||||
@ -264,8 +264,8 @@ L0005744 00000000 01000011 00000000 00000000*
|
||||
L0005776 00000000 00000011 00000000 00000001*
|
||||
L0005808 00000000 01000011 00000001 00000011*
|
||||
L0005840 00000000 01000011 00000000 00010001*
|
||||
L0005872 00000000 01000011 00000000 00000011*
|
||||
L0005904 000000 010000 000000 000011*
|
||||
L0005872 00000000 01000011 00000000 00001011*
|
||||
L0005904 000000 010000 000000 000001*
|
||||
L0005928 000000 000000 000000 000000*
|
||||
L0005952 000000 000000 000000 000000*
|
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L0005976 000000 000000 000000 000000*
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@ -338,8 +338,8 @@ L0007872 00000000 00000111 00000000 00000010*
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L0007904 00000000 00000001 00000000 00000000*
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L0007936 00000000 10000001 00000000 00000011*
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L0007968 00000000 10000001 00000001 00000011*
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L0008000 00000000 00000001 00000000 00000001*
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||||
L0008032 00000000 10001100 00000000 00000010*
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L0008000 00000000 10000001 00000000 00000001*
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L0008032 00000000 00001100 00000000 00000010*
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L0008064 000000 000000 000000 000000*
|
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L0008088 000000 000000 000000 000000*
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L0008112 000000 000000 000000 000000*
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@ -353,8 +353,8 @@ L0008304 00000000 00000001 00000000 00000001*
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L0008336 00000000 00000011 00000000 00000011*
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L0008368 00000000 00000011 00000100 00000001*
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L0008400 00000000 00000001 00000001 00000010*
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L0008432 00000000 10000001 00000000 00000001*
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L0008464 00000000 00000000 00000000 00000011*
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L0008432 00000000 00000001 00000000 00000001*
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||||
L0008464 00000000 10000000 00000000 00000011*
|
||||
L0008496 000000 000000 000000 000000*
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||||
L0008520 000000 000000 000001 000000*
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||||
L0008544 000000 000000 000000 000000*
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@ -754,7 +754,7 @@ L0019848 000000 000000 000000 000000*
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L0019872 00000000 00000010 00000001 10000011*
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L0019904 00000000 00000011 00000001 10000011*
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L0019936 00000000 00000011 00000001 10000011*
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L0019968 00000000 00000011 00000000 10000011*
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L0019968 00000000 00000011 00000000 10000111*
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L0020000 00000000 00000010 00000000 10000011*
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L0020032 00000000 00000011 00000000 00000011*
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L0020064 00000000 01000011 00000001 00000011*
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@ -765,7 +765,7 @@ L0020184 000000 000000 000000 000000*
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L0020208 000000 000000 000100 000001*
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L0020232 000000 000000 000000 000000*
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L0020256 000000 000000 000000 001000*
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L0020280 000000 000000 000000 000010*
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L0020280 000000 000000 000000 000000*
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L0020304 00000000 00000000 00000001 00000011*
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L0020336 00000000 00000011 00000001 00000011*
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L0020368 00000000 01000010 00000001 00000011*
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@ -848,8 +848,8 @@ L0022560 00000000 00000000 00000000 00000000*
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L0022592 00000000 00000000 00000001 00000000*
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L0022624 00000000 10000000 00000000 00000000*
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L0022656 00000000 10000000 00000000 00000000*
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L0022688 00000000 10000000 00000000 00000000*
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L0022720 00000000 00000000 00000000 00000000*
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L0022688 00000000 00000000 00000000 00000000*
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L0022720 00000000 10000000 00000000 00000000*
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L0022752 000000 000000 000000 000000*
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L0022776 000000 000000 000000 000000*
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L0022800 000000 000000 000000 000000*
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@ -863,8 +863,8 @@ L0022992 00000000 00000100 00000000 00000000*
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L0023024 00000000 00000000 00000000 00000000*
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L0023056 00000000 00000000 00000000 00000000*
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L0023088 00000000 00000000 00000000 00000000*
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L0023120 00000000 00000000 00000000 00000000*
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L0023152 00000000 10001100 00000000 00000000*
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L0023120 00000000 10000000 00000000 00000000*
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L0023152 00000000 00001100 00000000 00000000*
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L0023184 000000 000000 000000 000000*
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L0023208 000000 000000 000000 000000*
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L0023232 000000 000000 000000 000000*
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@ -1039,7 +1039,7 @@ L0028056 000000 000000 000000 000000*
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L0028080 00000000 00000000 00000000 00000010*
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L0028112 00000000 00000011 00000011 00000001*
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L0028144 00000000 00000000 00000000 00000000*
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L0028176 00000000 00000100 00000000 00000100*
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L0028176 00000000 00000100 00000000 00000000*
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L0028208 00000000 00000010 00000010 00000010*
|
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L0028240 00000000 00000000 00000000 01000000*
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L0028272 00000000 10000000 00000000 00000100*
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@ -1050,7 +1050,7 @@ L0028392 000000 000000 000000 000000*
|
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L0028416 000000 000000 000000 000110*
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L0028440 000000 000000 000000 000000*
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L0028464 000000 000010 000000 000110*
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L0028488 000000 000000 000000 000000*
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L0028488 000000 000000 000000 000010*
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L0028512 00000000 00000000 00000000 01011010*
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L0028544 00000000 00000010 00000110 01111001*
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L0028576 00000000 00000000 00000000 01111000*
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@ -1089,8 +1089,8 @@ L0029504 00000000 00000001 00000000 00000101*
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L0029536 00000000 00000000 00000000 00000000*
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L0029568 00000000 00000000 00000000 00010000*
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L0029600 00000000 00000000 00000000 00011000*
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L0029632 00000000 00000000 00000000 00011000*
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L0029664 000000 000000 000000 000000*
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L0029632 00000000 00000000 00000000 00010000*
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L0029664 000000 000000 000000 000010*
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L0029688 000000 000000 000000 000000*
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L0029712 000000 000000 000000 000000*
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L0029736 000000 000000 000000 000000*
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@ -1105,7 +1105,7 @@ L0029968 00000000 00000000 00000000 00000000*
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L0030000 00000000 00000000 00000000 00000000*
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L0030032 00000000 00000000 00000000 00000000*
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L0030064 00000000 00000000 00000000 00000000*
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L0030096 000000 000000 000000 000110*
|
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L0030096 000000 000000 000000 000100*
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L0030120 000000 000000 000000 000000*
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L0030144 000000 000000 000000 000000*
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L0030168 000000 000000 000000 000000*
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@ -1178,8 +1178,8 @@ L0032064 00000000 00000100 00000000 00000000*
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L0032096 00000000 00000000 00000000 00000100*
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L0032128 00000000 10000000 00000000 00000000*
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L0032160 00000000 10000000 00000000 00010000*
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L0032192 00000000 10000000 00000000 00011000*
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L0032224 00000000 00001100 00000000 00011000*
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L0032192 00000000 00000000 00000000 00011000*
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L0032224 00000000 10001100 00000000 00011000*
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L0032256 000000 000000 000000 000111*
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L0032280 000000 000000 000000 000000*
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L0032304 000000 000000 000000 000000*
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@ -1193,8 +1193,8 @@ L0032496 00000000 00000000 00000000 00000000*
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L0032528 00000000 00000001 00000000 00000000*
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L0032560 00000000 00000000 00000000 00000000*
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L0032592 00000000 00000000 00000000 00000000*
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L0032624 00000000 00000000 00000000 00000000*
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L0032656 00000000 10000000 00000000 00000000*
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L0032624 00000000 10000000 00000000 00000000*
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L0032656 00000000 00000000 00000000 00000000*
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L0032688 000000 000000 000000 000000*
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L0032712 000000 000000 000000 000000*
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L0032736 000000 000000 000000 000000*
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@ -1599,8 +1599,8 @@ L0044192 00000000 00000000 00000000 00000000*
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L0044224 00000000 00000000 00000000 00000000*
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L0044256 00000000 00000000 00000000 00000000*
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L0044288 00000000 00000000 00000000 00010000*
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L0044320 00000000 00000000 00000000 00000000*
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L0044352 000000 000000 000000 000111*
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L0044320 00000000 00000000 00000000 00001000*
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L0044352 000000 000000 000000 000101*
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L0044376 000000 000000 000000 000000*
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L0044400 000000 000000 000000 000000*
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L0044424 000000 000000 000000 000000*
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@ -1629,8 +1629,8 @@ L0045056 00000000 00000000 00000000 00000100*
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L0045088 00000000 00000000 00000000 00000000*
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L0045120 00000000 00000000 00000000 00010000*
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L0045152 00000000 00000000 00000000 00001000*
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L0045184 00000000 00000000 00000000 00011000*
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L0045216 000000 000000 000000 000101*
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L0045184 00000000 00000000 00000000 00010000*
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L0045216 000000 000000 000000 000111*
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L0045240 000000 000000 000000 000000*
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L0045264 000000 000000 000000 000000*
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L0045288 000000 000000 000000 000000*
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@ -1644,8 +1644,8 @@ L0045488 00000000 00000000 00000000 00000000*
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L0045520 00000000 00000000 00000000 00000000*
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L0045552 00000000 00000000 00000000 00000000*
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L0045584 00000000 00000000 00000000 00000000*
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L0045616 00000000 00000000 00000000 00000000*
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L0045648 000000 000000 000000 000010*
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L0045616 00000000 00000000 00000000 00001000*
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L0045648 000000 000000 000000 000000*
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L0045672 000000 000000 000000 000000*
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L0045696 000000 000000 000000 000000*
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L0045720 000000 000000 000000 000000*
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@ -1681,5 +1681,5 @@ L0046560 000000 000000 000000 000000*
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L0046584 000000 000000 000000 001111*
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L0046608 000000 000000 000100 000000*
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L0046632 000000 000000 000100 000000*
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CA518*
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05DC
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CA4D8*
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05ED
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692
RTL/RIPPLE.rpt
692
RTL/RIPPLE.rpt
@ -1,7 +1,7 @@
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cpldfit: version P.20131013 Xilinx Inc.
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Fitter Report
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Design Name: RIPPLE Date: 10-20-2023, 2:33PM
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Design Name: RIPPLE Date: 12-15-2023, 6:32PM
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Device Used: XC9572XL-10-VQ64
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Fitting Status: Successful
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@ -9,18 +9,18 @@ Fitting Status: Successful
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Macrocells Product Terms Function Block Registers Pins
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Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
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35 /72 ( 49%) 176 /360 ( 49%) 112/216 ( 52%) 22 /72 ( 31%) 47 /52 ( 90%)
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37 /72 ( 51%) 172 /360 ( 48%) 113/216 ( 52%) 23 /72 ( 32%) 46 /52 ( 88%)
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** Function Block Resources **
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 0/18 0/54 0/90 10/13
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FB2 16/18 42/54 69/90 13/13*
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FB3 5/18 27/54 20/90 13/14
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FB2 17/18 43/54 63/90 12/13
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FB3 6/18 27/54 22/90 13/14
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FB4 14/18 43/54 87/90 11/12
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----- ----- ----- -----
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35/72 112/216 176/360 47/52
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37/72 113/216 172/360 46/52
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* - Resource is exhausted
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@ -34,18 +34,18 @@ Global set/reset net(s) unused.
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Signal Type Required Mapped | Pin Type Used Total
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------------------------------------|------------------------------------
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Input : 30 30 | I/O : 42 46
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Input : 29 29 | I/O : 41 46
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Output : 14 14 | GCK/IO : 2 3
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Bidirectional : 3 3 | GTS/IO : 2 2
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GCK : 0 0 | GSR/IO : 1 1
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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Total 47 47
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Total 46 46
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** Power Data **
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There are 35 macrocells in high performance mode (MCHP).
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There are 37 macrocells in high performance mode (MCHP).
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There are 0 macrocells in low power mode (MCLP).
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End of Mapped Resource Summary
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************************** Errors and Warnings ***************************
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@ -73,6 +73,8 @@ WARNING:Cpld:1007 - Removing unused input(s) 'ADDR<11>'. The input(s) are
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unused after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'ADDR<9>'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1007 - Removing unused input(s) 'LDS_n'. The input(s) are unused
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after optimization. Please verify functionality via simulation.
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WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'ADDR_13_IBUF'
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is ignored. Most likely the signal is gated and therefore cannot be used as a
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global control signal.
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@ -86,7 +88,7 @@ WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'ADDR_12_IBUF'
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Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
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Name Pts Inps No. Type Use Mode Rate State
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DBUS<15> 8 29 FB2_3 58 I/O I/O STD SLOW RESET
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IDEBUF_OE 19 20 FB2_4 59 I/O O STD SLOW
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IDEBUF_OE 10 19 FB2_4 59 I/O O STD SLOW
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DTACK_n 0 0 FB2_10 1 I/O O STD SLOW
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OVR_n_1 0 0 FB3_6 34 I/O O STD SLOW
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IDE_ROMEN 15 17 FB3_11 33 I/O O STD SLOW
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@ -103,30 +105,32 @@ IDE1_CS_n<0> 8 18 FB4_14 50 I/O O STD SLOW
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DBUS<13> 7 29 FB4_15 56 I/O I/O STD SLOW RESET
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DBUS<14> 8 29 FB4_17 57 I/O I/O STD SLOW RESET
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** 18 Buried Nodes **
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** 20 Buried Nodes **
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Signal Total Total Loc Pwr Reg Init
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Name Pts Inps Mode State
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ide_enable 3 9 FB2_1 STD RESET
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RESET_CNTR<6> 3 9 FB2_2 STD RESET
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RESET_CNTR<5> 3 9 FB2_7 STD RESET
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RESET_CNTR<4> 3 8 FB2_8 STD RESET
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RESET_CNTR<3> 3 7 FB2_9 STD RESET
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RESET_CNTR<2> 3 6 FB2_11 STD RESET
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RESET_CNTR<1> 3 5 FB2_12 STD RESET
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RESET_CNTR<0> 3 4 FB2_13 STD RESET
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IDE/as_delay<0> 3 9 FB2_14 STD RESET
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AUTOCONFIG/shutup 3 31 FB2_15 STD RESET
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AUTOCONFIG/ide_base<2> 4 32 FB2_16 STD RESET
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AUTOCONFIG/ide_base<1> 4 32 FB2_17 STD RESET
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AUTOCONFIG/ide_base<0> 4 32 FB2_18 STD RESET
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ide_enable/ide_enable_CLKF 2 2 FB3_18 STD
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AUTOCONFIG/dtack 5 22 FB4_3 STD RESET
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IDE/ide_enabled 10 26 FB4_7 STD RESET
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IDE/as_delay<1> 3 10 FB4_16 STD RESET
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AUTOCONFIG/ide_configured 3 31 FB4_18 STD RESET
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RESET_CNTR<5> 3 9 FB2_5 STD RESET
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RESET_CNTR<4> 3 8 FB2_6 STD RESET
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RESET_CNTR<3> 3 7 FB2_7 STD RESET
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RESET_CNTR<2> 3 6 FB2_8 STD RESET
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RESET_CNTR<1> 3 5 FB2_9 STD RESET
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RESET_CNTR<0> 3 4 FB2_11 STD RESET
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IDE/as_delay<1> 3 10 FB2_12 STD RESET
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IDE/S3_n 3 9 FB2_13 STD RESET
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AUTOCONFIG/shutup 3 31 FB2_14 STD RESET
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AUTOCONFIG/ide_base<2> 4 32 FB2_15 STD RESET
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AUTOCONFIG/ide_base<1> 4 32 FB2_16 STD RESET
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AUTOCONFIG/ide_base<0> 4 32 FB2_17 STD RESET
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RESET_CNTR<6> 3 9 FB2_18 STD RESET
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ide_enable/ide_enable_CLKF 2 2 FB3_17 STD
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IDE/S3_n/IDE/S3_n_CLKF 2 2 FB3_18 STD
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AS_n_S4 3 10 FB4_7 STD RESET
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AUTOCONFIG/ide_configured 3 31 FB4_9 STD RESET
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AUTOCONFIG/dtack 5 22 FB4_16 STD RESET
|
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IDE/ide_enabled 10 24 FB4_18 STD RESET
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** 30 Inputs **
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** 29 Inputs **
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Signal Loc Pin Pin Pin
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Name No. Type Use
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@ -142,7 +146,6 @@ ADDR<2> FB1_12 23 I/O I
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ADDR<1> FB1_17 20 I/O I
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AS_n FB2_2 60 I/O I
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UDS_n FB2_5 61 I/O I
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LDS_n FB2_6 62 I/O I
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RW FB2_8 63 I/O I
|
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RESET_n FB2_9 64 GSR/I/O I
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ADDR<23> FB2_11 2 GTS/I/O I
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@ -200,69 +203,71 @@ Name Pt Pt Pt Pt # Type Use
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(unused) 0 0 0 5 FB1_17 20 I/O I
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||||
(unused) 0 0 0 5 FB1_18 (b)
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*********************************** FB2 ***********************************
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Number of function block inputs used/remaining: 42/12
|
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Number of signals used by logic mapping into function block: 42
|
||||
Number of function block inputs used/remaining: 43/11
|
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Number of signals used by logic mapping into function block: 43
|
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Signal Total Imp Exp Unused Loc Pin Pin Pin
|
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Name Pt Pt Pt Pt # Type Use
|
||||
ide_enable 3 0 \/1 1 FB2_1 (b) (b)
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RESET_CNTR<6> 3 1<- \/3 0 FB2_2 60 I/O I
|
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DBUS<15> 8 3<- 0 0 FB2_3 58 I/O I/O
|
||||
IDEBUF_OE 19 14<- 0 0 FB2_4 59 I/O O
|
||||
(unused) 0 0 /\5 0 FB2_5 61 I/O I
|
||||
(unused) 0 0 /\5 0 FB2_6 62 I/O I
|
||||
RESET_CNTR<5> 3 2<- /\4 0 FB2_7 (b) (b)
|
||||
RESET_CNTR<4> 3 0 /\2 0 FB2_8 63 I/O I
|
||||
RESET_CNTR<3> 3 0 0 2 FB2_9 64 GSR/I/O I
|
||||
ide_enable 3 0 0 2 FB2_1 (b) (b)
|
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(unused) 0 0 \/4 1 FB2_2 60 I/O I
|
||||
DBUS<15> 8 4<- \/1 0 FB2_3 58 I/O I/O
|
||||
IDEBUF_OE 10 5<- 0 0 FB2_4 59 I/O O
|
||||
RESET_CNTR<5> 3 2<- /\4 0 FB2_5 61 I/O I
|
||||
RESET_CNTR<4> 3 0 /\2 0 FB2_6 62 I/O (b)
|
||||
RESET_CNTR<3> 3 0 0 2 FB2_7 (b) (b)
|
||||
RESET_CNTR<2> 3 0 0 2 FB2_8 63 I/O I
|
||||
RESET_CNTR<1> 3 0 0 2 FB2_9 64 GSR/I/O I
|
||||
DTACK_n 0 0 0 5 FB2_10 1 I/O O
|
||||
RESET_CNTR<2> 3 0 0 2 FB2_11 2 GTS/I/O I
|
||||
RESET_CNTR<1> 3 0 0 2 FB2_12 4 I/O I
|
||||
RESET_CNTR<0> 3 0 0 2 FB2_13 (b) (b)
|
||||
IDE/as_delay<0> 3 0 0 2 FB2_14 5 GTS/I/O I
|
||||
AUTOCONFIG/shutup 3 0 0 2 FB2_15 6 I/O I
|
||||
RESET_CNTR<0> 3 0 0 2 FB2_11 2 GTS/I/O I
|
||||
IDE/as_delay<1> 3 0 0 2 FB2_12 4 I/O I
|
||||
IDE/S3_n 3 0 0 2 FB2_13 (b) (b)
|
||||
AUTOCONFIG/shutup 3 0 0 2 FB2_14 5 GTS/I/O I
|
||||
AUTOCONFIG/ide_base<2>
|
||||
4 0 0 1 FB2_16 (b) (b)
|
||||
4 0 0 1 FB2_15 6 I/O I
|
||||
AUTOCONFIG/ide_base<1>
|
||||
4 0 0 1 FB2_17 7 I/O I
|
||||
4 0 0 1 FB2_16 (b) (b)
|
||||
AUTOCONFIG/ide_base<0>
|
||||
4 0 0 1 FB2_18 (b) (b)
|
||||
4 0 0 1 FB2_17 7 I/O I
|
||||
RESET_CNTR<6> 3 0 0 2 FB2_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: ADDR<16> 15: ADDR<7> 29: DBUS<15>.PIN
|
||||
2: ADDR<17> 16: ADDR<8> 30: DBUS<14>.PIN
|
||||
3: ADDR<18> 17: AS_n 31: DBUS<13>.PIN
|
||||
4: ADDR<19> 18: AUTOCONFIG/dtack 32: RESET_CNTR<0>
|
||||
5: ADDR<1> 19: AUTOCONFIG/ide_base<0> 33: RESET_CNTR<1>
|
||||
6: ADDR<20> 20: AUTOCONFIG/ide_base<1> 34: RESET_CNTR<2>
|
||||
7: ADDR<21> 21: AUTOCONFIG/ide_base<2> 35: RESET_CNTR<3>
|
||||
8: ADDR<22> 22: AUTOCONFIG/ide_configured 36: RESET_CNTR<4>
|
||||
9: ADDR<23> 23: AUTOCONFIG/shutup 37: RESET_CNTR<5>
|
||||
10: ADDR<2> 24: BERR_n 38: RESET_CNTR<6>
|
||||
11: ADDR<3> 25: CFGIN_n 39: RESET_n
|
||||
12: ADDR<4> 26: CFGOUT_n 40: RW
|
||||
13: ADDR<5> 27: IDE_OFF_n 41: UDS_n
|
||||
14: ADDR<6> 28: LDS_n 42: ide_enable/ide_enable_CLKF
|
||||
1: ADDR<16> 16: ADDR<8> 30: DBUS<15>.PIN
|
||||
2: ADDR<17> 17: AS_n 31: DBUS<14>.PIN
|
||||
3: ADDR<18> 18: AS_n_S4 32: DBUS<13>.PIN
|
||||
4: ADDR<19> 19: AUTOCONFIG/dtack 33: RESET_CNTR<0>
|
||||
5: ADDR<1> 20: AUTOCONFIG/ide_base<0> 34: RESET_CNTR<1>
|
||||
6: ADDR<20> 21: AUTOCONFIG/ide_base<1> 35: RESET_CNTR<2>
|
||||
7: ADDR<21> 22: AUTOCONFIG/ide_base<2> 36: RESET_CNTR<3>
|
||||
8: ADDR<22> 23: AUTOCONFIG/ide_configured 37: RESET_CNTR<4>
|
||||
9: ADDR<23> 24: AUTOCONFIG/shutup 38: RESET_CNTR<5>
|
||||
10: ADDR<2> 25: BERR_n 39: RESET_CNTR<6>
|
||||
11: ADDR<3> 26: CFGIN_n 40: RESET_n
|
||||
12: ADDR<4> 27: CFGOUT_n 41: RW
|
||||
13: ADDR<5> 28: IDE/S3_n/IDE/S3_n_CLKF 42: UDS_n
|
||||
14: ADDR<6> 29: IDE_OFF_n 43: ide_enable/ide_enable_CLKF
|
||||
15: ADDR<7>
|
||||
|
||||
Signal 1 2 3 4 5 FB
|
||||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||||
ide_enable ..........................X....XXXXXXX...X........ 9
|
||||
RESET_CNTR<6> ...............................XXXXXXXX..X........ 9
|
||||
DBUS<15> XXXXXXXXXXXXXXXXX.......XX.....XXXXXXXXX.X........ 29
|
||||
IDEBUF_OE XXXX.XXXX.......X.XXXX.XXX.X..........XXX......... 20
|
||||
RESET_CNTR<5> ...............................XXXXXXXX..X........ 9
|
||||
RESET_CNTR<4> ...............................XXXXX.XX..X........ 8
|
||||
RESET_CNTR<3> ...............................XXXX..XX..X........ 7
|
||||
ide_enable ............................X...XXXXXXX...X....... 9
|
||||
DBUS<15> XXXXXXXXXXXXXXXXX........XX.....XXXXXXXXX.X....... 29
|
||||
IDEBUF_OE XXXX.XXXX.......XX.XXXX.XXX............XX......... 19
|
||||
RESET_CNTR<5> ................................XXXXXXXX..X....... 9
|
||||
RESET_CNTR<4> ................................XXXXX.XX..X....... 8
|
||||
RESET_CNTR<3> ................................XXXX..XX..X....... 7
|
||||
RESET_CNTR<2> ................................XXX...XX..X....... 6
|
||||
RESET_CNTR<1> ................................XX....XX..X....... 5
|
||||
DTACK_n .................................................. 0
|
||||
RESET_CNTR<2> ...............................XXX...XX..X........ 6
|
||||
RESET_CNTR<1> ...............................XX....XX..X........ 5
|
||||
RESET_CNTR<0> ...............................X.....XX..X........ 4
|
||||
IDE/as_delay<0> ................X..............XXXXXXX...X........ 9
|
||||
AUTOCONFIG/shutup XXXXXXXXXXXXXXXXXX....X.XX.....XXXXXXX.XXX........ 31
|
||||
RESET_CNTR<0> ................................X.....XX..X....... 4
|
||||
IDE/as_delay<1> ................XX..............XXXXXXX...X....... 10
|
||||
IDE/S3_n ................X..........X....XXXXXXX........... 9
|
||||
AUTOCONFIG/shutup XXXXXXXXXXXXXXXXX.X....X.XX.....XXXXXXX.XXX....... 31
|
||||
AUTOCONFIG/ide_base<2>
|
||||
XXXXXXXXXXXXXXXXXX...X..XX..X..XXXXXXX.XXX........ 32
|
||||
XXXXXXXXXXXXXXXXX.X...X..XX..X..XXXXXXX.XXX....... 32
|
||||
AUTOCONFIG/ide_base<1>
|
||||
XXXXXXXXXXXXXXXXXX...X..XX...X.XXXXXXX.XXX........ 32
|
||||
XXXXXXXXXXXXXXXXX.X...X..XX...X.XXXXXXX.XXX....... 32
|
||||
AUTOCONFIG/ide_base<0>
|
||||
XXXXXXXXXXXXXXXXXX...X..XX....XXXXXXXX.XXX........ 32
|
||||
XXXXXXXXXXXXXXXXX.X...X..XX....XXXXXXXX.XXX....... 32
|
||||
RESET_CNTR<6> ................................XXXXXXXX..X....... 9
|
||||
0----+----1----+----2----+----3----+----4----+----5
|
||||
0 0 0 0 0
|
||||
*********************************** FB3 ***********************************
|
||||
@ -286,8 +291,9 @@ IDE_ROMEN 15 10<- 0 0 FB3_11 33 I/O O
|
||||
OVR_n_2 0 0 0 5 FB3_14 35 I/O O
|
||||
(unused) 0 0 0 5 FB3_15 36 I/O
|
||||
CFGOUT_n 3 0 0 2 FB3_16 42 I/O O
|
||||
(unused) 0 0 0 5 FB3_17 38 I/O I
|
||||
ide_enable/ide_enable_CLKF
|
||||
2 0 0 3 FB3_17 38 I/O I
|
||||
IDE/S3_n/IDE/S3_n_CLKF
|
||||
2 0 0 3 FB3_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
@ -309,6 +315,8 @@ OVR_n_2 ........................................ 0
|
||||
CFGOUT_n ..........X...XX....XXXXXXX............. 10
|
||||
ide_enable/ide_enable_CLKF
|
||||
................XX...................... 2
|
||||
IDE/S3_n/IDE/S3_n_CLKF
|
||||
................XX...................... 2
|
||||
0----+----1----+----2----+----3----+----4
|
||||
0 0 0 0
|
||||
*********************************** FB4 ***********************************
|
||||
@ -316,25 +324,25 @@ Number of function block inputs used/remaining: 43/11
|
||||
Number of signals used by logic mapping into function block: 43
|
||||
Signal Total Imp Exp Unused Loc Pin Pin Pin
|
||||
Name Pt Pt Pt Pt # Type Use
|
||||
(unused) 0 0 \/5 0 FB4_1 (b) (b)
|
||||
SLAVE_n 9 7<- \/3 0 FB4_2 43 I/O O
|
||||
AUTOCONFIG/dtack 5 3<- \/3 0 FB4_3 46 I/O (b)
|
||||
IDE2_CS_n<1> 8 3<- 0 0 FB4_4 47 I/O O
|
||||
IOR_n 1 0 \/4 0 FB4_5 44 I/O O
|
||||
IDE1_CS_n<1> 8 4<- \/1 0 FB4_6 49 I/O O
|
||||
IDE/ide_enabled 10 5<- 0 0 FB4_7 (b) (b)
|
||||
IOW_n 1 0 /\4 0 FB4_8 45 I/O O
|
||||
(unused) 0 0 \/2 3 FB4_9 (b) (b)
|
||||
(unused) 0 0 /\5 0 FB4_1 (b) (b)
|
||||
SLAVE_n 9 6<- /\2 0 FB4_2 43 I/O O
|
||||
(unused) 0 0 /\5 0 FB4_3 46 I/O (b)
|
||||
IDE2_CS_n<1> 8 4<- /\1 0 FB4_4 47 I/O O
|
||||
IOR_n 1 0 /\4 0 FB4_5 44 I/O O
|
||||
IDE1_CS_n<1> 8 3<- 0 0 FB4_6 49 I/O O
|
||||
AS_n_S4 3 1<- /\3 0 FB4_7 (b) (b)
|
||||
IOW_n 1 0 /\1 3 FB4_8 45 I/O O
|
||||
AUTOCONFIG/ide_configured
|
||||
3 0 \/2 0 FB4_9 (b) (b)
|
||||
(unused) 0 0 \/5 0 FB4_10 51 I/O I
|
||||
IDE2_CS_n<0> 8 7<- \/4 0 FB4_11 48 I/O O
|
||||
DBUS<12> 8 4<- \/1 0 FB4_12 52 I/O O
|
||||
(unused) 0 0 \/5 0 FB4_13 (b) (b)
|
||||
IDE1_CS_n<0> 8 6<- \/3 0 FB4_14 50 I/O O
|
||||
DBUS<13> 7 3<- \/1 0 FB4_15 56 I/O I/O
|
||||
IDE/as_delay<1> 3 1<- \/3 0 FB4_16 (b) (b)
|
||||
AUTOCONFIG/dtack 5 1<- \/1 0 FB4_16 (b) (b)
|
||||
DBUS<14> 8 3<- 0 0 FB4_17 57 I/O I/O
|
||||
AUTOCONFIG/ide_configured
|
||||
3 0 \/2 0 FB4_18 (b) (b)
|
||||
IDE/ide_enabled 10 7<- /\2 0 FB4_18 (b) (b)
|
||||
|
||||
Signals Used by Logic in Function Block
|
||||
1: ADDR<12> 16: ADDR<4> 30: IDE/as_delay<1>
|
||||
@ -350,37 +358,43 @@ Signals Used by Logic in Function Block
|
||||
11: ADDR<21> 26: AUTOCONFIG/ide_configured 40: RW
|
||||
12: ADDR<22> 27: CFGIN_n 41: UDS_n
|
||||
13: ADDR<23> 28: CFGOUT_n 42: ide_enable
|
||||
14: ADDR<2> 29: IDE/as_delay<0> 43: ide_enable/ide_enable_CLKF
|
||||
14: ADDR<2> 29: IDE/S3_n 43: ide_enable/ide_enable_CLKF
|
||||
15: ADDR<3>
|
||||
|
||||
Signal 1 2 3 4 5 FB
|
||||
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
|
||||
SLAVE_n ....XXXX.XXXX.......X.XXXXXX...................... 15
|
||||
AUTOCONFIG/dtack ....XXXX.XXXX.......XX....XX...XXXXXXX.XX.X....... 22
|
||||
IDE2_CS_n<1> XXXXXXXX.XXXX.........XXXX.X..X................... 18
|
||||
IOR_n ....................X.......X..........X.......... 3
|
||||
IDE1_CS_n<1> XXXXXXXX.XXXX.........XXXX.X..X................... 18
|
||||
IDE/ide_enabled ...XXXXX.XXXX.........XXXX.XX.XXXXXXXX.XX.X....... 26
|
||||
AS_n_S4 ....................X.......X..XXXXXXX....X....... 10
|
||||
IOW_n ....................X.......XX.........X.......... 4
|
||||
AUTOCONFIG/ide_configured
|
||||
....XXXXXXXXXXXXXXXXXX...XXX...XXXXXXX.XX.X....... 31
|
||||
IDE2_CS_n<0> XXXXXXXX.XXXX.........XXXX.X..X................... 18
|
||||
DBUS<12> ....XXXXXXXXXXXXXXXXX.....XX...XXXXXXXXX.XX....... 30
|
||||
IDE1_CS_n<0> XXXXXXXX.XXXX.........XXXX.X..X................... 18
|
||||
DBUS<13> ....XXXXXXXXXXXXXXXXX.....XX...XXXXXXXXX..X....... 29
|
||||
IDE/as_delay<1> ....................X.......X..XXXXXXX....X....... 10
|
||||
AUTOCONFIG/dtack ....XXXX.XXXX.......XX....XX...XXXXXXX.XX.X....... 22
|
||||
DBUS<14> ....XXXXXXXXXXXXXXXXX.....XX...XXXXXXXXX..X....... 29
|
||||
AUTOCONFIG/ide_configured
|
||||
....XXXXXXXXXXXXXXXXXX...XXX...XXXXXXX.XX.X....... 31
|
||||
IDE/ide_enabled .....XXX.XXXX.........XXXX.XX.XXXXXXXX.XX.X....... 24
|
||||
0----+----1----+----2----+----3----+----4----+----5
|
||||
0 0 0 0 0
|
||||
******************************* Equations ********************************
|
||||
|
||||
********** Mapped Logic **********
|
||||
|
||||
AUTOCONFIG/dtack.D = ;Imported pterms FB4_2
|
||||
AUTOCONFIG/dtack & !AS_n
|
||||
!AS_n_S4.D = ;Imported pterms FB4_8
|
||||
!AS_n & !IDE/S3_n;
|
||||
AS_n_S4.CLK = ide_enable/ide_enable_CLKF;
|
||||
AS_n_S4.AP = !RESET_CNTR<0> & !RESET_CNTR<1> & !RESET_CNTR<2> &
|
||||
!RESET_CNTR<3> & !RESET_CNTR<4> & !RESET_CNTR<5> & RESET_CNTR<6>;
|
||||
|
||||
AUTOCONFIG/dtack.D = AUTOCONFIG/dtack & !AS_n
|
||||
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!ADDR<16> & !UDS_n & ADDR<23> & ADDR<22> & ADDR<21> &
|
||||
ADDR<19> & !AS_n & CFGOUT_n
|
||||
;Imported pterms FB4_15
|
||||
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
|
||||
!AS_n & CFGOUT_n;
|
||||
@ -467,8 +481,8 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
|
||||
!ADDR<2> & !ADDR<1> & !ADDR<3>
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
!ADDR<2> & ADDR<6> & !ADDR<3>
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<4> &
|
||||
ADDR<2> & ADDR<1> & !ADDR<6> & !ADDR<3>;
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<2> &
|
||||
ADDR<1> & !ADDR<6> & !ADDR<3>;
|
||||
DBUS<13>.CLK = ide_enable/ide_enable_CLKF;
|
||||
DBUS<13>.AR = !RESET_CNTR<0> & !RESET_CNTR<1> & !RESET_CNTR<2> &
|
||||
!RESET_CNTR<3> & !RESET_CNTR<4> & !RESET_CNTR<5> & RESET_CNTR<6>;
|
||||
@ -484,6 +498,7 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
|
||||
;Imported pterms FB4_16
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
!ADDR<2> & ADDR<6> & !ADDR<3>
|
||||
;Imported pterms FB4_18
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
ADDR<1> & !ADDR<6> & !ADDR<3>
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<4> &
|
||||
@ -498,11 +513,11 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
|
||||
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
|
||||
!AS_n & CFGOUT_n;
|
||||
|
||||
!DBUS<15>.D = !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
!ADDR<2> & ADDR<6> & !ADDR<3>
|
||||
;Imported pterms FB2_2
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
!DBUS<15>.D = ;Imported pterms FB2_2
|
||||
!ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
!ADDR<2> & ADDR<1> & !ADDR<3>
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
|
||||
!ADDR<2> & ADDR<6> & !ADDR<3>
|
||||
# !ADDR<8> & !ADDR<7> & ADDR<5> & !ADDR<4> &
|
||||
ADDR<2> & ADDR<1> & !ADDR<6> & ADDR<3>
|
||||
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<4> &
|
||||
@ -520,307 +535,265 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
|
||||
DTACK_n = Gnd;
|
||||
DTACK_n.OE = Gnd;
|
||||
|
||||
IDE/as_delay<0>.D = AS_n;
|
||||
IDE/as_delay<0>.CLK = ide_enable/ide_enable_CLKF;
|
||||
IDE/as_delay<0>.AP = !RESET_CNTR<0> & !RESET_CNTR<1> & !RESET_CNTR<2> &
|
||||
IDE/S3_n.D = AS_n;
|
||||
IDE/S3_n.CLK = IDE/S3_n/IDE/S3_n_CLKF;
|
||||
IDE/S3_n.AP = !RESET_CNTR<0> & !RESET_CNTR<1> & !RESET_CNTR<2> &
|
||||
!RESET_CNTR<3> & !RESET_CNTR<4> & !RESET_CNTR<5> & RESET_CNTR<6>;
|
||||
|
||||
!IDE/as_delay<1>.D = ;Imported pterms FB4_15
|
||||
!AS_n & !IDE/as_delay<0>;
|
||||
IDE/S3_n/IDE/S3_n_CLKF = C1n
|
||||
$ C3n;
|
||||
|
||||
!IDE/as_delay<1>.D = !AS_n & !AS_n_S4;
|
||||
IDE/as_delay<1>.CLK = ide_enable/ide_enable_CLKF;
|
||||
IDE/as_delay<1>.AP = !RESET_CNTR<0> & !RESET_CNTR<1> & !RESET_CNTR<2> &
|
||||
!RESET_CNTR<3> & !RESET_CNTR<4> & !RESET_CNTR<5> & RESET_CNTR<6>;
|
||||
|
||||
IDE/ide_enabled.T = !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
;Imported pterms FB4_6
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
;Imported pterms FB4_8
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!UDS_n & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/as_delay<0> & !IDE/ide_enabled & !ADDR<15> &
|
||||
!CFGOUT_n;
|
||||
IDE/ide_enabled.T = !ADDR<20> & ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
;Imported pterms FB4_1
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
;Imported pterms FB4_2
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !RW &
|
||||
AUTOCONFIG/ide_configured & !IDE/S3_n & !IDE/ide_enabled & !CFGOUT_n;
|
||||
IDE/ide_enabled.CLK = ide_enable/ide_enable_CLKF;
|
||||
IDE/ide_enabled.AR = !RESET_CNTR<0> & !RESET_CNTR<1> & !RESET_CNTR<2> &
|
||||
!RESET_CNTR<3> & !RESET_CNTR<4> & !RESET_CNTR<5> & RESET_CNTR<6>;
|
||||
|
||||
!IDE1_CS_n<0> = !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_13
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_12
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n;
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n;
|
||||
|
||||
!IDE1_CS_n<1> = !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_5
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & ADDR<12> &
|
||||
!ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n;
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_7
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & !ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n;
|
||||
|
||||
!IDE2_CS_n<0> = !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_10
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_9
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & !ADDR<14> & !CFGOUT_n;
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
!ADDR<14> & !CFGOUT_n;
|
||||
|
||||
!IDE2_CS_n<1> = !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_5
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
!ADDR<12> & AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
;Imported pterms FB4_3
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !ADDR<16> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !ADDR<16> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !ADDR<12> &
|
||||
ADDR<13> & AUTOCONFIG/ide_configured & IDE/ide_enabled &
|
||||
!ADDR<15> & ADDR<14> & !CFGOUT_n;
|
||||
!ADDR<12> & !AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> &
|
||||
!AUTOCONFIG/ide_base<2> & ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> &
|
||||
AUTOCONFIG/ide_configured & IDE/ide_enabled & !ADDR<15> & ADDR<13> &
|
||||
ADDR<14> & !CFGOUT_n;
|
||||
|
||||
!IDEBUF_OE = !RW
|
||||
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!ADDR<16> & !UDS_n & ADDR<23> & ADDR<22> & ADDR<21> &
|
||||
ADDR<19> & !AS_n & RESET_n & BERR_n & CFGOUT_n
|
||||
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
|
||||
!AS_n & RESET_n & BERR_n & !LDS_n & CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !UDS_n &
|
||||
!AS_n & RESET_n & !AS_n_S4 & BERR_n & CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
;Imported pterms FB2_3
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
;Imported pterms FB2_5
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> & !UDS_n &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
;Imported pterms FB2_6
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> & !UDS_n &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
;Imported pterms FB2_7
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & RESET_n & BERR_n & !LDS_n & !CFGOUT_n;
|
||||
AUTOCONFIG/ide_configured & RESET_n & !AS_n_S4 & BERR_n & !CFGOUT_n;
|
||||
|
||||
IDE_ROMEN = ADDR<20>
|
||||
# !ADDR<23>
|
||||
@ -837,14 +810,14 @@ IDE_ROMEN = ADDR<20>
|
||||
# !ADDR<18> & AUTOCONFIG/ide_base<1>
|
||||
# AUTOCONFIG/ide_base<2> & !ADDR<19>
|
||||
# !AUTOCONFIG/ide_base<2> & ADDR<19>
|
||||
# !ADDR<16> & ADDR<12> & !ADDR<13> &
|
||||
IDE/ide_enabled
|
||||
# !ADDR<16> & !ADDR<12> & ADDR<13> &
|
||||
IDE/ide_enabled;
|
||||
# !ADDR<16> & ADDR<12> & IDE/ide_enabled &
|
||||
!ADDR<13>
|
||||
# !ADDR<16> & !ADDR<12> & IDE/ide_enabled &
|
||||
ADDR<13>;
|
||||
|
||||
!IOR_n = RW & !AS_n & !IDE/as_delay<0>;
|
||||
!IOR_n = RW & !AS_n & !IDE/S3_n;
|
||||
|
||||
!IOW_n = !RW & !AS_n & !IDE/as_delay<0> & IDE/as_delay<1>;
|
||||
!IOW_n = !RW & !AS_n & !IDE/S3_n & IDE/as_delay<1>;
|
||||
|
||||
OVR_n_1 = Gnd;
|
||||
OVR_n_1.OE = Gnd;
|
||||
@ -875,14 +848,13 @@ RESET_CNTR<4>.T = RESET_n & RESET_CNTR<4>
|
||||
RESET_CNTR<2> & RESET_CNTR<3> & !RESET_CNTR<6>;
|
||||
RESET_CNTR<4>.CLK = ide_enable/ide_enable_CLKF;
|
||||
|
||||
RESET_CNTR<5>.T = ;Imported pterms FB2_8
|
||||
RESET_CNTR<5>.T = ;Imported pterms FB2_6
|
||||
RESET_n & RESET_CNTR<5>
|
||||
# RESET_CNTR<0> & !RESET_n & RESET_CNTR<1> &
|
||||
RESET_CNTR<2> & RESET_CNTR<3> & RESET_CNTR<4> & !RESET_CNTR<6>;
|
||||
RESET_CNTR<5>.CLK = ide_enable/ide_enable_CLKF;
|
||||
|
||||
RESET_CNTR<6>.D = !RESET_n & RESET_CNTR<6>
|
||||
;Imported pterms FB2_1
|
||||
# RESET_CNTR<0> & !RESET_n & RESET_CNTR<1> &
|
||||
RESET_CNTR<2> & RESET_CNTR<3> & RESET_CNTR<4> & RESET_CNTR<5>;
|
||||
RESET_CNTR<6>.CLK = ide_enable/ide_enable_CLKF;
|
||||
@ -894,15 +866,15 @@ RESET_CNTR<6>.D = !RESET_n & RESET_CNTR<6>
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
;Imported pterms FB4_1
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
;Imported pterms FB4_3
|
||||
# !ADDR<20> & ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
# !ADDR<20> & ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
@ -911,15 +883,15 @@ RESET_CNTR<6>.D = !RESET_n & RESET_CNTR<6>
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
;Imported pterms FB4_18
|
||||
# !ADDR<20> & !ADDR<18> & ADDR<17> &
|
||||
AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & !AS_n &
|
||||
AUTOCONFIG/ide_configured & !CFGOUT_n
|
||||
;Imported pterms FB4_4
|
||||
# !ADDR<20> & !ADDR<18> & !ADDR<17> &
|
||||
!AUTOCONFIG/ide_base<0> & !AUTOCONFIG/ide_base<1> & !AUTOCONFIG/ide_base<2> &
|
||||
ADDR<23> & ADDR<22> & ADDR<21> & !ADDR<19> & !AS_n &
|
||||
@ -991,7 +963,7 @@ No. Name No. Name
|
||||
27 ADDR<6> 59 IDEBUF_OE
|
||||
28 TDI 60 AS_n
|
||||
29 TMS 61 UDS_n
|
||||
30 TCK 62 LDS_n
|
||||
30 TCK 62 KPR
|
||||
31 ADDR<4> 63 RW
|
||||
32 ADDR<5> 64 RESET_n
|
||||
|
||||
|
||||
411
RTL/RIPPLE.tim
411
RTL/RIPPLE.tim
@ -5,17 +5,17 @@ Design: RIPPLE
|
||||
Device: XC9572XL-10-VQ64
|
||||
Speed File: Version 3.0
|
||||
Program: Timing Report Generator: version P.20131013
|
||||
Date: Thu Oct 19 23:47:50 2023
|
||||
Date: Fri Dec 15 18:32:43 2023
|
||||
|
||||
Performance Summary:
|
||||
|
||||
Pad to Pad (tPD) : 16.3ns (1 macrocell levels)
|
||||
Pad 'AS_n' to Pad 'IDEBUF_OE'
|
||||
Pad to Pad (tPD) : 15.9ns (1 macrocell levels)
|
||||
Pad 'ADDR<16>' to Pad 'IDE1_CS_n<0>'
|
||||
|
||||
Clock net 'AS_n' path delays:
|
||||
|
||||
Clock Pad to Output Pad (tCO) : 24.2ns (2 macrocell levels)
|
||||
Clock Pad 'AS_n' to Output Pad 'IDEBUF_OE' (Pterm Clock)
|
||||
Clock Pad to Output Pad (tCO) : 23.8ns (2 macrocell levels)
|
||||
Clock Pad 'AS_n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
|
||||
|
||||
Minimum Clock Period: 14.0ns
|
||||
Maximum Internal Clock Speed: 71.4Mhz
|
||||
@ -23,15 +23,15 @@ Clock Pad 'AS_n' to Output Pad 'IDEBUF_OE' (Pterm Clock)
|
||||
|
||||
Clock net 'C3n' path delays:
|
||||
|
||||
Clock Pad to Output Pad (tCO) : 31.9ns (3 macrocell levels)
|
||||
Clock Pad 'C3n' to Output Pad 'IDEBUF_OE' (Pterm Clock)
|
||||
Clock Pad to Output Pad (tCO) : 31.5ns (3 macrocell levels)
|
||||
Clock Pad 'C3n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
|
||||
|
||||
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
|
||||
Clock to Q, net 'ide_enable.Q' to DFF Setup(D) at 'DBUS<12>.D' (Pterm Clock)
|
||||
Target FF drives output net 'DBUS<12>'
|
||||
Clock to Setup (tCYC) : 11.4ns (1 macrocell levels)
|
||||
Clock to Q, net 'AUTOCONFIG/ide_base<0>.Q' to TFF Setup(D) at 'IDE/ide_enabled.D'(Pterm Clock)
|
||||
Target FF drives output net 'IDE/ide_enabled'
|
||||
|
||||
Setup to Clock at the Pad (tSU) : -4.6ns (0 macrocell levels)
|
||||
Data signal 'ADDR<4>' to DFF D input Pin at 'DBUS<13>.D'
|
||||
Setup to Clock at the Pad (tSU) : -4.2ns (0 macrocell levels)
|
||||
Data signal 'RW' to TFF D input Pin at 'IDE/ide_enabled.D'
|
||||
Clock pad 'C3n' (Pterm Clock)
|
||||
|
||||
Minimum Clock Period: 14.0ns
|
||||
@ -40,15 +40,15 @@ Clock pad 'C3n' (Pterm Clock)
|
||||
|
||||
Clock net 'C1n' path delays:
|
||||
|
||||
Clock Pad to Output Pad (tCO) : 31.9ns (3 macrocell levels)
|
||||
Clock Pad 'C1n' to Output Pad 'IDEBUF_OE' (Pterm Clock)
|
||||
Clock Pad to Output Pad (tCO) : 31.5ns (3 macrocell levels)
|
||||
Clock Pad 'C1n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
|
||||
|
||||
Clock to Setup (tCYC) : 11.0ns (1 macrocell levels)
|
||||
Clock to Q, net 'ide_enable.Q' to DFF Setup(D) at 'DBUS<12>.D' (Pterm Clock)
|
||||
Target FF drives output net 'DBUS<12>'
|
||||
Clock to Setup (tCYC) : 11.4ns (1 macrocell levels)
|
||||
Clock to Q, net 'AUTOCONFIG/ide_base<0>.Q' to TFF Setup(D) at 'IDE/ide_enabled.D'(Pterm Clock)
|
||||
Target FF drives output net 'IDE/ide_enabled'
|
||||
|
||||
Setup to Clock at the Pad (tSU) : -4.6ns (0 macrocell levels)
|
||||
Data signal 'ADDR<4>' to DFF D input Pin at 'DBUS<13>.D'
|
||||
Setup to Clock at the Pad (tSU) : -4.2ns (0 macrocell levels)
|
||||
Data signal 'RW' to TFF D input Pin at 'IDE/ide_enabled.D'
|
||||
Clock pad 'C1n' (Pterm Clock)
|
||||
|
||||
Minimum Clock Period: 14.0ns
|
||||
@ -80,7 +80,7 @@ IDE1_CS_n<0> 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9
|
||||
IDE1_CS_n<1> 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5
|
||||
IDE2_CS_n<0> 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9 15.9
|
||||
IDE2_CS_n<1> 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5
|
||||
IDEBUF_OE 14.5 16.3 16.3 16.3 16.3 16.3 16.3
|
||||
IDEBUF_OE 14.5 15.5 15.5 15.5 15.5 15.5 15.5
|
||||
IDE_ROMEN 15.5 15.5 15.5 15.5 15.5 15.5 14.5 15.5 14.5
|
||||
IOR_n
|
||||
IOW_n
|
||||
@ -89,11 +89,11 @@ SLAVE_n 14.5 15.9 15.9 15.9 15.9 15.9 15.9
|
||||
--------------------------------------------------------------------------------
|
||||
Pad to Pad (tPD) (nsec)
|
||||
|
||||
\ From A A B C L R R U
|
||||
\ D S E F D E W D
|
||||
\ D _ R G S S S
|
||||
\ R n R I _ E _
|
||||
\ < _ N n T n
|
||||
\ From A A B C R R
|
||||
\ D S E F E W
|
||||
\ D _ R G S
|
||||
\ R n R I E
|
||||
\ < _ N T
|
||||
\ 2 n _ _
|
||||
\ 3 n n
|
||||
\ >
|
||||
@ -101,7 +101,7 @@ SLAVE_n 14.5 15.9 15.9 15.9 15.9 15.9 15.9
|
||||
\
|
||||
\
|
||||
\
|
||||
To \------------------------------------------------
|
||||
To \------------------------------------
|
||||
|
||||
DBUS<12> 11.0 11.0 11.0 11.0
|
||||
DBUS<13> 11.0 11.0 11.0 11.0
|
||||
@ -111,7 +111,7 @@ IDE1_CS_n<0> 15.9
|
||||
IDE1_CS_n<1> 15.5
|
||||
IDE2_CS_n<0> 15.9
|
||||
IDE2_CS_n<1> 15.5
|
||||
IDEBUF_OE 16.3 16.3 16.3 14.5 16.3 16.3 14.5 15.9
|
||||
IDEBUF_OE 15.5 15.5 15.5 14.5 15.5 14.5
|
||||
IDE_ROMEN 14.5 15.5
|
||||
IOR_n 14.5 14.5
|
||||
IOW_n 14.5 14.5
|
||||
@ -143,7 +143,7 @@ IDE1_CS_n<0> 23.8 31.5 31.5
|
||||
IDE1_CS_n<1> 23.4 31.1 31.1
|
||||
IDE2_CS_n<0> 23.8 31.5 31.5
|
||||
IDE2_CS_n<1> 23.4 31.1 31.1
|
||||
IDEBUF_OE 24.2 31.9 31.9
|
||||
IDEBUF_OE 23.4 31.1 31.1
|
||||
IDE_ROMEN 22.4 31.1 31.1
|
||||
IOR_n 30.1 30.1
|
||||
IOW_n 30.1 30.1
|
||||
@ -163,16 +163,15 @@ SLAVE_n 23.8 31.5 31.5
|
||||
\
|
||||
To \------------
|
||||
|
||||
ADDR<15> -4.6 -4.6
|
||||
ADDR<16> -4.6 -4.6
|
||||
ADDR<17> -4.6 -4.6
|
||||
ADDR<18> -4.6 -4.6
|
||||
ADDR<19> -4.6 -4.6
|
||||
ADDR<17> -4.2 -4.2
|
||||
ADDR<18> -4.2 -4.2
|
||||
ADDR<19> -4.2 -4.2
|
||||
ADDR<1> -4.6 -4.6
|
||||
ADDR<20> -4.6 -4.6
|
||||
ADDR<21> -4.6 -4.6
|
||||
ADDR<22> -4.6 -4.6
|
||||
ADDR<23> -4.6 -4.6
|
||||
ADDR<20> -4.2 -4.2
|
||||
ADDR<21> -4.2 -4.2
|
||||
ADDR<22> -4.2 -4.2
|
||||
ADDR<23> -4.2 -4.2
|
||||
ADDR<2> -4.6 -4.6
|
||||
ADDR<3> -4.6 -4.6
|
||||
ADDR<4> -4.6 -4.6
|
||||
@ -187,30 +186,30 @@ DBUS<14> -5.6 -5.6
|
||||
DBUS<15> -5.6 -5.6
|
||||
IDE_OFF_n -5.6 -5.6
|
||||
RESET_n -4.6 -4.6
|
||||
RW -4.6 -4.6
|
||||
UDS_n -4.6 -4.6
|
||||
RW -4.2 -4.2
|
||||
UDS_n -4.2 -4.2
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C3n)
|
||||
|
||||
\ From A A A A A A I I
|
||||
\ U U U U U U D D
|
||||
\ T T T T T T E E
|
||||
\ O O O O O O / /
|
||||
\ C C C C C C a i
|
||||
\ O O O O O O s d
|
||||
\ N N N N N N _ e
|
||||
\ F F F F F F d _
|
||||
\ I I I I I I e e
|
||||
\ G G G G G G l n
|
||||
\ / / / / / / a a
|
||||
\ d i i i i s y b
|
||||
\ t d d d d h < l
|
||||
\ a e e e e u 0 e
|
||||
\ c _ _ _ _ t > d
|
||||
\ k b b b c u . .
|
||||
\ . a a a o p Q Q
|
||||
\ From A A A A A A A I
|
||||
\ S U U U U U U D
|
||||
\ _ T T T T T T E
|
||||
\ n O O O O O O /
|
||||
\ _ C C C C C C S
|
||||
\ S O O O O O O 3
|
||||
\ 4 N N N N N N _
|
||||
\ . F F F F F F n
|
||||
\ Q I I I I I I .
|
||||
\ G G G G G G Q
|
||||
\ / / / / / /
|
||||
\ d i i i i s
|
||||
\ t d d d d h
|
||||
\ a e e e e u
|
||||
\ c _ _ _ _ t
|
||||
\ k b b b c u
|
||||
\ . a a a o p
|
||||
\ Q s s s n .
|
||||
\ e e e f Q
|
||||
\ < < < i
|
||||
@ -224,15 +223,16 @@ UDS_n -4.6 -4.6
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AUTOCONFIG/dtack.D 11.0
|
||||
AS_n_S4.D 11.0
|
||||
AUTOCONFIG/dtack.D 10.0
|
||||
AUTOCONFIG/ide_base<0>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_base<1>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_base<2>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_configured.CE 10.0 10.0
|
||||
AUTOCONFIG/shutup.CE 10.0 10.0
|
||||
DBUS<12>.D
|
||||
IDE/as_delay<1>.D 11.0
|
||||
IDE/ide_enabled.D 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
IDE/as_delay<1>.D 10.0
|
||||
IDE/ide_enabled.D 11.4 11.4 11.4 11.4 11.4
|
||||
RESET_CNTR<0>.D
|
||||
RESET_CNTR<1>.D
|
||||
RESET_CNTR<2>.D
|
||||
@ -246,23 +246,23 @@ ide_enable.CE
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C3n)
|
||||
|
||||
\ From R R R R R R R i
|
||||
\ E E E E E E E d
|
||||
\ S S S S S S S e
|
||||
\ E E E E E E E _
|
||||
\ T T T T T T T e
|
||||
\ _ _ _ _ _ _ _ n
|
||||
\ C C C C C C C a
|
||||
\ N N N N N N N b
|
||||
\ T T T T T T T l
|
||||
\ R R R R R R R e
|
||||
\ < < < < < < < .
|
||||
\ 0 1 2 3 4 5 6 Q
|
||||
\ > > > > > > >
|
||||
\ . . . . . . .
|
||||
\ Q Q Q Q Q Q Q
|
||||
\
|
||||
\
|
||||
\ From I R R R R R R R
|
||||
\ D E E E E E E E
|
||||
\ E S S S S S S S
|
||||
\ / E E E E E E E
|
||||
\ i T T T T T T T
|
||||
\ d _ _ _ _ _ _ _
|
||||
\ e C C C C C C C
|
||||
\ _ N N N N N N N
|
||||
\ e T T T T T T T
|
||||
\ n R R R R R R R
|
||||
\ a < < < < < < <
|
||||
\ b 0 1 2 3 4 5 6
|
||||
\ l > > > > > > >
|
||||
\ e . . . . . . .
|
||||
\ d Q Q Q Q Q Q Q
|
||||
\ .
|
||||
\ Q
|
||||
\
|
||||
\
|
||||
\
|
||||
@ -276,6 +276,60 @@ ide_enable.CE
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AS_n_S4.D
|
||||
AUTOCONFIG/dtack.D
|
||||
AUTOCONFIG/ide_base<0>.CE
|
||||
AUTOCONFIG/ide_base<1>.CE
|
||||
AUTOCONFIG/ide_base<2>.CE
|
||||
AUTOCONFIG/ide_configured.CE
|
||||
AUTOCONFIG/shutup.CE
|
||||
DBUS<12>.D
|
||||
IDE/as_delay<1>.D
|
||||
IDE/ide_enabled.D 11.4
|
||||
RESET_CNTR<0>.D 10.0 10.0
|
||||
RESET_CNTR<1>.D 10.0 10.0 10.0
|
||||
RESET_CNTR<2>.D 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<3>.D 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<4>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<5>.D 11.0 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
RESET_CNTR<6>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
ide_enable.CE 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C3n)
|
||||
|
||||
\ From i
|
||||
\ d
|
||||
\ e
|
||||
\ _
|
||||
\ e
|
||||
\ n
|
||||
\ a
|
||||
\ b
|
||||
\ l
|
||||
\ e
|
||||
\ .
|
||||
\ Q
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
To \------
|
||||
|
||||
AS_n_S4.D
|
||||
AUTOCONFIG/dtack.D
|
||||
AUTOCONFIG/ide_base<0>.CE
|
||||
AUTOCONFIG/ide_base<1>.CE
|
||||
@ -285,58 +339,6 @@ AUTOCONFIG/shutup.CE
|
||||
DBUS<12>.D 11.0
|
||||
IDE/as_delay<1>.D
|
||||
IDE/ide_enabled.D
|
||||
RESET_CNTR<0>.D 10.0 10.0
|
||||
RESET_CNTR<1>.D 10.0 10.0 10.0
|
||||
RESET_CNTR<2>.D 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<3>.D 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<4>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<5>.D 11.0 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
RESET_CNTR<6>.D 11.0 11.0 11.0 11.0 11.0 11.0 10.0
|
||||
ide_enable.CE 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C1n)
|
||||
|
||||
\ From A A A A A A I I
|
||||
\ U U U U U U D D
|
||||
\ T T T T T T E E
|
||||
\ O O O O O O / /
|
||||
\ C C C C C C a i
|
||||
\ O O O O O O s d
|
||||
\ N N N N N N _ e
|
||||
\ F F F F F F d _
|
||||
\ I I I I I I e e
|
||||
\ G G G G G G l n
|
||||
\ / / / / / / a a
|
||||
\ d i i i i s y b
|
||||
\ t d d d d h < l
|
||||
\ a e e e e u 0 e
|
||||
\ c _ _ _ _ t > d
|
||||
\ k b b b c u . .
|
||||
\ . a a a o p Q Q
|
||||
\ Q s s s n .
|
||||
\ e e e f Q
|
||||
\ < < < i
|
||||
\ 0 1 2 g
|
||||
\ > > > u
|
||||
\ . . . r
|
||||
\ Q Q Q e
|
||||
\ d
|
||||
\ .
|
||||
\ Q
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AUTOCONFIG/dtack.D 11.0
|
||||
AUTOCONFIG/ide_base<0>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_base<1>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_base<2>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_configured.CE 10.0 10.0
|
||||
AUTOCONFIG/shutup.CE 10.0 10.0
|
||||
DBUS<12>.D
|
||||
IDE/as_delay<1>.D 11.0
|
||||
IDE/ide_enabled.D 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
RESET_CNTR<0>.D
|
||||
RESET_CNTR<1>.D
|
||||
RESET_CNTR<2>.D
|
||||
@ -350,23 +352,76 @@ ide_enable.CE
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C1n)
|
||||
|
||||
\ From R R R R R R R i
|
||||
\ E E E E E E E d
|
||||
\ S S S S S S S e
|
||||
\ E E E E E E E _
|
||||
\ T T T T T T T e
|
||||
\ _ _ _ _ _ _ _ n
|
||||
\ C C C C C C C a
|
||||
\ N N N N N N N b
|
||||
\ T T T T T T T l
|
||||
\ R R R R R R R e
|
||||
\ < < < < < < < .
|
||||
\ 0 1 2 3 4 5 6 Q
|
||||
\ > > > > > > >
|
||||
\ . . . . . . .
|
||||
\ Q Q Q Q Q Q Q
|
||||
\
|
||||
\ From A A A A A A A I
|
||||
\ S U U U U U U D
|
||||
\ _ T T T T T T E
|
||||
\ n O O O O O O /
|
||||
\ _ C C C C C C S
|
||||
\ S O O O O O O 3
|
||||
\ 4 N N N N N N _
|
||||
\ . F F F F F F n
|
||||
\ Q I I I I I I .
|
||||
\ G G G G G G Q
|
||||
\ / / / / / /
|
||||
\ d i i i i s
|
||||
\ t d d d d h
|
||||
\ a e e e e u
|
||||
\ c _ _ _ _ t
|
||||
\ k b b b c u
|
||||
\ . a a a o p
|
||||
\ Q s s s n .
|
||||
\ e e e f Q
|
||||
\ < < < i
|
||||
\ 0 1 2 g
|
||||
\ > > > u
|
||||
\ . . . r
|
||||
\ Q Q Q e
|
||||
\ d
|
||||
\ .
|
||||
\ Q
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AS_n_S4.D 11.0
|
||||
AUTOCONFIG/dtack.D 10.0
|
||||
AUTOCONFIG/ide_base<0>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_base<1>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_base<2>.CE 10.0 10.0
|
||||
AUTOCONFIG/ide_configured.CE 10.0 10.0
|
||||
AUTOCONFIG/shutup.CE 10.0 10.0
|
||||
DBUS<12>.D
|
||||
IDE/as_delay<1>.D 10.0
|
||||
IDE/ide_enabled.D 11.4 11.4 11.4 11.4 11.4
|
||||
RESET_CNTR<0>.D
|
||||
RESET_CNTR<1>.D
|
||||
RESET_CNTR<2>.D
|
||||
RESET_CNTR<3>.D
|
||||
RESET_CNTR<4>.D
|
||||
RESET_CNTR<5>.D
|
||||
RESET_CNTR<6>.D
|
||||
ide_enable.CE
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C1n)
|
||||
|
||||
\ From I R R R R R R R
|
||||
\ D E E E E E E E
|
||||
\ E S S S S S S S
|
||||
\ / E E E E E E E
|
||||
\ i T T T T T T T
|
||||
\ d _ _ _ _ _ _ _
|
||||
\ e C C C C C C C
|
||||
\ _ N N N N N N N
|
||||
\ e T T T T T T T
|
||||
\ n R R R R R R R
|
||||
\ a < < < < < < <
|
||||
\ b 0 1 2 3 4 5 6
|
||||
\ l > > > > > > >
|
||||
\ e . . . . . . .
|
||||
\ d Q Q Q Q Q Q Q
|
||||
\ .
|
||||
\ Q
|
||||
\
|
||||
\
|
||||
\
|
||||
@ -380,6 +435,60 @@ ide_enable.CE
|
||||
\
|
||||
To \------------------------------------------------
|
||||
|
||||
AS_n_S4.D
|
||||
AUTOCONFIG/dtack.D
|
||||
AUTOCONFIG/ide_base<0>.CE
|
||||
AUTOCONFIG/ide_base<1>.CE
|
||||
AUTOCONFIG/ide_base<2>.CE
|
||||
AUTOCONFIG/ide_configured.CE
|
||||
AUTOCONFIG/shutup.CE
|
||||
DBUS<12>.D
|
||||
IDE/as_delay<1>.D
|
||||
IDE/ide_enabled.D 11.4
|
||||
RESET_CNTR<0>.D 10.0 10.0
|
||||
RESET_CNTR<1>.D 10.0 10.0 10.0
|
||||
RESET_CNTR<2>.D 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<3>.D 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<4>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<5>.D 11.0 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
RESET_CNTR<6>.D 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
ide_enable.CE 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Clock to Setup (tCYC) (nsec)
|
||||
(Clock: C1n)
|
||||
|
||||
\ From i
|
||||
\ d
|
||||
\ e
|
||||
\ _
|
||||
\ e
|
||||
\ n
|
||||
\ a
|
||||
\ b
|
||||
\ l
|
||||
\ e
|
||||
\ .
|
||||
\ Q
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
\
|
||||
To \------
|
||||
|
||||
AS_n_S4.D
|
||||
AUTOCONFIG/dtack.D
|
||||
AUTOCONFIG/ide_base<0>.CE
|
||||
AUTOCONFIG/ide_base<1>.CE
|
||||
@ -389,14 +498,14 @@ AUTOCONFIG/shutup.CE
|
||||
DBUS<12>.D 11.0
|
||||
IDE/as_delay<1>.D
|
||||
IDE/ide_enabled.D
|
||||
RESET_CNTR<0>.D 10.0 10.0
|
||||
RESET_CNTR<1>.D 10.0 10.0 10.0
|
||||
RESET_CNTR<2>.D 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<3>.D 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<4>.D 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<5>.D 11.0 11.0 11.0 11.0 11.0 11.0 11.0
|
||||
RESET_CNTR<6>.D 11.0 11.0 11.0 11.0 11.0 11.0 10.0
|
||||
ide_enable.CE 10.0 10.0 10.0 10.0 10.0 10.0 10.0
|
||||
RESET_CNTR<0>.D
|
||||
RESET_CNTR<1>.D
|
||||
RESET_CNTR<2>.D
|
||||
RESET_CNTR<3>.D
|
||||
RESET_CNTR<4>.D
|
||||
RESET_CNTR<5>.D
|
||||
RESET_CNTR<6>.D
|
||||
ide_enable.CE
|
||||
|
||||
Path Type Definition:
|
||||
|
||||
|
||||
@ -34,7 +34,7 @@ module Autoconfig (
|
||||
|
||||
// Autoconfig
|
||||
localparam [15:0] mfg_id = 16'd5194;
|
||||
localparam [7:0] prod_id = 8'd5;
|
||||
localparam [7:0] prod_id = 8'd7;
|
||||
localparam [31:0] serial = `SERIAL;
|
||||
|
||||
reg ide_configured = 0;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user