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Compile latest version for prototype revision

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This commit is contained in:
Matt Harlum 2024-08-07 23:22:48 +12:00
parent 1551249b90
commit 96b7f2a179
7 changed files with 1469 additions and 1551 deletions
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1516
Binary/RIPPLE.jed
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File diff suppressed because it is too large Load Diff

17
RTL/IDE.v
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@ -30,9 +30,8 @@ module IDE(
output DTACK,
output IOR_n,
output IOW_n,
output [1:0] IDE1_CS_n,
output [1:0] IDE2_CS_n,
output [1:0] ROM_BANK,
output IDE1_CS_n,
output IDE2_CS_n,
output IDE_ROMEN
);
@ -40,12 +39,8 @@ wire ds = !UDS_n || !LDS_n;
reg ide_dtack;
reg ide_enabled = 0;
reg bank_sel = 0;
reg [1:0] as_delay; // AS_n shifted by CLK
reg [1:0] rom_bankSel;
assign ROM_BANK = (ide_enabled) ? rom_bankSel : {1'b0,ADDR[16]};
reg S3_n; // S3 has started
@ -54,21 +49,17 @@ assign AS_n_S4 = as_delay[0];
always @(posedge CLK or negedge RESET_n) begin
if (!RESET_n) begin
ide_enabled <= 0;
rom_bankSel <= 0;
end else begin
// IDE enabled on first write seen
if (ide_enable && ide_access && !RW && !UDS_n && !S3_n) ide_enabled <= 1;
if (ide_enable && ide_access && ADDR[16:15] == 2'b01 && !RW && !UDS_n && !S3_n) rom_bankSel <= DIN;
end
end
wire CS_0 = ide_enabled && ide_access && ADDR[16:15] == 2'b00 && ADDR[13:12] == 2'b01;
wire CS_1 = ide_enabled && ide_access && ADDR[16:15] == 2'b00 && ADDR[13:12] == 2'b10;
assign IDE1_CS_n[0] = !(!ADDR[14] && CS_0);
assign IDE2_CS_n[0] = !(!ADDR[14] && CS_1);
assign IDE1_CS_n[1] = !( ADDR[14] && CS_0);
assign IDE2_CS_n[1] = !( ADDR[14] && CS_1);
assign IDE1_CS_n = !(!ADDR[14] && CS_0);
assign IDE2_CS_n = !(!ADDR[14] && CS_1);
// IDE ROM is mapped to whole range until ide is enabled by the first write
// After then, it is mapped to (base address) + 64K

2
RTL/Makefile
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@ -7,7 +7,7 @@ DEFINES=makedefines SERIAL=32'h${SERIAL} PRODID=${PRODID}
CABLE=usb21
CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper -optimize speed -pterms 21
CPLDFITFLAGS=-loc on -slew slow -init low -terminate keeper -optimize speed -pterms 21
.PHONY: all clean timing

633
RTL/RIPPLE.rpt
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@ -1,7 +1,7 @@
cpldfit: version P.20131013 Xilinx Inc.
Fitter Report
Design Name: RIPPLE Date: 4-18-2024, 4:18AM
Design Name: RIPPLE Date: 8- 7-2024, 12:06PM
Device Used: XC9572XL-10-VQ64
Fitting Status: Successful
@ -9,18 +9,18 @@ Fitting Status: Successful
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
41 /72 ( 57%) 193 /360 ( 54%) 114/216 ( 53%) 23 /72 ( 32%) 48 /52 ( 92%)
37 /72 ( 51%) 163 /360 ( 45%) 111/216 ( 51%) 24 /72 ( 33%) 44 /52 ( 85%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 3/18 5/54 7/90 10/13
FB2 11/18 39/54 44/90 12/13
FB3 9/18 31/54 81/90 14/14*
FB4 18/18* 39/54 61/90 12/12*
FB1 0/18 0/54 0/90 10/13
FB2 9/18 39/54 41/90 12/13
FB3 10/18 33/54 54/90 13/14
FB4 18/18* 39/54 68/90 9/12
----- ----- ----- -----
41/72 114/216 193/360 48/52
37/72 111/216 163/360 44/52
* - Resource is exhausted
@ -34,18 +34,18 @@ Global set/reset net(s) unused.
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 29 29 | I/O : 43 46
Output : 15 15 | GCK/IO : 2 3
Input : 29 29 | I/O : 39 46
Output : 11 11 | GCK/IO : 2 3
Bidirectional : 4 4 | GTS/IO : 2 2
GCK : 0 0 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 48 48
Total 44 44
** Power Data **
There are 41 macrocells in high performance mode (MCHP).
There are 37 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
@ -73,6 +73,8 @@ WARNING:Cpld:1007 - Removing unused input(s) 'ADDR<11>'. The input(s) are
unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'ADDR<9>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'CDACn'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'LDS_n'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'ADDR_13_IBUF'
@ -83,90 +85,86 @@ WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'ADDR_12_IBUF'
global control signal.
************************* Summary of Mapped Logic ************************
** 19 Outputs **
** 15 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DBUS<15> 8 23 FB2_3 58 I/O I/O STD SLOW RESET
IDEBUF_OE 4 17 FB2_4 59 I/O O STD SLOW
DTACK_n 0 0 FB2_10 1 I/O O STD SLOW
OVR_n_1 0 0 FB3_6 34 I/O O STD SLOW
IDE_ROMEN 19 21 FB3_11 33 I/O O STD SLOW
OVR_n_2 0 0 FB3_14 35 I/O O STD SLOW
ROM_BANK<1> 1 2 FB3_15 36 I/O O STD SLOW
CFGOUT_n 3 4 FB3_16 42 I/O O STD SLOW SET
SLAVE_n 3 13 FB4_2 43 I/O O STD SLOW
ROM_BANK<0> 2 3 FB4_3 46 I/O O STD SLOW
IDE2_CS_n<1> 1 4 FB4_4 47 I/O O STD SLOW
IOR_n 1 3 FB4_5 44 I/O O STD SLOW
IDE1_CS_n<1> 1 4 FB4_6 49 I/O O STD SLOW
IOW_n 1 4 FB4_8 45 I/O O STD SLOW
IDE2_CS_n<0> 1 4 FB4_11 48 I/O O STD SLOW
DBUS<12> 8 24 FB4_12 52 I/O I/O STD SLOW RESET
IDE1_CS_n<0> 1 4 FB4_14 50 I/O O STD SLOW
DBUS<13> 7 23 FB4_15 56 I/O I/O STD SLOW RESET
DBUS<14> 8 23 FB4_17 57 I/O I/O STD SLOW RESET
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
DBUS<15> 8 23 FB2_3 58 I/O I/O STD SLOW RESET
IDEBUF_OE 3 16 FB2_4 59 I/O O STD SLOW
DTACK_n 0 0 FB2_10 1 I/O O STD SLOW
OVR_n_1 0 0 FB3_6 34 I/O O STD SLOW
IDE_ROMEN 19 21 FB3_11 33 I/O O STD SLOW
OVR_n_2 0 0 FB3_14 35 I/O O STD SLOW
CFGOUT_n 3 4 FB3_16 42 I/O O STD SLOW SET
SLAVE_n 2 12 FB4_2 43 I/O O STD SLOW
IOR_n 1 3 FB4_5 44 I/O O STD SLOW
IDE2_CS_n 1 7 FB4_6 49 I/O O STD SLOW
IOW_n 1 4 FB4_8 45 I/O O STD SLOW
DBUS<12> 8 24 FB4_12 52 I/O I/O STD SLOW RESET
IDE1_CS_n 1 7 FB4_14 50 I/O O STD SLOW
DBUS<13> 7 23 FB4_15 56 I/O I/O STD SLOW RESET
DBUS<14> 8 23 FB4_17 57 I/O I/O STD SLOW RESET
** 22 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
ide_enable/ide_enable_CLKF 2 2 FB1_16 STD
IDE/S3_n/IDE/S3_n_CLKF 2 2 FB1_17 STD
ide_enable 3 3 FB1_18 STD RESET
RESET 2 2 FB2_1 STD RESET
IDE/as_delay<1> 3 4 FB2_2 STD RESET
AUTOCONFIG/shutup 3 25 FB2_5 STD RESET
AUTOCONFIG/ide_base<7> 4 26 FB2_6 STD RESET
AUTOCONFIG/ide_base<4> 4 26 FB2_7 STD RESET
AUTOCONFIG/ide_base<3> 4 26 FB2_8 STD RESET
IDE/rom_bankSel<1> 6 13 FB2_9 STD RESET
IDE/rom_bankSel<0> 6 13 FB2_11 STD RESET
IDE/ide_enabled 22 23 FB3_1 STD RESET
$OpTx$INV$24 14 14 FB3_5 STD
$OpTx$FX_DC$38 19 19 FB3_10 STD
IDE/S3_n 3 3 FB3_17 STD RESET
AUTOCONFIG/dtack 5 16 FB4_1 STD RESET
AS_n_S4 3 4 FB4_7 STD RESET
AUTOCONFIG/ide_base<6> 4 26 FB4_9 STD RESET
AUTOCONFIG/ide_base<5> 4 26 FB4_10 STD RESET
AUTOCONFIG/ide_base<2> 4 26 FB4_13 STD RESET
AUTOCONFIG/ide_base<1> 4 26 FB4_16 STD RESET
AUTOCONFIG/ide_configured 3 25 FB4_18 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
reset_delay<0> 2 2 FB2_1 STD RESET
ide_enable 3 3 FB2_2 STD RESET
IDE/as_delay<1> 3 4 FB2_5 STD RESET
IDE/S3_n 3 3 FB2_6 STD RESET
AUTOCONFIG/shutup 3 25 FB2_7 STD RESET
$OpTx$FX_DC$41 16 16 FB2_9 STD
IDE/ide_enabled 22 23 FB3_1 STD RESET
reset_delay<2>/reset_delay<2>_CLKF 2 2 FB3_8 STD
reset_delay<2> 2 2 FB3_12 STD RESET
reset_delay<1> 2 2 FB3_13 STD RESET
RESET 2 4 FB3_15 STD RESET
IDE/S3_n/IDE/S3_n_CLKF 2 2 FB3_17 STD
IDE/as_delay<0> 3 4 FB4_1 STD RESET
AUTOCONFIG/ide_configured 3 25 FB4_3 STD RESET
AUTOCONFIG/ide_base<7> 4 26 FB4_4 STD RESET
AUTOCONFIG/ide_base<6> 4 26 FB4_7 STD RESET
AUTOCONFIG/ide_base<5> 4 26 FB4_9 STD RESET
AUTOCONFIG/ide_base<4> 4 26 FB4_10 STD RESET
AUTOCONFIG/ide_base<3> 4 26 FB4_11 STD RESET
AUTOCONFIG/ide_base<2> 4 26 FB4_13 STD RESET
AUTOCONFIG/ide_base<1> 4 26 FB4_16 STD RESET
AUTOCONFIG/dtack 5 16 FB4_18 STD RESET
** 29 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
ADDR<18> FB1_2 8 I/O I
ADDR<15> FB1_3 12 I/O I
ADDR<14> FB1_4 13 I/O I
ADDR<17> FB1_5 9 I/O I
ADDR<16> FB1_6 10 I/O I
BERR_n FB1_8 11 I/O I
ADDR<13> FB1_9 15 GCK/I/O I
ADDR<12> FB1_11 16 GCK/I/O I
ADDR<2> FB1_12 23 I/O I
ADDR<1> FB1_17 20 I/O I
AS_n FB2_2 60 I/O I
UDS_n FB2_5 61 I/O I
RW FB2_8 63 I/O I
RESET_n FB2_9 64 GSR/I/O I
ADDR<23> FB2_11 2 GTS/I/O I
ADDR<21> FB2_12 4 I/O I
ADDR<22> FB2_14 5 GTS/I/O I
ADDR<20> FB2_15 6 I/O I
ADDR<19> FB2_17 7 I/O I
ADDR<8> FB3_2 22 I/O I
ADDR<4> FB3_3 31 I/O I
ADDR<5> FB3_4 32 I/O I
ADDR<7> FB3_5 24 I/O I
ADDR<3> FB3_8 25 I/O I
ADDR<6> FB3_9 27 I/O I
C3n FB3_10 39 I/O I
CFGIN_n FB3_12 40 I/O I
C1n FB3_17 38 I/O I
IDE_OFF_n FB4_10 51 I/O I
Signal Loc Pin Pin Pin
Name No. Type Use
ADDR<18> FB1_2 8 I/O I
ADDR<15> FB1_3 12 I/O I
ADDR<14> FB1_4 13 I/O I
ADDR<17> FB1_5 9 I/O I
ADDR<16> FB1_6 10 I/O I
BERR_n FB1_8 11 I/O I
ADDR<13> FB1_9 15 GCK/I/O I
ADDR<12> FB1_11 16 GCK/I/O I
ADDR<2> FB1_12 23 I/O I
ADDR<1> FB1_17 20 I/O I
AS_n FB2_2 60 I/O I
UDS_n FB2_5 61 I/O I
RW FB2_8 63 I/O I
RESET_n FB2_9 64 GSR/I/O I
ADDR<23> FB2_11 2 GTS/I/O I
ADDR<21> FB2_12 4 I/O I
ADDR<22> FB2_14 5 GTS/I/O I
ADDR<20> FB2_15 6 I/O I
ADDR<19> FB2_17 7 I/O I
ADDR<8> FB3_2 22 I/O I
ADDR<4> FB3_3 31 I/O I
ADDR<5> FB3_4 32 I/O I
ADDR<7> FB3_5 24 I/O I
ADDR<3> FB3_8 25 I/O I
ADDR<6> FB3_9 27 I/O I
C3n FB3_10 39 I/O I
CFGIN_n FB3_12 40 I/O I
C1n FB3_17 38 I/O I
IDE_OFF_n FB4_10 51 I/O I
Legend:
Pin No. - ~ - User Assigned
@ -184,8 +182,8 @@ Pin Type/Use - I - Input GCK - Global Clock
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/49
Number of signals used by logic mapping into function block: 5
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
@ -203,44 +201,25 @@ Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 17 GCK/I/O
(unused) 0 0 0 5 FB1_15 19 I/O
ide_enable/ide_enable_CLKF
2 0 0 3 FB1_16 (b) (b)
IDE/S3_n/IDE/S3_n_CLKF
2 0 0 3 FB1_17 20 I/O I
ide_enable 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: C1n 3: IDE_OFF_n 5: ide_enable/ide_enable_CLKF
2: C3n 4: RESET
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ide_enable/ide_enable_CLKF
XX...................................... 2
IDE/S3_n/IDE/S3_n_CLKF
XX...................................... 2
ide_enable ..XXX................................... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 20 I/O I
(unused) 0 0 0 5 FB1_18 (b)
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 39/15
Number of signals used by logic mapping into function block: 39
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
RESET 2 0 0 3 FB2_1 (b) (b)
IDE/as_delay<1> 3 0 \/2 0 FB2_2 60 I/O I
reset_delay<0> 2 0 0 3 FB2_1 (b) (b)
ide_enable 3 0 \/1 1 FB2_2 60 I/O I
DBUS<15> 8 3<- 0 0 FB2_3 58 I/O I/O
IDEBUF_OE 4 0 /\1 0 FB2_4 59 I/O O
AUTOCONFIG/shutup 3 0 0 2 FB2_5 61 I/O I
AUTOCONFIG/ide_base<7>
4 0 0 1 FB2_6 62 I/O (b)
AUTOCONFIG/ide_base<4>
4 0 0 1 FB2_7 (b) (b)
AUTOCONFIG/ide_base<3>
4 0 \/1 0 FB2_8 63 I/O I
IDE/rom_bankSel<1> 6 1<- 0 0 FB2_9 64 GSR/I/O I
DTACK_n 0 0 \/1 4 FB2_10 1 I/O O
IDE/rom_bankSel<0> 6 1<- 0 0 FB2_11 2 GTS/I/O I
IDEBUF_OE 3 0 /\2 0 FB2_4 59 I/O O
IDE/as_delay<1> 3 0 0 2 FB2_5 61 I/O I
IDE/S3_n 3 0 0 2 FB2_6 62 I/O (b)
AUTOCONFIG/shutup 3 0 \/2 0 FB2_7 (b) (b)
(unused) 0 0 \/5 0 FB2_8 63 I/O I
$OpTx$FX_DC$41 16 11<- 0 0 FB2_9 64 GSR/I/O I
DTACK_n 0 0 /\4 1 FB2_10 1 I/O O
(unused) 0 0 0 5 FB2_11 2 GTS/I/O I
(unused) 0 0 0 5 FB2_12 4 I/O I
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 5 GTS/I/O I
@ -250,86 +229,86 @@ IDE/rom_bankSel<0> 6 1<- 0 0 FB2_11 2 GTS/I/O I
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$24 14: ADDR<4> 27: CFGOUT_n
2: ADDR<15> 15: ADDR<5> 28: IDE/S3_n
3: ADDR<16> 16: ADDR<6> 29: IDE/rom_bankSel<0>
4: ADDR<17> 17: ADDR<7> 30: IDE/rom_bankSel<1>
5: ADDR<18> 18: ADDR<8> 31: DBUS<15>.PIN
6: ADDR<19> 19: AS_n 32: DBUS<14>.PIN
7: ADDR<1> 20: AS_n_S4 33: DBUS<12>.PIN
8: ADDR<20> 21: AUTOCONFIG/dtack 34: RESET
9: ADDR<21> 22: AUTOCONFIG/ide_base<5> 35: RESET_n
10: ADDR<22> 23: AUTOCONFIG/ide_configured 36: RW
11: ADDR<23> 24: AUTOCONFIG/shutup 37: UDS_n
12: ADDR<2> 25: BERR_n 38: ide_enable
13: ADDR<3> 26: CFGIN_n 39: ide_enable/ide_enable_CLKF
1: $OpTx$FX_DC$41 14: ADDR<5> 27: AUTOCONFIG/ide_configured
2: ADDR<16> 15: ADDR<6> 28: AUTOCONFIG/shutup
3: ADDR<17> 16: ADDR<7> 29: BERR_n
4: ADDR<18> 17: ADDR<8> 30: CFGIN_n
5: ADDR<19> 18: AS_n 31: CFGOUT_n
6: ADDR<1> 19: AUTOCONFIG/dtack 32: IDE/S3_n/IDE/S3_n_CLKF
7: ADDR<20> 20: AUTOCONFIG/ide_base<1> 33: IDE/as_delay<0>
8: ADDR<21> 21: AUTOCONFIG/ide_base<2> 34: IDE_OFF_n
9: ADDR<22> 22: AUTOCONFIG/ide_base<3> 35: RESET
10: ADDR<23> 23: AUTOCONFIG/ide_base<4> 36: RESET_n
11: ADDR<2> 24: AUTOCONFIG/ide_base<5> 37: RW
12: ADDR<3> 25: AUTOCONFIG/ide_base<6> 38: UDS_n
13: ADDR<4> 26: AUTOCONFIG/ide_base<7> 39: reset_delay<2>/reset_delay<2>_CLKF
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
RESET ..................................X...X. 2
IDE/as_delay<1> ..................XX.............X....X. 4
DBUS<15> ..XXXXXXXXXXXXXXXXX......XX......XXX..X. 23
IDEBUF_OE X.XXXX.XXXX.......XX.X..XXX.......XX.... 17
AUTOCONFIG/shutup ..XXXXXXXXXXXXXXXXX.X..X.XX......X.XX.X. 25
AUTOCONFIG/ide_base<7>
..XXXXXXXXXXXXXXXXX.X.X..XX...X..X.XX.X. 26
AUTOCONFIG/ide_base<4>
..XXXXXXXXXXXXXXXXX.X.X..XX.....XX.XX.X. 26
AUTOCONFIG/ide_base<3>
..XXXXXXXXXXXXXXXXX.X.X..XX...X..X.XX.X. 26
IDE/rom_bankSel<1> XXX.....X............X.....X.XX..X.XXXX. 13
reset_delay<0> ...................................X..X. 2
ide_enable .................................XX...X. 3
DBUS<15> .XXXXXXXXXXXXXXXXX...........XX...XXX.X. 23
IDEBUF_OE XXXXX.XXXX.......X..........XXX.X..XX... 16
IDE/as_delay<1> .................X..............X.X...X. 4
IDE/S3_n .................X.............X..X..... 3
AUTOCONFIG/shutup .XXXXXXXXXXXXXXXXXX........X.XX...X.XXX. 25
$OpTx$FX_DC$41 ..XXX.XXXX.........XXXXXXXX...X......... 16
DTACK_n ........................................ 0
IDE/rom_bankSel<0> XXX.....X............X.....XX..X.X.XXXX. 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Number of function block inputs used/remaining: 33/21
Number of signals used by logic mapping into function block: 33
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
IDE/ide_enabled 22 17<- 0 0 FB3_1 (b) (b)
(unused) 0 0 /\5 0 FB3_2 22 I/O I
(unused) 0 0 /\5 0 FB3_3 31 I/O I
(unused) 0 0 \/5 0 FB3_4 32 I/O I
$OpTx$INV$24 14 9<- 0 0 FB3_5 24 I/O I
OVR_n_1 0 0 /\4 1 FB3_6 34 I/O O
(unused) 0 0 \/5 0 FB3_7 (b) (b)
(unused) 0 0 \/5 0 FB3_8 25 I/O I
(unused) 0 0 0 5 FB3_4 32 I/O I
(unused) 0 0 0 5 FB3_5 24 I/O I
OVR_n_1 0 0 0 5 FB3_6 34 I/O O
(unused) 0 0 0 5 FB3_7 (b)
reset_delay<2>/reset_delay<2>_CLKF
2 0 \/1 2 FB3_8 25 I/O I
(unused) 0 0 \/5 0 FB3_9 27 I/O I
$OpTx$FX_DC$38 19 15<- \/1 0 FB3_10 39 I/O I
(unused) 0 0 \/5 0 FB3_10 39 I/O I
IDE_ROMEN 19 14<- 0 0 FB3_11 33 I/O O
(unused) 0 0 /\5 0 FB3_12 40 I/O I
(unused) 0 0 /\5 0 FB3_13 (b) (b)
OVR_n_2 0 0 /\3 2 FB3_14 35 I/O O
ROM_BANK<1> 1 0 0 4 FB3_15 36 I/O O
reset_delay<2> 2 0 /\3 0 FB3_12 40 I/O I
reset_delay<1> 2 0 0 3 FB3_13 (b) (b)
OVR_n_2 0 0 0 5 FB3_14 35 I/O O
RESET 2 0 0 3 FB3_15 36 I/O (b)
CFGOUT_n 3 0 0 2 FB3_16 42 I/O O
IDE/S3_n 3 0 \/2 0 FB3_17 38 I/O I
IDE/S3_n/IDE/S3_n_CLKF
2 0 \/2 1 FB3_17 38 I/O I
(unused) 0 0 \/5 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: ADDR<12> 12: AS_n 22: CFGOUT_n
2: ADDR<13> 13: AUTOCONFIG/ide_base<1> 23: IDE/S3_n
3: ADDR<15> 14: AUTOCONFIG/ide_base<2> 24: IDE/S3_n/IDE/S3_n_CLKF
4: ADDR<16> 15: AUTOCONFIG/ide_base<3> 25: IDE/ide_enabled
5: ADDR<17> 16: AUTOCONFIG/ide_base<4> 26: IDE/rom_bankSel<1>
6: ADDR<18> 17: AUTOCONFIG/ide_base<5> 27: RESET
7: ADDR<19> 18: AUTOCONFIG/ide_base<6> 28: RW
8: ADDR<20> 19: AUTOCONFIG/ide_base<7> 29: UDS_n
9: ADDR<21> 20: AUTOCONFIG/ide_configured 30: ide_enable
10: ADDR<22> 21: AUTOCONFIG/shutup 31: ide_enable/ide_enable_CLKF
11: ADDR<23>
1: ADDR<12> 12: AUTOCONFIG/ide_base<1> 23: CFGOUT_n
2: ADDR<13> 13: AUTOCONFIG/ide_base<2> 24: IDE/S3_n
3: ADDR<16> 14: AUTOCONFIG/ide_base<3> 25: IDE/ide_enabled
4: ADDR<17> 15: AUTOCONFIG/ide_base<4> 26: RESET
5: ADDR<18> 16: AUTOCONFIG/ide_base<5> 27: RW
6: ADDR<19> 17: AUTOCONFIG/ide_base<6> 28: UDS_n
7: ADDR<20> 18: AUTOCONFIG/ide_base<7> 29: ide_enable
8: ADDR<21> 19: AUTOCONFIG/ide_configured 30: reset_delay<0>
9: ADDR<22> 20: AUTOCONFIG/shutup 31: reset_delay<1>
10: ADDR<23> 21: C1n 32: reset_delay<2>
11: AS_n 22: C3n 33: reset_delay<2>/reset_delay<2>_CLKF
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
IDE/ide_enabled ....XXXXXXX.XXXXXXXX.XX.X.XXXXX......... 23
$OpTx$INV$24 ....XXXX.XX.XXXX.XXX.X.................. 14
IDE/ide_enabled ...XXXXXXX.XXXXXXXX...XXXXXXX...X....... 23
OVR_n_1 ........................................ 0
$OpTx$FX_DC$38 ..XXXXXXXXX.XXXXXXXX.X..X............... 19
IDE_ROMEN XX.XXXXXXXXXXXXXXXXX.X..X............... 21
reset_delay<2>/reset_delay<2>_CLKF
....................XX.................. 2
IDE_ROMEN XXXXXXXXXXXXXXXXXXX...X.X............... 21
reset_delay<2> ..............................X.X....... 2
reset_delay<1> .............................X..X....... 2
OVR_n_2 ........................................ 0
ROM_BANK<1> ........................XX.............. 2
CFGOUT_n ...........X.......XX.....X............. 4
IDE/S3_n ...........X...........X..X............. 3
RESET .............................XXXX....... 4
CFGOUT_n ..........X.......XX.....X.............. 4
IDE/S3_n/IDE/S3_n_CLKF
....................XX.................. 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
@ -337,132 +316,115 @@ Number of function block inputs used/remaining: 39/15
Number of signals used by logic mapping into function block: 39
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
AUTOCONFIG/dtack 5 0 0 0 FB4_1 (b) (b)
SLAVE_n 3 0 0 2 FB4_2 43 I/O O
ROM_BANK<0> 2 0 0 3 FB4_3 46 I/O O
IDE2_CS_n<1> 1 0 0 4 FB4_4 47 I/O O
IDE/as_delay<0> 3 0 /\2 0 FB4_1 (b) (b)
SLAVE_n 2 0 0 3 FB4_2 43 I/O O
AUTOCONFIG/ide_configured
3 0 0 2 FB4_3 46 I/O (b)
AUTOCONFIG/ide_base<7>
4 0 0 1 FB4_4 47 I/O (b)
IOR_n 1 0 0 4 FB4_5 44 I/O O
IDE1_CS_n<1> 1 0 0 4 FB4_6 49 I/O O
AS_n_S4 3 0 0 2 FB4_7 (b) (b)
IOW_n 1 0 0 4 FB4_8 45 I/O O
IDE2_CS_n 1 0 0 4 FB4_6 49 I/O O
AUTOCONFIG/ide_base<6>
4 0 0 1 FB4_9 (b) (b)
4 0 0 1 FB4_7 (b) (b)
IOW_n 1 0 0 4 FB4_8 45 I/O O
AUTOCONFIG/ide_base<5>
4 0 0 1 FB4_10 51 I/O I
IDE2_CS_n<0> 1 0 \/3 1 FB4_11 48 I/O O
4 0 0 1 FB4_9 (b) (b)
AUTOCONFIG/ide_base<4>
4 0 \/1 0 FB4_10 51 I/O I
AUTOCONFIG/ide_base<3>
4 1<- \/2 0 FB4_11 48 I/O (b)
DBUS<12> 8 3<- 0 0 FB4_12 52 I/O I/O
AUTOCONFIG/ide_base<2>
4 0 0 1 FB4_13 (b) (b)
IDE1_CS_n<0> 1 0 \/2 2 FB4_14 50 I/O O
4 0 /\1 0 FB4_13 (b) (b)
IDE1_CS_n 1 0 \/2 2 FB4_14 50 I/O O
DBUS<13> 7 2<- 0 0 FB4_15 56 I/O I/O
AUTOCONFIG/ide_base<1>
4 0 \/1 0 FB4_16 (b) (b)
DBUS<14> 8 3<- 0 0 FB4_17 57 I/O I/O
AUTOCONFIG/ide_configured
3 0 /\2 0 FB4_18 (b) (b)
AUTOCONFIG/dtack 5 2<- /\2 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$38 14: ADDR<23> 27: CFGOUT_n
2: $OpTx$INV$24 15: ADDR<2> 28: IDE/S3_n
3: ADDR<12> 16: ADDR<3> 29: IDE/as_delay<1>
4: ADDR<13> 17: ADDR<4> 30: IDE/ide_enabled
5: ADDR<14> 18: ADDR<5> 31: IDE/rom_bankSel<0>
6: ADDR<16> 19: ADDR<6> 32: DBUS<14>.PIN
7: ADDR<17> 20: ADDR<7> 33: DBUS<13>.PIN
1: $OpTx$FX_DC$41 14: ADDR<23> 27: IDE/S3_n
2: ADDR<12> 15: ADDR<2> 28: IDE/as_delay<1>
3: ADDR<13> 16: ADDR<3> 29: IDE/ide_enabled
4: ADDR<14> 17: ADDR<4> 30: DBUS<15>.PIN
5: ADDR<15> 18: ADDR<5> 31: DBUS<14>.PIN
6: ADDR<16> 19: ADDR<6> 32: DBUS<13>.PIN
7: ADDR<17> 20: ADDR<7> 33: DBUS<12>.PIN
8: ADDR<18> 21: ADDR<8> 34: RESET
9: ADDR<19> 22: AS_n 35: RESET_n
10: ADDR<1> 23: AUTOCONFIG/dtack 36: RW
11: ADDR<20> 24: AUTOCONFIG/ide_base<5> 37: UDS_n
12: ADDR<21> 25: AUTOCONFIG/ide_configured 38: ide_enable
13: ADDR<22> 26: CFGIN_n 39: ide_enable/ide_enable_CLKF
11: ADDR<20> 24: AUTOCONFIG/ide_configured 37: UDS_n
12: ADDR<21> 25: CFGIN_n 38: ide_enable
13: ADDR<22> 26: CFGOUT_n 39: reset_delay<2>/reset_delay<2>_CLKF
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
AUTOCONFIG/dtack .....XXXX.XXXX.......XX..XX......X.XX.X. 16
SLAVE_n .X...XXXX.XXXX.......X.X.XX............. 13
ROM_BANK<0> .....X.......................XX......... 3
IDE2_CS_n<1> X.XXX................................... 4
IOR_n .....................X.....X.......X.... 3
IDE1_CS_n<1> X.XXX................................... 4
AS_n_S4 .....................X.....X.....X....X. 4
IOW_n .....................X.....XX......X.... 4
AUTOCONFIG/ide_base<6>
.....XXXXXXXXXXXXXXXXXX.XXX....X.X.XX.X. 26
AUTOCONFIG/ide_base<5>
.....XXXXXXXXXXXXXXXXXX.XXX.....XX.XX.X. 26
IDE2_CS_n<0> X.XXX................................... 4
DBUS<12> .....XXXXXXXXXXXXXXXXX...XX......XXX.XX. 24
AUTOCONFIG/ide_base<2>
.....XXXXXXXXXXXXXXXXXX.XXX....X.X.XX.X. 26
IDE1_CS_n<0> X.XXX................................... 4
DBUS<13> .....XXXXXXXXXXXXXXXXX...XX......XXX..X. 23
AUTOCONFIG/ide_base<1>
.....XXXXXXXXXXXXXXXXXX.XXX.....XX.XX.X. 26
DBUS<14> .....XXXXXXXXXXXXXXXXX...XX......XXX..X. 23
IDE/as_delay<0> .....................X....X......X....X. 4
SLAVE_n X....XXXX.XXXX.......X..XX.............. 12
AUTOCONFIG/ide_configured
.....XXXXXXXXXXXXXXXXXX.XXX......X.XX.X. 25
.....XXXXXXXXXXXXXXXXXXXXX.......X.XX.X. 25
AUTOCONFIG/ide_base<7>
.....XXXXXXXXXXXXXXXXXXXXX...X...X.XX.X. 26
IOR_n .....................X....X........X.... 3
IDE2_CS_n XXXXXX......................X........... 7
AUTOCONFIG/ide_base<6>
.....XXXXXXXXXXXXXXXXXXXXX....X..X.XX.X. 26
IOW_n .....................X....XX.......X.... 4
AUTOCONFIG/ide_base<5>
.....XXXXXXXXXXXXXXXXXXXXX.....X.X.XX.X. 26
AUTOCONFIG/ide_base<4>
.....XXXXXXXXXXXXXXXXXXXXX......XX.XX.X. 26
AUTOCONFIG/ide_base<3>
.....XXXXXXXXXXXXXXXXXXXXX...X...X.XX.X. 26
DBUS<12> .....XXXXXXXXXXXXXXXXX..XX.......XXX.XX. 24
AUTOCONFIG/ide_base<2>
.....XXXXXXXXXXXXXXXXXXXXX....X..X.XX.X. 26
IDE1_CS_n XXXXXX......................X........... 7
DBUS<13> .....XXXXXXXXXXXXXXXXX..XX.......XXX..X. 23
AUTOCONFIG/ide_base<1>
.....XXXXXXXXXXXXXXXXXXXXX.....X.X.XX.X. 26
DBUS<14> .....XXXXXXXXXXXXXXXXX..XX.......XXX..X. 23
AUTOCONFIG/dtack .....XXXX.XXXX.......XX.XX.......X.XX.X. 16
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$FX_DC$38 = ADDR<16>
# !AUTOCONFIG/ide_configured
# ADDR<15>
$OpTx$FX_DC$41 = !AUTOCONFIG/ide_configured
# CFGOUT_n
;Imported pterms FB3_9
# !IDE/ide_enabled
# ADDR<18> & !AUTOCONFIG/ide_base<2>
# !ADDR<18> & AUTOCONFIG/ide_base<2>
# AUTOCONFIG/ide_base<6> & !ADDR<22>
# !AUTOCONFIG/ide_base<6> & ADDR<22>
;Imported pterms FB3_8
# ADDR<17> & !AUTOCONFIG/ide_base<1>
# !ADDR<17> & AUTOCONFIG/ide_base<1>
# !AUTOCONFIG/ide_base<3> & ADDR<19>
# AUTOCONFIG/ide_base<7> & !ADDR<23>
# !AUTOCONFIG/ide_base<7> & ADDR<23>
;Imported pterms FB3_7
;Imported pterms FB2_8
# ADDR<20> & !AUTOCONFIG/ide_base<4>
# !ADDR<20> & AUTOCONFIG/ide_base<4>
# AUTOCONFIG/ide_base<3> & !ADDR<19>
# AUTOCONFIG/ide_base<5> & !ADDR<21>
# !AUTOCONFIG/ide_base<5> & ADDR<21>;
$OpTx$INV$24 = !AUTOCONFIG/ide_configured
# CFGOUT_n
# ADDR<18> & !AUTOCONFIG/ide_base<2>
# AUTOCONFIG/ide_base<6> & !ADDR<22>
# !AUTOCONFIG/ide_base<5> & ADDR<21>
# !AUTOCONFIG/ide_base<6> & ADDR<22>
;Imported pterms FB3_4
# !ADDR<18> & AUTOCONFIG/ide_base<2>
;Imported pterms FB2_7
# ADDR<17> & !AUTOCONFIG/ide_base<1>
# !ADDR<17> & AUTOCONFIG/ide_base<1>
# AUTOCONFIG/ide_base<7> & !ADDR<23>
# !AUTOCONFIG/ide_base<7> & ADDR<23>
;Imported pterms FB3_6
# ADDR<20> & !AUTOCONFIG/ide_base<4>
# !ADDR<20> & AUTOCONFIG/ide_base<4>
;Imported pterms FB2_10
# ADDR<18> & !AUTOCONFIG/ide_base<2>
# !ADDR<18> & AUTOCONFIG/ide_base<2>
# AUTOCONFIG/ide_base<3> & !ADDR<19>
# !AUTOCONFIG/ide_base<3> & ADDR<19>;
!AS_n_S4.D = !AS_n & !IDE/S3_n;
AS_n_S4.CLK = ide_enable/ide_enable_CLKF;
AS_n_S4.AP = !RESET;
AUTOCONFIG/dtack.D = AUTOCONFIG/dtack & !AS_n
;Imported pterms FB4_1
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & ADDR<23> & ADDR<22> & ADDR<21> &
ADDR<19> & !AS_n & CFGOUT_n
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
!AS_n & CFGOUT_n;
AUTOCONFIG/dtack.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/dtack.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/dtack.AR = !RESET;
AUTOCONFIG/ide_base<1>.D = DBUS<13>.PIN;
AUTOCONFIG/ide_base<1>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<1>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<1>.AR = !RESET;
AUTOCONFIG/ide_base<1>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -471,7 +433,7 @@ AUTOCONFIG/ide_base<1>.D = DBUS<13>.PIN;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_base<2>.D = DBUS<14>.PIN;
AUTOCONFIG/ide_base<2>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<2>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<2>.AR = !RESET;
AUTOCONFIG/ide_base<2>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -479,8 +441,9 @@ AUTOCONFIG/ide_base<2>.D = DBUS<14>.PIN;
ADDR<22> & ADDR<21> & ADDR<19> & !RW & !AS_n & ADDR<6> &
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_base<3>.D = DBUS<15>.PIN;
AUTOCONFIG/ide_base<3>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<3>.D = ;Imported pterms FB4_10
DBUS<15>.PIN;
AUTOCONFIG/ide_base<3>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<3>.AR = !RESET;
AUTOCONFIG/ide_base<3>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -489,7 +452,7 @@ AUTOCONFIG/ide_base<3>.D = DBUS<15>.PIN;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_base<4>.D = DBUS<12>.PIN;
AUTOCONFIG/ide_base<4>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<4>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<4>.AR = !RESET;
AUTOCONFIG/ide_base<4>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -498,7 +461,7 @@ AUTOCONFIG/ide_base<4>.D = DBUS<12>.PIN;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_base<5>.D = DBUS<13>.PIN;
AUTOCONFIG/ide_base<5>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<5>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<5>.AR = !RESET;
AUTOCONFIG/ide_base<5>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -507,7 +470,7 @@ AUTOCONFIG/ide_base<5>.D = DBUS<13>.PIN;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_base<6>.D = DBUS<14>.PIN;
AUTOCONFIG/ide_base<6>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<6>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<6>.AR = !RESET;
AUTOCONFIG/ide_base<6>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -516,7 +479,7 @@ AUTOCONFIG/ide_base<6>.D = DBUS<14>.PIN;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_base<7>.D = DBUS<15>.PIN;
AUTOCONFIG/ide_base<7>.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_base<7>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_base<7>.AR = !RESET;
AUTOCONFIG/ide_base<7>.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -525,7 +488,7 @@ AUTOCONFIG/ide_base<7>.D = DBUS<15>.PIN;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/ide_configured.D = Vcc;
AUTOCONFIG/ide_configured.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/ide_configured.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/ide_configured.AR = !RESET;
AUTOCONFIG/ide_configured.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -534,7 +497,7 @@ AUTOCONFIG/ide_configured.D = Vcc;
ADDR<3> & !AUTOCONFIG/ide_configured & CFGOUT_n;
AUTOCONFIG/shutup.D = Vcc;
AUTOCONFIG/shutup.CLK = ide_enable/ide_enable_CLKF;
AUTOCONFIG/shutup.CLK = reset_delay<2>/reset_delay<2>_CLKF;
AUTOCONFIG/shutup.AR = !RESET;
AUTOCONFIG/shutup.CE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & !UDS_n & !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
@ -553,9 +516,10 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
!ADDR<2> & ADDR<6> & !ADDR<3>
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
ADDR<1> & !ADDR<6> & !ADDR<3>
;Imported pterms FB4_13
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<4> &
!ADDR<2> & !ADDR<1> & !ADDR<6> & !ADDR<3>;
DBUS<12>.CLK = ide_enable/ide_enable_CLKF;
DBUS<12>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
DBUS<12>.AR = !RESET;
DBUS<12>.OE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
@ -571,7 +535,7 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
!ADDR<2> & !ADDR<1> & !ADDR<3>
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
!ADDR<2> & ADDR<6> & !ADDR<3>;
DBUS<13>.CLK = ide_enable/ide_enable_CLKF;
DBUS<13>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
DBUS<13>.AR = !RESET;
DBUS<13>.OE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
@ -590,7 +554,7 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
ADDR<1> & !ADDR<6> & !ADDR<3>
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<4> &
ADDR<2> & !ADDR<1> & !ADDR<6> & !ADDR<3>;
DBUS<14>.CLK = ide_enable/ide_enable_CLKF;
DBUS<14>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
DBUS<14>.AR = !RESET;
DBUS<14>.OE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
@ -604,12 +568,12 @@ CFGOUT_n.D = !AUTOCONFIG/ide_configured & !AUTOCONFIG/shutup;
;Imported pterms FB2_2
# !ADDR<8> & !ADDR<7> & !ADDR<5> & !ADDR<4> &
!ADDR<2> & ADDR<1> & !ADDR<3>
;Imported pterms FB2_4
# !ADDR<8> & !ADDR<7> & ADDR<5> & !ADDR<4> &
ADDR<2> & ADDR<1> & !ADDR<6> & ADDR<3>
;Imported pterms FB2_4
# !ADDR<8> & !ADDR<7> & !ADDR<5> & ADDR<4> &
ADDR<2> & ADDR<1> & !ADDR<6> & !ADDR<3>;
DBUS<15>.CLK = ide_enable/ide_enable_CLKF;
DBUS<15>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
DBUS<15>.AR = !RESET;
DBUS<15>.OE = !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> & RW &
@ -628,12 +592,16 @@ IDE/S3_n.D = AS_n;
IDE/S3_n/IDE/S3_n_CLKF = C1n
$ C3n;
!IDE/as_delay<1>.D = !AS_n & !AS_n_S4;
IDE/as_delay<1>.CLK = ide_enable/ide_enable_CLKF;
!IDE/as_delay<0>.D = !AS_n & !IDE/S3_n;
IDE/as_delay<0>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
IDE/as_delay<0>.AP = !RESET;
!IDE/as_delay<1>.D = !AS_n & !IDE/as_delay<0>;
IDE/as_delay<1>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
IDE/as_delay<1>.AP = !RESET;
!IDE/ide_enabled.D = RW & !IDE/ide_enabled
# !IDE/ide_enabled & !AUTOCONFIG/ide_configured
# !AUTOCONFIG/ide_configured & !IDE/ide_enabled
# !IDE/ide_enabled & CFGOUT_n
;Imported pterms FB3_2
# ADDR<20> & !AUTOCONFIG/ide_base<4> &
@ -659,7 +627,7 @@ IDE/S3_n/IDE/S3_n_CLKF = C1n
!IDE/ide_enabled
;Imported pterms FB3_18
# UDS_n & !IDE/ide_enabled
# !IDE/ide_enabled & IDE/S3_n
# IDE/S3_n & !IDE/ide_enabled
# !IDE/ide_enabled & !ide_enable
# AUTOCONFIG/ide_base<3> & !ADDR<19> &
!IDE/ide_enabled
@ -670,57 +638,21 @@ IDE/S3_n/IDE/S3_n_CLKF = C1n
!IDE/ide_enabled
# !ADDR<17> & AUTOCONFIG/ide_base<1> &
!IDE/ide_enabled;
IDE/ide_enabled.CLK = ide_enable/ide_enable_CLKF;
IDE/ide_enabled.CLK = reset_delay<2>/reset_delay<2>_CLKF;
IDE/ide_enabled.AR = !RESET;
IDE/rom_bankSel<0>.T = !ADDR<16> & !UDS_n & DBUS<14>.PIN &
AUTOCONFIG/ide_base<5> & !IDE/rom_bankSel<0> & ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24
# !ADDR<16> & !UDS_n & DBUS<14>.PIN &
!AUTOCONFIG/ide_base<5> & !IDE/rom_bankSel<0> & !ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24
# !ADDR<16> & !UDS_n & !DBUS<14>.PIN &
AUTOCONFIG/ide_base<5> & IDE/rom_bankSel<0> & ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24
;Imported pterms FB2_10
# !ADDR<16> & !UDS_n & !DBUS<14>.PIN &
!AUTOCONFIG/ide_base<5> & IDE/rom_bankSel<0> & !ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24;
IDE/rom_bankSel<0>.CLK = ide_enable/ide_enable_CLKF;
IDE/rom_bankSel<0>.AR = !RESET;
!IDE1_CS_n = !ADDR<16> & IDE/ide_enabled & !ADDR<15> &
!ADDR<13> & ADDR<12> & !ADDR<14> & !$OpTx$FX_DC$41;
IDE/rom_bankSel<1>.T = !ADDR<16> & !UDS_n & DBUS<15>.PIN &
AUTOCONFIG/ide_base<5> & !IDE/rom_bankSel<1> & ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24
# !ADDR<16> & !UDS_n & DBUS<15>.PIN &
!AUTOCONFIG/ide_base<5> & !IDE/rom_bankSel<1> & !ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24
# !ADDR<16> & !UDS_n & !DBUS<15>.PIN &
AUTOCONFIG/ide_base<5> & IDE/rom_bankSel<1> & ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24
;Imported pterms FB2_8
# !ADDR<16> & !UDS_n & !DBUS<15>.PIN &
!AUTOCONFIG/ide_base<5> & IDE/rom_bankSel<1> & !ADDR<21> & !RW & !IDE/S3_n &
ide_enable & ADDR<15> & !$OpTx$INV$24;
IDE/rom_bankSel<1>.CLK = ide_enable/ide_enable_CLKF;
IDE/rom_bankSel<1>.AR = !RESET;
!IDE1_CS_n<0> = ADDR<12> & !ADDR<13> & !ADDR<14> & !$OpTx$FX_DC$38;
!IDE1_CS_n<1> = ADDR<12> & !ADDR<13> & ADDR<14> & !$OpTx$FX_DC$38;
!IDE2_CS_n<0> = !ADDR<12> & ADDR<13> & !ADDR<14> & !$OpTx$FX_DC$38;
!IDE2_CS_n<1> = !ADDR<12> & ADDR<13> & ADDR<14> & !$OpTx$FX_DC$38;
!IDE2_CS_n = !ADDR<16> & IDE/ide_enabled & !ADDR<15> &
ADDR<13> & !ADDR<12> & !ADDR<14> & !$OpTx$FX_DC$41;
!IDEBUF_OE = !RW
# AUTOCONFIG/ide_base<5> & ADDR<21> & !AS_n &
RESET_n & !AS_n_S4 & BERR_n & !$OpTx$INV$24
# !AUTOCONFIG/ide_base<5> & !ADDR<21> & !AS_n &
RESET_n & !AS_n_S4 & BERR_n & !$OpTx$INV$24
# !AS_n & RESET_n & !IDE/as_delay<0> & BERR_n &
!$OpTx$FX_DC$41
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
!AS_n & RESET_n & !AS_n_S4 & BERR_n & CFGOUT_n;
!AS_n & RESET_n & !IDE/as_delay<0> & BERR_n & CFGOUT_n;
IDE_ROMEN = AS_n
# !AUTOCONFIG/ide_configured
@ -729,24 +661,24 @@ IDE_ROMEN = AS_n
# !AUTOCONFIG/ide_base<3> & ADDR<19>
;Imported pterms FB3_10
# ADDR<20> & !AUTOCONFIG/ide_base<4>
;Imported pterms FB3_12
# !ADDR<20> & AUTOCONFIG/ide_base<4>
# ADDR<17> & !AUTOCONFIG/ide_base<1>
# !ADDR<17> & AUTOCONFIG/ide_base<1>
# AUTOCONFIG/ide_base<5> & !ADDR<21>
# !AUTOCONFIG/ide_base<5> & ADDR<21>
;Imported pterms FB3_13
# ADDR<18> & !AUTOCONFIG/ide_base<2>
# !ADDR<18> & AUTOCONFIG/ide_base<2>
;Imported pterms FB3_9
# AUTOCONFIG/ide_base<6> & !ADDR<22>
# !AUTOCONFIG/ide_base<6> & ADDR<22>
# !AUTOCONFIG/ide_base<7> & ADDR<23>
;Imported pterms FB3_14
# AUTOCONFIG/ide_base<7> & !ADDR<23>
# !ADDR<16> & ADDR<12> & !ADDR<13> &
IDE/ide_enabled
# !ADDR<16> & !ADDR<12> & ADDR<13> &
IDE/ide_enabled;
# !AUTOCONFIG/ide_base<7> & ADDR<23>
# !ADDR<16> & IDE/ide_enabled & !ADDR<13> &
ADDR<12>
;Imported pterms FB3_8
# !ADDR<16> & IDE/ide_enabled & ADDR<13> &
!ADDR<12>
;Imported pterms FB3_12
# ADDR<18> & !AUTOCONFIG/ide_base<2>
# !ADDR<18> & AUTOCONFIG/ide_base<2>
# !ADDR<17> & AUTOCONFIG/ide_base<1>;
!IOR_n = RW & !AS_n & !IDE/S3_n;
@ -758,27 +690,28 @@ OVR_n_1 = Gnd;
OVR_n_2 = Gnd;
OVR_n_2.OE = Gnd;
RESET.D = RESET_n;
RESET.CLK = ide_enable/ide_enable_CLKF;
!RESET.D = !reset_delay<0> & !reset_delay<1> & !reset_delay<2>;
RESET.CLK = reset_delay<2>/reset_delay<2>_CLKF;
ROM_BANK<0> = ADDR<16> & !IDE/ide_enabled
# IDE/rom_bankSel<0> & IDE/ide_enabled;
ROM_BANK<1> = IDE/rom_bankSel<1> & IDE/ide_enabled;
!SLAVE_n = AUTOCONFIG/ide_base<5> & ADDR<21> & !AS_n &
!$OpTx$INV$24
# !AUTOCONFIG/ide_base<5> & !ADDR<21> & !AS_n &
!$OpTx$INV$24
!SLAVE_n = !AS_n & !$OpTx$FX_DC$41
# !CFGIN_n & !ADDR<20> & !ADDR<18> & !ADDR<17> &
!ADDR<16> & ADDR<23> & ADDR<22> & ADDR<21> & ADDR<19> &
!AS_n & CFGOUT_n;
ide_enable.D = IDE_OFF_n;
ide_enable.CLK = ide_enable/ide_enable_CLKF;
ide_enable.CLK = reset_delay<2>/reset_delay<2>_CLKF;
ide_enable.CE = !RESET;
!ide_enable/ide_enable_CLKF = C1n
reset_delay<0>.D = RESET_n;
reset_delay<0>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
reset_delay<1>.D = reset_delay<0>;
reset_delay<1>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
reset_delay<2>.D = reset_delay<1>;
reset_delay<2>.CLK = reset_delay<2>/reset_delay<2>_CLKF;
!reset_delay<2>/reset_delay<2>_CLKF = C1n
$ C3n;
****************************** Device Pin Out *****************************
@ -813,7 +746,7 @@ No. Name No. Name
1 DTACK_n 33 IDE_ROMEN
2 ADDR<23> 34 OVR_n_1
3 VCC 35 OVR_n_2
4 ADDR<21> 36 ROM_BANK<1>
4 ADDR<21> 36 KPR
5 ADDR<22> 37 VCC
6 ADDR<20> 38 C1n
7 ADDR<19> 39 C3n
@ -823,11 +756,11 @@ No. Name No. Name
11 BERR_n 43 SLAVE_n
12 ADDR<15> 44 IOR_n
13 ADDR<14> 45 IOW_n
14 GND 46 ROM_BANK<0>
15 ADDR<13> 47 IDE2_CS_n<1>
16 ADDR<12> 48 IDE2_CS_n<0>
17 KPR 49 IDE1_CS_n<1>
18 KPR 50 IDE1_CS_n<0>
14 GND 46 KPR
15 ADDR<13> 47 KPR
16 ADDR<12> 48 KPR
17 KPR 49 IDE2_CS_n
18 KPR 50 IDE1_CS_n
19 KPR 51 IDE_OFF_n
20 ADDR<1> 52 DBUS<12>
21 GND 53 TDO

734
RTL/RIPPLE.tim
View File

@ -5,17 +5,17 @@ Design: RIPPLE
Device: XC9572XL-10-VQ64
Speed File: Version 3.0
Program: Timing Report Generator: version P.20131013
Date: Thu Apr 18 04:18:38 2024
Date: Wed Aug 7 11:58:23 2024
Performance Summary:
Pad to Pad (tPD) : 24.0ns (2 macrocell levels)
Pad 'ADDR<19>' to Pad 'IDE1_CS_n<0>'
Pad to Pad (tPD) : 23.6ns (2 macrocell levels)
Pad 'ADDR<17>' to Pad 'IDE1_CS_n'
Clock net 'AS_n' path delays:
Clock Pad to Output Pad (tCO) : 30.1ns (3 macrocell levels)
Clock Pad 'AS_n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Clock Pad 'AS_n' to Output Pad 'IDE1_CS_n' (Pterm Clock)
Minimum Clock Period: 14.0ns
Maximum Internal Clock Speed: 71.4Mhz
@ -23,135 +23,116 @@ Clock Pad 'AS_n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Clock net 'C3n' path delays:
Clock Pad to Output Pad (tCO) : 39.6ns (4 macrocell levels)
Clock Pad 'C3n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Clock Pad to Output Pad (tCO) : 39.2ns (4 macrocell levels)
Clock Pad 'C3n' to Output Pad 'IDE1_CS_n' (Pterm Clock)
Clock to Setup (tCYC) : 19.7ns (2 macrocell levels)
Clock to Q, net 'AUTOCONFIG/ide_base<1>.Q' to TFF Setup(D) at 'IDE/rom_bankSel<0>.D'(Pterm Clock)
Target FF drives output net 'IDE/rom_bankSel<0>'
Clock to Setup (tCYC) : 11.4ns (1 macrocell levels)
Clock to Q, net 'AUTOCONFIG/ide_base<1>.Q' to DFF Setup(D) at 'IDE/ide_enabled.D'(Pterm Clock)
Target FF drives output net 'IDE/ide_enabled'
Setup to Clock at the Pad (tSU) : 4.1ns (1 macrocell levels)
Data signal 'ADDR<17>' to TFF D input Pin at 'IDE/rom_bankSel<0>.D'
Setup to Clock at the Pad (tSU) : -4.2ns (0 macrocell levels)
Data signal 'ADDR<17>' to DFF D input Pin at 'IDE/ide_enabled.D'
Clock pad 'C3n' (Pterm Clock)
Minimum Clock Period: 19.7ns
Maximum Internal Clock Speed: 50.7Mhz
(Limited by Cycle Time)
Minimum Clock Period: 14.0ns
Maximum Internal Clock Speed: 71.4Mhz
(Limited by Clock Pulse Width)
Clock net 'C1n' path delays:
Clock Pad to Output Pad (tCO) : 39.6ns (4 macrocell levels)
Clock Pad 'C1n' to Output Pad 'IDE1_CS_n<0>' (Pterm Clock)
Clock Pad to Output Pad (tCO) : 39.2ns (4 macrocell levels)
Clock Pad 'C1n' to Output Pad 'IDE1_CS_n' (Pterm Clock)
Clock to Setup (tCYC) : 19.7ns (2 macrocell levels)
Clock to Q, net 'AUTOCONFIG/ide_base<1>.Q' to TFF Setup(D) at 'IDE/rom_bankSel<0>.D'(Pterm Clock)
Target FF drives output net 'IDE/rom_bankSel<0>'
Clock to Setup (tCYC) : 11.4ns (1 macrocell levels)
Clock to Q, net 'AUTOCONFIG/ide_base<1>.Q' to DFF Setup(D) at 'IDE/ide_enabled.D'(Pterm Clock)
Target FF drives output net 'IDE/ide_enabled'
Setup to Clock at the Pad (tSU) : 4.1ns (1 macrocell levels)
Data signal 'ADDR<17>' to TFF D input Pin at 'IDE/rom_bankSel<0>.D'
Setup to Clock at the Pad (tSU) : -4.2ns (0 macrocell levels)
Data signal 'ADDR<17>' to DFF D input Pin at 'IDE/ide_enabled.D'
Clock pad 'C1n' (Pterm Clock)
Minimum Clock Period: 19.7ns
Maximum Internal Clock Speed: 50.7Mhz
(Limited by Cycle Time)
Minimum Clock Period: 14.0ns
Maximum Internal Clock Speed: 71.4Mhz
(Limited by Clock Pulse Width)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A A A A A A A A A A
\ D D D D D D D D D D D
\ D D D D D D D D D D D
\ R R R R R R R R R R R
\ < < < < < < < < < < <
\ 1 1 1 1 1 1 1 1 2 2 2
\ 2 3 4 5 6 7 8 9 0 1 2
\ > > > > > > > > > > >
\
\
\
\
To \------------------------------------------------------------------
\ From A A A A A A A A A A A
\ D D D D D D D D D D D
\ D D D D D D D D D D D
\ R R R R R R R R R R R
\ < < < < < < < < < < <
\ 1 1 1 1 1 1 1 1 2 2 2
\ 2 3 4 5 6 7 8 9 0 1 2
\ > > > > > > > > > > >
\
To \------------------------------------------------------------------
DBUS<12> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<13> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<14> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<15> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
IDE1_CS_n<0> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDE1_CS_n<1> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDE2_CS_n<0> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDE2_CS_n<1> 14.5 14.5 14.5 22.2 22.2 23.6 23.2 24.0 24.0 24.0 23.2
IDEBUF_OE 14.5 23.2 23.2 23.2 23.2 14.5 22.2
IDE_ROMEN 16.3 16.3 16.3 15.5 15.9 14.5 15.5 15.5 15.9
IOR_n
IOW_n
ROM_BANK<0> 14.5
SLAVE_n 14.5 23.2 23.2 23.2 23.2 14.5 22.2
DBUS<12> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<13> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<14> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
DBUS<15> 11.0 11.0 11.0 11.0 11.0 11.0 11.0
IDE1_CS_n 14.5 14.5 14.5 14.5 14.5 23.6 23.2 23.2 23.2 23.2 23.2
IDE2_CS_n 14.5 14.5 14.5 14.5 14.5 23.6 23.2 23.2 23.2 23.2 23.2
IDEBUF_OE 14.5 23.6 23.2 23.2 23.2 23.2 23.2
IDE_ROMEN 16.3 16.3 16.3 15.5 15.5 15.5 14.5 15.5 15.9
IOR_n
IOW_n
SLAVE_n 14.5 23.6 23.2 23.2 23.2 23.2 23.2
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From A A B C R R
\ D S E F E W
\ D _ R G S
\ R n R I E
\ < _ N T
\ 2 n _ _
\ 3 n n
\ >
\
\
\
\
To \------------------------------------
\ From A A B C R R
\ D S E F E W
\ D _ R G S
\ R n R I E
\ < _ N T
\ 2 n _ _
\ 3 n n
\ >
\
To \------------------------------------
DBUS<12> 11.0 11.0 11.0 11.0
DBUS<13> 11.0 11.0 11.0 11.0
DBUS<14> 11.0 11.0 11.0 11.0
DBUS<15> 11.0 11.0 11.0 11.0
IDE1_CS_n<0> 23.6
IDE1_CS_n<1> 23.6
IDE2_CS_n<0> 23.6
IDE2_CS_n<1> 23.6
IDEBUF_OE 23.2 14.5 14.5 14.5 14.5 14.5
IDE_ROMEN 16.3 14.5
IOR_n 14.5 14.5
IOW_n 14.5 14.5
ROM_BANK<0>
SLAVE_n 23.2 14.5 14.5
DBUS<12> 11.0 11.0 11.0 11.0
DBUS<13> 11.0 11.0 11.0 11.0
DBUS<14> 11.0 11.0 11.0 11.0
DBUS<15> 11.0 11.0 11.0 11.0
IDE1_CS_n 22.2
IDE2_CS_n 22.2
IDEBUF_OE 22.2 14.5 14.5 14.5 14.5 14.5
IDE_ROMEN 15.9 14.5
IOR_n 14.5 14.5
IOW_n 14.5 14.5
SLAVE_n 22.2 14.5 14.5
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From A C C
\ S 1 3
\ _ n n
\ n
\
\
\
\
\
\
\
\
To \------------------
\ From A C C
\ S 1 3
\ _ n n
\ n
\
\
\
\
\
To \------------------
CFGOUT_n 14.7
DBUS<12> 18.9 22.4 22.4
DBUS<13> 18.9 22.4 22.4
DBUS<14> 18.9 22.4 22.4
DBUS<15> 18.9 22.4 22.4
IDE1_CS_n<0> 30.1 39.6 39.6
IDE1_CS_n<1> 30.1 39.6 39.6
IDE2_CS_n<0> 30.1 39.6 39.6
IDE2_CS_n<1> 30.1 39.6 39.6
IDEBUF_OE 30.1 38.8 38.8
IDE_ROMEN 22.4 31.9 31.9
IOR_n 30.1 30.1
IOW_n 30.1 30.1
ROM_BANK<0> 30.1 30.1
ROM_BANK<1> 30.1 30.1
SLAVE_n 30.1 38.8 38.8
CFGOUT_n 14.7
DBUS<12> 18.9 22.4 22.4
DBUS<13> 18.9 22.4 22.4
DBUS<14> 18.9 22.4 22.4
DBUS<15> 18.9 22.4 22.4
IDE1_CS_n 30.1 39.2 39.2
IDE2_CS_n 30.1 39.2 39.2
IDEBUF_OE 30.1 39.2 39.2
IDE_ROMEN 22.4 31.9 31.9
IOR_n 30.1 30.1
IOW_n 30.1 30.1
SLAVE_n 30.1 39.2 39.2
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU or tSUF) (nsec)
@ -167,16 +148,15 @@ SLAVE_n 30.1 38.8 38.8
\
To \------------
ADDR<15> -4.6 -4.6
ADDR<16> -4.6 -4.6
ADDR<17> 4.1 4.1
ADDR<18> 4.1 4.1
ADDR<19> 4.1 4.1
ADDR<17> -4.2 -4.2
ADDR<18> -4.2 -4.2
ADDR<19> -4.6 -4.6
ADDR<1> -4.6 -4.6
ADDR<20> 4.1 4.1
ADDR<20> -4.6 -4.6
ADDR<21> -4.6 -4.6
ADDR<22> 3.1 3.1
ADDR<23> 4.1 4.1
ADDR<22> -4.2 -4.2
ADDR<23> -4.2 -4.2
ADDR<2> -4.6 -4.6
ADDR<3> -4.6 -4.6
ADDR<4> -4.6 -4.6
@ -184,11 +164,11 @@ ADDR<5> -4.6 -4.6
ADDR<6> -4.6 -4.6
ADDR<7> -4.6 -4.6
ADDR<8> -4.6 -4.6
AS_n -5.6 -5.6
CFGIN_n -5.6 -5.6
AS_n -4.6 -4.6
CFGIN_n -4.6 -4.6
DBUS<12> -5.6 -5.6
DBUS<13> -5.6 -5.6
DBUS<14> -4.6 -4.6
DBUS<14> -5.6 -5.6
DBUS<15> -4.6 -4.6
IDE_OFF_n -5.6 -5.6
RESET_n -5.6 -5.6
@ -200,312 +180,324 @@ UDS_n -4.6 -4.6
(Clock: C3n)
\ From A A A A A A A A
\ S U U U U U U U
\ _ T T T T T T T
\ n O O O O O O O
\ _ C C C C C C C
\ S O O O O O O O
\ 4 N N N N N N N
\ . F F F F F F F
\ Q I I I I I I I
\ G G G G G G G
\ / / / / / / /
\ d i i i i i i
\ t d d d d d d
\ a e e e e e e
\ c _ _ _ _ _ _
\ k b b b b b b
\ . a a a a a a
\ Q s s s s s s
\ e e e e e e
\ < < < < < <
\ 1 2 3 4 5 6
\ > > > > > >
\ . . . . . .
\ Q Q Q Q Q Q
\ U U U U U U U U
\ T T T T T T T T
\ O O O O O O O O
\ C C C C C C C C
\ O O O O O O O O
\ N N N N N N N N
\ F F F F F F F F
\ I I I I I I I I
\ G G G G G G G G
\ / / / / / / / /
\ d i i i i i i i
\ t d d d d d d d
\ a e e e e e e e
\ c _ _ _ _ _ _ _
\ k b b b b b b b
\ . a a a a a a a
\ Q s s s s s s s
\ e e e e e e e
\ < < < < < < <
\ 1 2 3 4 5 6 7
\ > > > > > > >
\ . . . . . . .
\ Q Q Q Q Q Q Q
\
\
\
\
To \------------------------------------------------
AS_n_S4.D
AUTOCONFIG/dtack.D 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
AUTOCONFIG/dtack.D 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D 10.0
IDE/ide_enabled.D 11.4 11.4 11.0 11.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 19.7 19.7 19.7 11.0 18.7
IDE/rom_bankSel<1>.D 19.7 19.7 19.7 19.7 11.0 18.7
IDE/as_delay<0>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.4 11.4 11.0 11.0 11.0 11.4 11.4
RESET.D
ide_enable.CE
reset_delay<1>.D
reset_delay<2>.D
reset_delay<3>.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C3n)
\ From A A A I I I I R
\ U U U D D D D E
\ T T T E E E E S
\ O O O / / / / E
\ C C C S i r r T
\ O O O 3 d o o .
\ N N N _ e m m Q
\ F F F n _ _ _
\ I I I . e b b
\ G G G Q n a a
\ / / / a n n
\ i i s b k k
\ d d h l S S
\ e e u e e e
\ _ _ t d l l
\ b c u . < <
\ a o p Q 0 1
\ s n . > >
\ e f Q . .
\ < i Q Q
\ 7 g
\ > u
\ . r
\ Q e
\ d
\ .
\ Q
\ From A A I I I R i r
\ U U D D D E d e
\ T T E E E S e s
\ O O / / / E _ e
\ C C S a i T e t
\ O O 3 s d . n _
\ N N _ _ e Q a d
\ F F n d _ b e
\ I I . e e l l
\ G G Q l n e a
\ / / a a . y
\ i s y b Q <
\ d h < l 0
\ e u 0 e >
\ _ t > d .
\ c u . . Q
\ o p Q Q
\ n .
\ f Q
\ i
\ g
\ u
\ r
\ e
\ d
\ .
\ Q
\
To \------------------------------------------------
AS_n_S4.D 10.0
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.4 10.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 18.7 11.0 11.0
IDE/rom_bankSel<1>.D 19.7 18.7 11.0 11.0
ide_enable.CE 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D 10.0
IDE/as_delay<0>.D 10.0
IDE/as_delay<1>.D 10.0
IDE/ide_enabled.D 10.0 11.0 11.4 11.0
RESET.D 10.0
ide_enable.CE 10.0
reset_delay<1>.D 10.0
reset_delay<2>.D
reset_delay<3>.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C3n)
\ From i
\ d
\ e
\ _
\ e
\ n
\ a
\ b
\ l
\ e
\ .
\ Q
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
To \------
\ From r r r
\ e e e
\ s s s
\ e e e
\ t t t
\ _ _ _
\ d d d
\ e e e
\ l l l
\ a a a
\ y y y
\ < < <
\ 1 2 3
\ > > >
\ . . .
\ Q Q Q
\
\
\
\
\
\
\
\
\
\
\
\
To \------------------
AS_n_S4.D
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE
AUTOCONFIG/ide_base<2>.CE
AUTOCONFIG/ide_base<3>.CE
AUTOCONFIG/ide_base<4>.CE
AUTOCONFIG/ide_base<5>.CE
AUTOCONFIG/ide_base<6>.CE
AUTOCONFIG/ide_base<7>.CE
AUTOCONFIG/ide_configured.CE
AUTOCONFIG/shutup.CE
DBUS<12>.D 10.0
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.0
IDE/rom_bankSel<0>.D 11.0
IDE/rom_bankSel<1>.D 11.0
ide_enable.CE
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE
AUTOCONFIG/ide_base<2>.CE
AUTOCONFIG/ide_base<3>.CE
AUTOCONFIG/ide_base<4>.CE
AUTOCONFIG/ide_base<5>.CE
AUTOCONFIG/ide_base<6>.CE
AUTOCONFIG/ide_base<7>.CE
AUTOCONFIG/ide_configured.CE
AUTOCONFIG/shutup.CE
DBUS<12>.D
IDE/as_delay<0>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D
RESET.D 10.0 10.0 10.0
ide_enable.CE
reset_delay<1>.D
reset_delay<2>.D 10.0
reset_delay<3>.D 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C1n)
\ From A A A A A A A A
\ S U U U U U U U
\ _ T T T T T T T
\ n O O O O O O O
\ _ C C C C C C C
\ S O O O O O O O
\ 4 N N N N N N N
\ . F F F F F F F
\ Q I I I I I I I
\ G G G G G G G
\ / / / / / / /
\ d i i i i i i
\ t d d d d d d
\ a e e e e e e
\ c _ _ _ _ _ _
\ k b b b b b b
\ . a a a a a a
\ Q s s s s s s
\ e e e e e e
\ < < < < < <
\ 1 2 3 4 5 6
\ > > > > > >
\ . . . . . .
\ Q Q Q Q Q Q
\ U U U U U U U U
\ T T T T T T T T
\ O O O O O O O O
\ C C C C C C C C
\ O O O O O O O O
\ N N N N N N N N
\ F F F F F F F F
\ I I I I I I I I
\ G G G G G G G G
\ / / / / / / / /
\ d i i i i i i i
\ t d d d d d d d
\ a e e e e e e e
\ c _ _ _ _ _ _ _
\ k b b b b b b b
\ . a a a a a a a
\ Q s s s s s s s
\ e e e e e e e
\ < < < < < < <
\ 1 2 3 4 5 6 7
\ > > > > > > >
\ . . . . . . .
\ Q Q Q Q Q Q Q
\
\
\
\
To \------------------------------------------------
AS_n_S4.D
AUTOCONFIG/dtack.D 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
AUTOCONFIG/dtack.D 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D 10.0
IDE/ide_enabled.D 11.4 11.4 11.0 11.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 19.7 19.7 19.7 11.0 18.7
IDE/rom_bankSel<1>.D 19.7 19.7 19.7 19.7 11.0 18.7
IDE/as_delay<0>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.4 11.4 11.0 11.0 11.0 11.4 11.4
RESET.D
ide_enable.CE
reset_delay<1>.D
reset_delay<2>.D
reset_delay<3>.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C1n)
\ From A A A I I I I R
\ U U U D D D D E
\ T T T E E E E S
\ O O O / / / / E
\ C C C S i r r T
\ O O O 3 d o o .
\ N N N _ e m m Q
\ F F F n _ _ _
\ I I I . e b b
\ G G G Q n a a
\ / / / a n n
\ i i s b k k
\ d d h l S S
\ e e u e e e
\ _ _ t d l l
\ b c u . < <
\ a o p Q 0 1
\ s n . > >
\ e f Q . .
\ < i Q Q
\ 7 g
\ > u
\ . r
\ Q e
\ d
\ .
\ Q
\ From A A I I I R i r
\ U U D D D E d e
\ T T E E E S e s
\ O O / / / E _ e
\ C C S a i T e t
\ O O 3 s d . n _
\ N N _ _ e Q a d
\ F F n d _ b e
\ I I . e e l l
\ G G Q l n e a
\ / / a a . y
\ i s y b Q <
\ d h < l 0
\ e u 0 e >
\ _ t > d .
\ c u . . Q
\ o p Q Q
\ n .
\ f Q
\ i
\ g
\ u
\ r
\ e
\ d
\ .
\ Q
\
To \------------------------------------------------
AS_n_S4.D 10.0
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.4 10.0 11.0 11.4
IDE/rom_bankSel<0>.D 19.7 18.7 11.0 11.0
IDE/rom_bankSel<1>.D 19.7 18.7 11.0 11.0
ide_enable.CE 10.0
AUTOCONFIG/ide_base<1>.CE 10.0
AUTOCONFIG/ide_base<2>.CE 10.0
AUTOCONFIG/ide_base<3>.CE 10.0
AUTOCONFIG/ide_base<4>.CE 10.0
AUTOCONFIG/ide_base<5>.CE 10.0
AUTOCONFIG/ide_base<6>.CE 10.0
AUTOCONFIG/ide_base<7>.CE 10.0
AUTOCONFIG/ide_configured.CE 10.0
AUTOCONFIG/shutup.CE 10.0
DBUS<12>.D 10.0
IDE/as_delay<0>.D 10.0
IDE/as_delay<1>.D 10.0
IDE/ide_enabled.D 10.0 11.0 11.4 11.0
RESET.D 10.0
ide_enable.CE 10.0
reset_delay<1>.D 10.0
reset_delay<2>.D
reset_delay<3>.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: C1n)
\ From i
\ d
\ e
\ _
\ e
\ n
\ a
\ b
\ l
\ e
\ .
\ Q
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
To \------
\ From r r r
\ e e e
\ s s s
\ e e e
\ t t t
\ _ _ _
\ d d d
\ e e e
\ l l l
\ a a a
\ y y y
\ < < <
\ 1 2 3
\ > > >
\ . . .
\ Q Q Q
\
\
\
\
\
\
\
\
\
\
\
\
To \------------------
AS_n_S4.D
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE
AUTOCONFIG/ide_base<2>.CE
AUTOCONFIG/ide_base<3>.CE
AUTOCONFIG/ide_base<4>.CE
AUTOCONFIG/ide_base<5>.CE
AUTOCONFIG/ide_base<6>.CE
AUTOCONFIG/ide_base<7>.CE
AUTOCONFIG/ide_configured.CE
AUTOCONFIG/shutup.CE
DBUS<12>.D 10.0
IDE/as_delay<1>.D
IDE/ide_enabled.D 11.0
IDE/rom_bankSel<0>.D 11.0
IDE/rom_bankSel<1>.D 11.0
ide_enable.CE
AUTOCONFIG/dtack.D
AUTOCONFIG/ide_base<1>.CE
AUTOCONFIG/ide_base<2>.CE
AUTOCONFIG/ide_base<3>.CE
AUTOCONFIG/ide_base<4>.CE
AUTOCONFIG/ide_base<5>.CE
AUTOCONFIG/ide_base<6>.CE
AUTOCONFIG/ide_base<7>.CE
AUTOCONFIG/ide_configured.CE
AUTOCONFIG/shutup.CE
DBUS<12>.D
IDE/as_delay<0>.D
IDE/as_delay<1>.D
IDE/ide_enabled.D
RESET.D 10.0 10.0 10.0
ide_enable.CE
reset_delay<1>.D
reset_delay<2>.D 10.0
reset_delay<3>.D 10.0
Path Type Definition:

101
RTL/RIPPLE.ucf
View File

@ -1,52 +1,49 @@
NET "ADDR<1>" LOC = "P20";
NET "ADDR<2>" LOC = "P23";
NET "ADDR<3>" LOC = "P25";
NET "ADDR<4>" LOC = "P31";
NET "ADDR<5>" LOC = "P32";
NET "ADDR<6>" LOC = "P27";
NET "ADDR<7>" LOC = "P24";
NET "ADDR<8>" LOC = "P22";
NET "ADDR<9>" LOC = "P19";
NET "ADDR<10>" LOC = "P18";
NET "ADDR<11>" LOC = "P17";
NET "ADDR<12>" LOC = "P16";
NET "ADDR<13>" LOC = "P15";
NET "ADDR<14>" LOC = "P13";
NET "ADDR<15>" LOC = "P12";
NET "ADDR<16>" LOC = "P10";
NET "ADDR<17>" LOC = "P9";
NET "ADDR<18>" LOC = "P8";
NET "ADDR<19>" LOC = "P7";
NET "ADDR<20>" LOC = "P6";
NET "ADDR<21>" LOC = "P4";
NET "ADDR<22>" LOC = "P5";
NET "ADDR<23>" LOC = "P2";
NET "DBUS<12>" LOC = "P52";
NET "DBUS<13>" LOC = "P56";
NET "DBUS<14>" LOC = "P57";
NET "DBUS<15>" LOC = "P58";
NET "BERR_n" LOC = "P11";
NET "UDS_n" LOC = "P61";
NET "LDS_n" LOC = "P62";
NET "RW" LOC = "P63";
NET "AS_n" LOC = "P60";
NET "RESET_n" LOC = "P64";
NET "C1n" LOC = "P38";
NET "C3n" LOC = "P39";
NET "CFGIN_n" LOC = "P40";
NET "CFGOUT_n" LOC = "P42";
NET "OVR_n_1" LOC = "P34";
NET "OVR_n_2" LOC = "P35";
NET "DTACK_n" LOC = "P1";
NET "IDE_OFF_n" LOC = "P51";
NET "IOR_n" LOC = "P44";
NET "IOW_n" LOC = "P45";
NET "IDE1_CS_n<0>" LOC = "P50";
NET "IDE1_CS_n<1>" LOC = "P49";
NET "IDE2_CS_n<0>" LOC = "P48";
NET "IDE2_CS_n<1>" LOC = "P47";
NET "IDEBUF_OE" LOC = "P59";
NET "IDE_ROMEN" LOC = "P33";
NET "SLAVE_n" LOC = "P43";
NET "ROM_BANK<0>" LOC = "P46";
NET "ROM_BANK<1>" LOC = "P36";
NET "ADDR<1>" LOC = "P20";
NET "ADDR<2>" LOC = "P23";
NET "ADDR<3>" LOC = "P25";
NET "ADDR<4>" LOC = "P31";
NET "ADDR<5>" LOC = "P32";
NET "ADDR<6>" LOC = "P27";
NET "ADDR<7>" LOC = "P24";
NET "ADDR<8>" LOC = "P22";
NET "ADDR<9>" LOC = "P19";
NET "ADDR<10>" LOC = "P18";
NET "ADDR<11>" LOC = "P17";
NET "ADDR<12>" LOC = "P16";
NET "ADDR<13>" LOC = "P15";
NET "ADDR<14>" LOC = "P13";
NET "ADDR<15>" LOC = "P12";
NET "ADDR<16>" LOC = "P10";
NET "ADDR<17>" LOC = "P9";
NET "ADDR<18>" LOC = "P8";
NET "ADDR<19>" LOC = "P7";
NET "ADDR<20>" LOC = "P6";
NET "ADDR<21>" LOC = "P4";
NET "ADDR<22>" LOC = "P5";
NET "ADDR<23>" LOC = "P2";
NET "DBUS<12>" LOC = "P52";
NET "DBUS<13>" LOC = "P56";
NET "DBUS<14>" LOC = "P57";
NET "DBUS<15>" LOC = "P58";
NET "BERR_n" LOC = "P11";
NET "UDS_n" LOC = "P61";
NET "LDS_n" LOC = "P62";
NET "RW" LOC = "P63";
NET "AS_n" LOC = "P60";
NET "RESET_n" LOC = "P64";
NET "C1n" LOC = "P38";
NET "C3n" LOC = "P39";
NET "CDACn" LOC = "P36";
NET "CFGIN_n" LOC = "P40";
NET "CFGOUT_n" LOC = "P42";
NET "OVR_n_1" LOC = "P34";
NET "OVR_n_2" LOC = "P35";
NET "DTACK_n" LOC = "P1";
NET "IDE_OFF_n" LOC = "P51";
NET "IOR_n" LOC = "P44";
NET "IOW_n" LOC = "P45";
NET "IDE1_CS_n" LOC = "P50";
NET "IDE2_CS_n" LOC = "P49";
NET "IDEBUF_OE" LOC = "P59";
NET "IDE_ROMEN" LOC = "P33";
NET "SLAVE_n" LOC = "P43";

17
RTL/top.v
View File

@ -22,6 +22,7 @@ module RIPPLE(
input BERR_n,
input C1n,
input C3n,
input CDACn,
input CFGIN_n,
inout [15:12] DBUS,
input LDS_n,
@ -35,11 +36,10 @@ module RIPPLE(
output SLAVE_n,
// IDE stuff
input IDE_OFF_n,
output [1:0] ROM_BANK,
output IDE_ROMEN,
output IDEBUF_OE,
output [1:0] IDE1_CS_n,
output [1:0] IDE2_CS_n,
output IDE1_CS_n,
output IDE2_CS_n,
output IOR_n,
output IOW_n
);
@ -53,8 +53,14 @@ wire CLK7M = !(C1n ^ C3n);
reg RESET = 0;
reg [2:0] reset_delay;
always @(posedge CLK7M) begin
RESET <= RESET_n;
reset_delay <= {reset_delay[1:0], RESET_n};
if (reset_delay == 'b0) begin
RESET <= 1'b0;
end else begin
RESET <= 1'b1;
end
end
reg ide_enable;
@ -98,8 +104,7 @@ IDE IDE (
.IOW_n (IOW_n),
.IDE1_CS_n (IDE1_CS_n),
.IDE2_CS_n (IDE2_CS_n),
.IDE_ROMEN (IDE_ROMEN),
.ROM_BANK (ROM_BANK)
.IDE_ROMEN (IDE_ROMEN)
);
assign DBUS[15:12] = (autoconfig_cycle) && RW && RESET_n ? autoconfig_dout : 'bZ;