mirror of
https://github.com/LIV2/RIDE.git
synced 2025-12-06 04:22:43 +00:00
1352 lines
87 KiB
Plaintext
1352 lines
87 KiB
Plaintext
Performance Summary Report
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--------------------------
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Design: RIDE
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Device: XC95144XL-10-TQ100
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Speed File: Version 3.0
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Program: Timing Report Generator: version P.20131013
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Date: Thu Jan 2 04:37:05 2025
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Performance Summary:
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Pad to Pad (tPD) : 34.1ns (4 macrocell levels)
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Pad 'ADDR<19>' to Pad 'DBUS<13>'
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Clock net 'RESET_n' path delays:
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Clock Pad to Output Pad (tCO) : 31.1ns (3 macrocell levels)
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Clock Pad 'RESET_n' to Output Pad 'RAMOE_n' (Pterm Clock)
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Setup to Clock at the Pad (tSU) : 2.1ns (0 macrocell levels)
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Data signal 'OVR_n' to DFF D input Pin at 'ovr_detect.D'
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Clock pad 'RESET_n' (Pterm Clock)
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Minimum Clock Period: 14.0ns
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Maximum Internal Clock Speed: 71.4Mhz
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(Limited by Clock Pulse Width)
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Clock net 'as_n_sync<1>.Q' path delays:
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Setup to Clock at the Pad (tSU) : 0.4ns (0 macrocell levels)
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Data signal 'CFGIN_n' to DFF D input Pin at 'AUTOCONFIG/cfgin.D'
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Clock pad 'as_n_sync<1>.Q' (Pterm Clock)
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Minimum Clock Period: 14.0ns
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Maximum Internal Clock Speed: 71.4Mhz
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(Limited by Clock Pulse Width)
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Clock net 'ECLK' path delays:
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Clock to Setup (tCYC) : 10.0ns (1 macrocell levels)
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Clock to Q, net 'SDRAM/refresh_timer<0>.Q' to TFF Setup(D) at 'SDRAM/refresh_timer<0>.D'(Pterm Clock)
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Target FF drives output net 'SDRAM/refresh_timer<0>'
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Minimum Clock Period: 14.0ns
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Maximum Internal Clock Speed: 71.4Mhz
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(Limited by Clock Pulse Width)
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Clock net 'MEMCLK' path delays:
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Clock Pad to Output Pad (tCO) : 37.8ns (5 macrocell levels)
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Clock Pad 'MEMCLK' to Output Pad 'DBUS<13>' (GCK)
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Clock to Setup (tCYC) : 41.8ns (5 macrocell levels)
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Clock to Q, net 'SDRAM/ram_state_FSM_FFd1.Q' to DFF Setup(D) at 'SDRAM/ram_state_FSM_FFd2.D' (GCK)
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Target FF drives output net 'SDRAM/ram_state_FSM_FFd2'
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Setup to Clock at the Pad (tSU) : 37.3ns (4 macrocell levels)
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Data signal 'ADDR<19>' to DFF D input Pin at 'ideregister_dout<0>.D'
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Clock pad 'MEMCLK' (GCK)
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Minimum Clock Period: 41.8ns
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Maximum Internal Clock Speed: 23.9Mhz
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(Limited by Cycle Time)
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--------------------------------------------------------------------------------
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Pad to Pad (tPD) (nsec)
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\ From A A A A A A A A A A A
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\ D D D D D D D D D D D
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\ D D D D D D D D D D D
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\ R R R R R R R R R R R
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\ < < < < < < < < < < <
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\ 1 1 1 1 1 1 1 2 2 2 2
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\ 2 3 5 6 7 8 9 0 1 2 3
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\ > > > > > > > > > > >
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\
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\
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\
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To \------------------------------------------------------------------
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DBUS<12> 18.7 26.4 26.4 26.4 34.1 26.4 26.4 26.4 26.4
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DBUS<13> 18.7 26.4 26.4 26.4 34.1 26.4 26.4 26.4 26.4
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DBUS<14> 18.7 26.4 26.4 26.4 34.1 26.4 26.4 26.4 26.4
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DBUS<15> 18.7 26.4 26.4 26.4 34.1 26.4 26.4 26.4 26.4
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DTACK_n 19.7 19.7 27.4 27.4 19.7 19.7 19.7
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IDEBUF_OE 14.5 14.5 22.2 22.2 29.9 22.2 22.2 22.2 22.2
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IDECS1_n 14.5 14.5 14.5 14.5 22.2 22.2 29.9 22.2 22.2 22.2 22.2
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IDECS2_n 14.5 14.5 14.5 14.5 22.2 22.2 29.9 22.2 22.2 22.2 22.2
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IDE_ROMEN 14.5 22.2 22.2 29.9 22.2 22.2 22.2 22.2
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OVR_n 19.7 19.7 27.4 27.4 19.7 19.7 19.7
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RAMOE_n 23.2 23.2 30.9 30.9 23.2 23.2 23.2
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ROM_BANK<0> 14.5
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--------------------------------------------------------------------------------
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Pad to Pad (tPD) (nsec)
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\ From A L R R U
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\ S D E W D
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\ _ S S S
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\ n _ E _
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\ n T n
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\ _
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\ n
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\
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\
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\
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\
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To \------------------------------
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DBUS<12> 11.0 11.0
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DBUS<13> 11.0 11.0
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DBUS<14> 11.0 11.0
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DBUS<15> 11.0 11.0
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DTACK_n 11.0
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IDEBUF_OE 14.5 14.5 14.5
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IDECS1_n
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IDECS2_n
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IDE_ROMEN
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OVR_n
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RAMOE_n 14.5 14.5 14.5 14.5
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ROM_BANK<0>
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--------------------------------------------------------------------------------
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Clock Pad to Output Pad (tCO) (nsec)
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\ From M R
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\ E E
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\ M S
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\ C E
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\ L T
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\ K _
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\ n
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\
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\
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\
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\
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To \------------
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BA<0> 10.3
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BA<1> 10.3
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CAS_n 10.3
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CFGOUT_n 18.2
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CKE 10.3
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DBUS<12> 37.8
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DBUS<13> 37.8
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DBUS<14> 37.8
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DBUS<15> 37.8
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DQMH 10.3
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DQML 10.3
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DTACK_n 23.2 27.6
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IDEBUF_OE 33.4
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IDECS1_n 33.4
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IDECS2_n 33.4
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IDE_ROMEN 33.4
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IOR_n 10.3
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IOW_n 10.3
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MA<0> 10.3
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MA<10> 10.3
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MA<11> 10.3
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MA<1> 10.3
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MA<2> 10.3
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MA<3> 10.3
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MA<4> 10.3
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MA<5> 10.3
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MA<6> 10.3
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MA<7> 10.3
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MA<8> 10.3
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MA<9> 10.3
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MEMW_n 10.3
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OVR_n 23.2 27.6
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RAMCS_n 10.3
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RAMOE_n 26.7 31.1
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RAS_n 10.3
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ROM_BANK<0> 18.0
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ROM_BANK<1> 18.0
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--------------------------------------------------------------------------------
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Setup to Clock at Pad (tSU or tSUF) (nsec)
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\ From M R
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\ E E
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\ M S
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\ C E
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\ L T
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\ K _
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\ n
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\
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\
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\
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\
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To \------------
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ADDR<10> 6.5
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ADDR<11> 6.5
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ADDR<12> 6.5
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ADDR<13> 6.5
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ADDR<14> 6.5
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ADDR<15> 21.9
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ADDR<16> 21.9
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ADDR<17> 29.6
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ADDR<18> 29.6
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ADDR<19> 37.3
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ADDR<1> 14.2
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ADDR<20> 31.6
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ADDR<21> 29.6
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ADDR<22> 29.6
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ADDR<23> 29.6
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ADDR<2> 7.5
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ADDR<3> 14.2
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ADDR<4> 14.2
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ADDR<5> 14.2
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ADDR<6> 14.2
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ADDR<7> 14.2
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ADDR<8> 14.2
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ADDR<9> 6.5
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AS_n 6.5
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DBUS<12> 6.5
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DBUS<13> 6.5
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DBUS<14> 6.5
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DBUS<15> 6.5
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IDE_ENABLE 7.5
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LDS_n 6.5
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OVR_n 2.1
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RAM_SIZE<0> 14.2
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RAM_SIZE<1> 14.2
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RESET_n 14.2
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RW 21.9
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UDS_n 6.5
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: ECLK)
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\ From S S S S
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\ D D D D
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\ R R R R
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\ A A A A
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\ M M M M
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\ / / / /
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\ r r r r
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\ e e e e
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\ f f f f
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\ r r r r
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\ e e e e
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\ s s s s
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\ h h h h
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\ _ _ _ _
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\ t t t t
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\ i i i i
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\ m m m m
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\ e e e e
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\ r r r r
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\ < < < <
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\ 0 1 2 3
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\ > > > >
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\ . . . .
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\ Q Q Q Q
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To \------------------------
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SDRAM/refresh_timer<0>.D 10.0 10.0 10.0 10.0
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SDRAM/refresh_timer<1>.D 10.0 10.0 10.0 10.0
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SDRAM/refresh_timer<2>.D 10.0 10.0 10.0 10.0
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SDRAM/refresh_timer<3>.D 10.0 10.0 10.0 10.0
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: MEMCLK)
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\ From A A A A A A A A
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\ U U U U U U U U
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\ T T T T T T T T
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\ O O O O O O O O
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\ C C C C C C C C
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\ O O O O O O O O
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\ N N N N N N N N
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\ F F F F F F F F
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\ I I I I I I I I
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\ G G G G G G G G
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\ / / / / / / / /
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\ a a a a a a i i
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\ c c d d d d d d
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\ _ _ d d d d e e
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\ s s r r r r _ _
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\ t t _ _ _ _ b b
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\ a a m m m m a a
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\ t t a a a a s s
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\ e e t t t t e e
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\ < < c c c c < <
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\ 0 1 h h h h 0 1
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\ > > < < < < > >
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\ . . 0 1 2 3 . .
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\ Q Q > > > > Q Q
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\ . . . .
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\ Q Q Q Q
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\
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\
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To \------------------------------------------------
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AUTOCONFIG/ac_state<0>.D 10.0
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AUTOCONFIG/ac_state<1>.D 10.0 10.0
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AUTOCONFIG/addr_match<0>.CE 10.0 10.0
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AUTOCONFIG/addr_match<0>.D 10.0
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AUTOCONFIG/addr_match<1>.CE 10.0 10.0
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AUTOCONFIG/addr_match<1>.D 10.0
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AUTOCONFIG/addr_match<2>.CE 10.0 10.0
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AUTOCONFIG/addr_match<2>.D 10.0
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AUTOCONFIG/addr_match<3>.CE 10.0 10.0
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AUTOCONFIG/addr_match<3>.D 10.0
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AUTOCONFIG/ide_base<0>.CE 10.0 10.0
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AUTOCONFIG/ide_base<1>.CE 10.0 10.0
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AUTOCONFIG/ide_base<2>.CE 10.0 10.0
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AUTOCONFIG/ide_configured.CE 10.0 10.0
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AUTOCONFIG/ram_configured.CE 10.0 10.0
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BA<0>.CE
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BA<0>.D
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BA<1>.CE
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BA<1>.D
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CAS_n.D
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CKE.CE
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CKE.D
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DQMH.D
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DQML.D
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IDE/ds_delay<0>.D
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IDE/ds_delay<1>.D
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IDE/ds_delay<2>.D
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IDE/rom_bankSel<0>.D 25.4 25.4
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IDE/rom_bankSel<1>.D 25.4 25.4
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IOR_n.D
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IOW_n.CE
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IOW_n.D
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MA<0>.D
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MA<10>.D
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MA<11>.D
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MA<1>.D
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MA<2>.D
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MA<3>.D
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MA<4>.D
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MA<5>.D
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MA<6>.D
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MA<7>.D
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MA<8>.D
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MA<9>.D
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MEMW_n.D
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RAMCS_n.D
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RAS_n.D
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SDRAM/init_refreshed.CE
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SDRAM/ram_state_FSM_FFd1.D 25.4 25.4 25.4 25.4
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SDRAM/ram_state_FSM_FFd2.D 26.4 26.4 26.4 26.4
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SDRAM/ram_state_FSM_FFd3.D 26.4 26.4 26.4 26.4
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SDRAM/ram_state_FSM_FFd4.D 26.4 26.4 26.4 26.4
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SDRAM/refresh_request<1>.D
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SDRAM/refreshing.D
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SDRAM/timer_tRFC<0>.D
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SDRAM/timer_tRFC<1>.D
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as_n_sync<1>.D
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autoconf_dtack.D
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autoconfig_dout<0>.CE
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autoconfig_dout<0>.D 11.0 11.0
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autoconfig_dout<1>.CE
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autoconfig_dout<1>.D 11.0 11.0
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autoconfig_dout<2>.CE
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autoconfig_dout<2>.D 11.0 11.0
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D 11.0 11.0
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enable_maprom.D 25.4 25.4
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ide_enabled.D 17.7 17.7
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idereg_dtack.D 17.7 17.7
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ideregister_dout<0>.D 33.1 33.1
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ideregister_dout<1>.D 33.1 33.1
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ideregister_dout<2>.D 33.1 33.1
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ideregister_dout<3>.D 33.1 33.1
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lds_n_sync<1>.D
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otherram_en.D 25.4 25.4
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ovl.CE
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ram_dtack.D
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ram_ready.CE
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rw_sync<1>.D
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uds_n_sync<1>.D
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z2_state_FSM_FFd1.D
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z2_state_FSM_FFd2.D 17.7 17.7 17.7 17.7 25.4 25.4
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--------------------------------------------------------------------------------
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Clock to Setup (tCYC) (nsec)
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(Clock: MEMCLK)
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\ From A A A A A D D I
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\ U U U U U Q Q D
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\ T T T T T M M E
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\ O O O O O H L /
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\ C C C C C . . d
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\ O O O O O Q Q s
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\ N N N N N _
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\ F F F F F d
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\ I I I I I e
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\ G G G G G l
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\ / / / / / a
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\ i i r z z y
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\ d d a r r <
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\ e e m a a 0
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\ _ _ _ m m >
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\ b c c _ _ .
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\ a o o s s Q
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\ s n n i i
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\ e f f z z
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\ < i i e e
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\ 2 g g < <
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\ > u u 0 2
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\ . r r > >
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\ Q e e . .
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\ d d Q Q
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\ . .
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\ Q Q
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\
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To \------------------------------------------------
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AUTOCONFIG/ac_state<0>.D
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AUTOCONFIG/ac_state<1>.D
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AUTOCONFIG/addr_match<0>.CE
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AUTOCONFIG/addr_match<0>.D
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AUTOCONFIG/addr_match<1>.CE
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AUTOCONFIG/addr_match<1>.D
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AUTOCONFIG/addr_match<2>.CE
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AUTOCONFIG/addr_match<2>.D
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AUTOCONFIG/addr_match<3>.CE
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AUTOCONFIG/addr_match<3>.D
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AUTOCONFIG/ide_base<0>.CE
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AUTOCONFIG/ide_base<1>.CE
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AUTOCONFIG/ide_base<2>.CE
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AUTOCONFIG/ide_configured.CE
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AUTOCONFIG/ram_configured.CE
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BA<0>.CE
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BA<0>.D
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BA<1>.CE
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BA<1>.D
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CAS_n.D
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CKE.CE
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CKE.D
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DQMH.D 10.0
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DQML.D 10.0
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IDE/ds_delay<0>.D 10.0
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IDE/ds_delay<1>.D 10.0
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IDE/ds_delay<2>.D 10.0
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IDE/rom_bankSel<0>.D 33.1 25.4
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IDE/rom_bankSel<1>.D 33.1 25.4
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IOR_n.D 10.0
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IOW_n.CE
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IOW_n.D 10.0
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MA<0>.D
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MA<10>.D
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MA<11>.D
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MA<1>.D
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MA<2>.D
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MA<3>.D
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MA<4>.D
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MA<5>.D
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MA<6>.D
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MA<7>.D
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MA<8>.D
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MA<9>.D
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MEMW_n.D
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RAMCS_n.D
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RAS_n.D
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SDRAM/init_refreshed.CE
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SDRAM/ram_state_FSM_FFd1.D 25.4
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SDRAM/ram_state_FSM_FFd2.D 26.4
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SDRAM/ram_state_FSM_FFd3.D 26.4
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SDRAM/ram_state_FSM_FFd4.D 26.4
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SDRAM/refresh_request<1>.D
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SDRAM/refreshing.D
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SDRAM/timer_tRFC<0>.D
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SDRAM/timer_tRFC<1>.D
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as_n_sync<1>.D
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autoconf_dtack.D
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autoconfig_dout<0>.CE
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autoconfig_dout<0>.D 11.0
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autoconfig_dout<1>.CE
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autoconfig_dout<1>.D 11.0
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autoconfig_dout<2>.CE
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autoconfig_dout<2>.D 11.0
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autoconfig_dout<3>.CE
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autoconfig_dout<3>.D
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enable_maprom.D 33.1 25.4
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ide_enabled.D 25.4 17.7
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idereg_dtack.D 25.4 17.7
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ideregister_dout<0>.D 40.8 33.1
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ideregister_dout<1>.D 40.8 33.1
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ideregister_dout<2>.D 40.8 33.1
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ideregister_dout<3>.D 40.8 33.1
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lds_n_sync<1>.D
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otherram_en.D 33.1 25.4
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ovl.CE
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|
ram_dtack.D
|
|
ram_ready.CE
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D
|
|
z2_state_FSM_FFd2.D 33.1 25.4 17.7
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From I I I I I M M M
|
|
\ D D D D O A A A
|
|
\ E E E E R < < <
|
|
\ / / / / _ 0 1 1
|
|
\ d d r r n > 0 1
|
|
\ s s o o . . > >
|
|
\ _ _ m m Q Q . .
|
|
\ d d _ _ Q Q
|
|
\ e e b b
|
|
\ l l a a
|
|
\ a a n n
|
|
\ y y k k
|
|
\ < < S S
|
|
\ 1 2 e e
|
|
\ > > l l
|
|
\ . . < <
|
|
\ Q Q 0 1
|
|
\ > >
|
|
\ . .
|
|
\ Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D
|
|
AUTOCONFIG/ac_state<1>.D
|
|
AUTOCONFIG/addr_match<0>.CE
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE
|
|
AUTOCONFIG/ide_base<1>.CE
|
|
AUTOCONFIG/ide_base<2>.CE
|
|
AUTOCONFIG/ide_configured.CE
|
|
AUTOCONFIG/ram_configured.CE
|
|
BA<0>.CE
|
|
BA<0>.D
|
|
BA<1>.CE
|
|
BA<1>.D
|
|
CAS_n.D
|
|
CKE.CE
|
|
CKE.D
|
|
DQMH.D
|
|
DQML.D
|
|
IDE/ds_delay<0>.D 10.0 10.0
|
|
IDE/ds_delay<1>.D 10.0 10.0
|
|
IDE/ds_delay<2>.D 10.0 10.0
|
|
IDE/rom_bankSel<0>.D 10.0
|
|
IDE/rom_bankSel<1>.D 10.0
|
|
IOR_n.D 10.0 10.0 10.0
|
|
IOW_n.CE
|
|
IOW_n.D 10.0 10.0
|
|
MA<0>.D 10.0
|
|
MA<10>.D 10.0
|
|
MA<11>.D 10.0
|
|
MA<1>.D
|
|
MA<2>.D
|
|
MA<3>.D
|
|
MA<4>.D
|
|
MA<5>.D
|
|
MA<6>.D
|
|
MA<7>.D
|
|
MA<8>.D
|
|
MA<9>.D
|
|
MEMW_n.D
|
|
RAMCS_n.D
|
|
RAS_n.D
|
|
SDRAM/init_refreshed.CE
|
|
SDRAM/ram_state_FSM_FFd1.D
|
|
SDRAM/ram_state_FSM_FFd2.D
|
|
SDRAM/ram_state_FSM_FFd3.D
|
|
SDRAM/ram_state_FSM_FFd4.D
|
|
SDRAM/refresh_request<1>.D
|
|
SDRAM/refreshing.D
|
|
SDRAM/timer_tRFC<0>.D
|
|
SDRAM/timer_tRFC<1>.D
|
|
as_n_sync<1>.D
|
|
autoconf_dtack.D
|
|
autoconfig_dout<0>.CE
|
|
autoconfig_dout<0>.D
|
|
autoconfig_dout<1>.CE
|
|
autoconfig_dout<1>.D
|
|
autoconfig_dout<2>.CE
|
|
autoconfig_dout<2>.D
|
|
autoconfig_dout<3>.CE
|
|
autoconfig_dout<3>.D
|
|
enable_maprom.D
|
|
ide_enabled.D
|
|
idereg_dtack.D
|
|
ideregister_dout<0>.D
|
|
ideregister_dout<1>.D
|
|
ideregister_dout<2>.D 10.0
|
|
ideregister_dout<3>.D 10.0
|
|
lds_n_sync<1>.D
|
|
otherram_en.D
|
|
ovl.CE
|
|
ram_dtack.D
|
|
ram_ready.CE
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D
|
|
z2_state_FSM_FFd2.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From M M M M M M M M
|
|
\ A A A A A A A A
|
|
\ < < < < < < < <
|
|
\ 1 2 3 4 5 6 7 8
|
|
\ > > > > > > > >
|
|
\ . . . . . . . .
|
|
\ Q Q Q Q Q Q Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D
|
|
AUTOCONFIG/ac_state<1>.D
|
|
AUTOCONFIG/addr_match<0>.CE
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE
|
|
AUTOCONFIG/ide_base<1>.CE
|
|
AUTOCONFIG/ide_base<2>.CE
|
|
AUTOCONFIG/ide_configured.CE
|
|
AUTOCONFIG/ram_configured.CE
|
|
BA<0>.CE
|
|
BA<0>.D
|
|
BA<1>.CE
|
|
BA<1>.D
|
|
CAS_n.D
|
|
CKE.CE
|
|
CKE.D
|
|
DQMH.D
|
|
DQML.D
|
|
IDE/ds_delay<0>.D
|
|
IDE/ds_delay<1>.D
|
|
IDE/ds_delay<2>.D
|
|
IDE/rom_bankSel<0>.D
|
|
IDE/rom_bankSel<1>.D
|
|
IOR_n.D
|
|
IOW_n.CE
|
|
IOW_n.D
|
|
MA<0>.D
|
|
MA<10>.D
|
|
MA<11>.D
|
|
MA<1>.D 10.0
|
|
MA<2>.D 10.0
|
|
MA<3>.D 10.0
|
|
MA<4>.D 10.0
|
|
MA<5>.D 10.0
|
|
MA<6>.D 10.0
|
|
MA<7>.D 10.0
|
|
MA<8>.D 10.0
|
|
MA<9>.D
|
|
MEMW_n.D
|
|
RAMCS_n.D
|
|
RAS_n.D
|
|
SDRAM/init_refreshed.CE
|
|
SDRAM/ram_state_FSM_FFd1.D
|
|
SDRAM/ram_state_FSM_FFd2.D
|
|
SDRAM/ram_state_FSM_FFd3.D
|
|
SDRAM/ram_state_FSM_FFd4.D
|
|
SDRAM/refresh_request<1>.D
|
|
SDRAM/refreshing.D
|
|
SDRAM/timer_tRFC<0>.D
|
|
SDRAM/timer_tRFC<1>.D
|
|
as_n_sync<1>.D
|
|
autoconf_dtack.D
|
|
autoconfig_dout<0>.CE
|
|
autoconfig_dout<0>.D
|
|
autoconfig_dout<1>.CE
|
|
autoconfig_dout<1>.D
|
|
autoconfig_dout<2>.CE
|
|
autoconfig_dout<2>.D
|
|
autoconfig_dout<3>.CE
|
|
autoconfig_dout<3>.D
|
|
enable_maprom.D
|
|
ide_enabled.D
|
|
idereg_dtack.D
|
|
ideregister_dout<0>.D
|
|
ideregister_dout<1>.D
|
|
ideregister_dout<2>.D
|
|
ideregister_dout<3>.D
|
|
lds_n_sync<1>.D
|
|
otherram_en.D
|
|
ovl.CE
|
|
ram_dtack.D
|
|
ram_ready.CE
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D
|
|
z2_state_FSM_FFd2.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From M R S S S S S S
|
|
\ A A D D D D D D
|
|
\ < M R R R R R R
|
|
\ 9 C A A A A A A
|
|
\ > S M M M M M M
|
|
\ . _ / / / / / /
|
|
\ Q n i r r r r r
|
|
\ . n a a a a e
|
|
\ Q i m m m m f
|
|
\ t _ _ _ _ r
|
|
\ _ s s s s e
|
|
\ r t t t t s
|
|
\ e a a a a h
|
|
\ f t t t t _
|
|
\ r e e e e r
|
|
\ e _ _ _ _ e
|
|
\ s F F F F q
|
|
\ h S S S S u
|
|
\ e M M M M e
|
|
\ d _ _ _ _ s
|
|
\ . F F F F t
|
|
\ Q F F F F <
|
|
\ d d d d 0
|
|
\ 1 2 3 4 >
|
|
\ . . . . .
|
|
\ Q Q Q Q Q
|
|
\
|
|
\
|
|
To \------------------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D
|
|
AUTOCONFIG/ac_state<1>.D
|
|
AUTOCONFIG/addr_match<0>.CE
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE
|
|
AUTOCONFIG/ide_base<1>.CE
|
|
AUTOCONFIG/ide_base<2>.CE
|
|
AUTOCONFIG/ide_configured.CE
|
|
AUTOCONFIG/ram_configured.CE
|
|
BA<0>.CE 10.0 10.0 10.0
|
|
BA<0>.D
|
|
BA<1>.CE 10.0 10.0 10.0
|
|
BA<1>.D
|
|
CAS_n.D 25.4 25.4 25.4 25.4
|
|
CKE.CE 10.0 10.0 10.0
|
|
CKE.D
|
|
DQMH.D 40.8 40.8 40.8 40.8
|
|
DQML.D 40.8 40.8 40.8 40.8
|
|
IDE/ds_delay<0>.D
|
|
IDE/ds_delay<1>.D
|
|
IDE/ds_delay<2>.D
|
|
IDE/rom_bankSel<0>.D
|
|
IDE/rom_bankSel<1>.D
|
|
IOR_n.D
|
|
IOW_n.CE
|
|
IOW_n.D
|
|
MA<0>.D 40.8 40.8 40.8 40.8
|
|
MA<10>.D 40.8 40.8 40.8 40.8
|
|
MA<11>.D 17.7 17.7 17.7 17.7
|
|
MA<1>.D 40.8 40.8 40.8 40.8
|
|
MA<2>.D 40.8 40.8 40.8 40.8
|
|
MA<3>.D 40.8 40.8 40.8 40.8
|
|
MA<4>.D 40.8 40.8 40.8 40.8
|
|
MA<5>.D 40.8 40.8 40.8 40.8
|
|
MA<6>.D 40.8 40.8 40.8 40.8
|
|
MA<7>.D 40.8 40.8 40.8 40.8
|
|
MA<8>.D 40.8 40.8 40.8 40.8
|
|
MA<9>.D 10.0 17.7 17.7 17.7 17.7
|
|
MEMW_n.D 40.8 40.8 40.8 40.8
|
|
RAMCS_n.D 10.0 25.4 25.4 25.4 25.4
|
|
RAS_n.D 33.1 33.1 33.1 33.1
|
|
SDRAM/init_refreshed.CE 10.0 17.7 17.7 17.7 17.7
|
|
SDRAM/ram_state_FSM_FFd1.D 33.1 33.1 33.1 33.1
|
|
SDRAM/ram_state_FSM_FFd2.D 41.8 41.8 41.8 41.8
|
|
SDRAM/ram_state_FSM_FFd3.D 11.0 34.1 34.1 34.1 34.1
|
|
SDRAM/ram_state_FSM_FFd4.D 41.8 41.8 41.8 41.8
|
|
SDRAM/refresh_request<1>.D 10.0
|
|
SDRAM/refreshing.D 25.4 25.4 25.4 25.4
|
|
SDRAM/timer_tRFC<0>.D 33.1 33.1 33.1 33.1
|
|
SDRAM/timer_tRFC<1>.D 33.1 33.1 33.1 33.1
|
|
as_n_sync<1>.D
|
|
autoconf_dtack.D
|
|
autoconfig_dout<0>.CE
|
|
autoconfig_dout<0>.D
|
|
autoconfig_dout<1>.CE
|
|
autoconfig_dout<1>.D
|
|
autoconfig_dout<2>.CE
|
|
autoconfig_dout<2>.D
|
|
autoconfig_dout<3>.CE
|
|
autoconfig_dout<3>.D
|
|
enable_maprom.D
|
|
ide_enabled.D
|
|
idereg_dtack.D
|
|
ideregister_dout<0>.D
|
|
ideregister_dout<1>.D
|
|
ideregister_dout<2>.D
|
|
ideregister_dout<3>.D
|
|
lds_n_sync<1>.D
|
|
otherram_en.D
|
|
ovl.CE
|
|
ram_dtack.D 10.0 10.0 10.0 10.0
|
|
ram_ready.CE 17.7 17.7 17.7 17.7
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D
|
|
z2_state_FSM_FFd2.D
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From S S S S a a a a
|
|
\ D D D D s s u u
|
|
\ R R R R _ _ t t
|
|
\ A A A A n n o o
|
|
\ M M M M _ _ c c
|
|
\ / / / / s s o o
|
|
\ r r t t y y n n
|
|
\ e e i i n n f f
|
|
\ f f m m c c _ i
|
|
\ r r e e < < d g
|
|
\ e e r r 0 1 t _
|
|
\ s s _ _ > > a d
|
|
\ h h t t . . c o
|
|
\ _ i R R Q Q k u
|
|
\ r n F F . t
|
|
\ e g C C Q <
|
|
\ q . < < 0
|
|
\ u Q 0 1 >
|
|
\ e > > .
|
|
\ s . . Q
|
|
\ t Q Q
|
|
\ <
|
|
\ 1
|
|
\ >
|
|
\ .
|
|
\ Q
|
|
\
|
|
\
|
|
To \------------------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D 17.7
|
|
AUTOCONFIG/ac_state<1>.D 17.7
|
|
AUTOCONFIG/addr_match<0>.CE 10.0
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE 10.0
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE 10.0
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE 10.0
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE 10.0
|
|
AUTOCONFIG/ide_base<1>.CE 10.0
|
|
AUTOCONFIG/ide_base<2>.CE 10.0
|
|
AUTOCONFIG/ide_configured.CE 10.0
|
|
AUTOCONFIG/ram_configured.CE 10.0
|
|
BA<0>.CE
|
|
BA<0>.D
|
|
BA<1>.CE
|
|
BA<1>.D
|
|
CAS_n.D
|
|
CKE.CE
|
|
CKE.D
|
|
DQMH.D
|
|
DQML.D
|
|
IDE/ds_delay<0>.D
|
|
IDE/ds_delay<1>.D
|
|
IDE/ds_delay<2>.D
|
|
IDE/rom_bankSel<0>.D
|
|
IDE/rom_bankSel<1>.D
|
|
IOR_n.D 10.0
|
|
IOW_n.CE 10.0
|
|
IOW_n.D
|
|
MA<0>.D
|
|
MA<10>.D
|
|
MA<11>.D
|
|
MA<1>.D
|
|
MA<2>.D
|
|
MA<3>.D
|
|
MA<4>.D
|
|
MA<5>.D
|
|
MA<6>.D
|
|
MA<7>.D
|
|
MA<8>.D
|
|
MA<9>.D
|
|
MEMW_n.D
|
|
RAMCS_n.D
|
|
RAS_n.D
|
|
SDRAM/init_refreshed.CE 10.0 10.0
|
|
SDRAM/ram_state_FSM_FFd1.D 17.7
|
|
SDRAM/ram_state_FSM_FFd2.D 18.7 26.4 26.4
|
|
SDRAM/ram_state_FSM_FFd3.D 18.7 18.7 18.7
|
|
SDRAM/ram_state_FSM_FFd4.D 18.7 26.4 26.4
|
|
SDRAM/refresh_request<1>.D
|
|
SDRAM/refreshing.D 10.0
|
|
SDRAM/timer_tRFC<0>.D 17.7 17.7
|
|
SDRAM/timer_tRFC<1>.D 17.7 17.7
|
|
as_n_sync<1>.D 10.0
|
|
autoconf_dtack.D 10.0
|
|
autoconfig_dout<0>.CE 10.0
|
|
autoconfig_dout<0>.D 11.0
|
|
autoconfig_dout<1>.CE 10.0
|
|
autoconfig_dout<1>.D
|
|
autoconfig_dout<2>.CE 10.0
|
|
autoconfig_dout<2>.D
|
|
autoconfig_dout<3>.CE 10.0
|
|
autoconfig_dout<3>.D
|
|
enable_maprom.D
|
|
ide_enabled.D
|
|
idereg_dtack.D
|
|
ideregister_dout<0>.D
|
|
ideregister_dout<1>.D
|
|
ideregister_dout<2>.D
|
|
ideregister_dout<3>.D
|
|
lds_n_sync<1>.D
|
|
otherram_en.D
|
|
ovl.CE 10.0
|
|
ram_dtack.D
|
|
ram_ready.CE
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D 10.0
|
|
z2_state_FSM_FFd2.D 10.0 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From a a a e i i i i
|
|
\ u u u n d d d d
|
|
\ t t t a e e e e
|
|
\ o o o b _ r r r
|
|
\ c c c l e e e e
|
|
\ o o o e n g g g
|
|
\ n n n _ a _ i i
|
|
\ f f f m b d s s
|
|
\ i i i a l t t t
|
|
\ g g g p e a e e
|
|
\ _ _ _ r d c r r
|
|
\ d d d o . k _ _
|
|
\ o o o m Q . d d
|
|
\ u u u . Q o o
|
|
\ t t t Q u u
|
|
\ < < < t t
|
|
\ 1 2 3 < <
|
|
\ > > > 0 1
|
|
\ . . . > >
|
|
\ Q Q Q . .
|
|
\ Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D
|
|
AUTOCONFIG/ac_state<1>.D
|
|
AUTOCONFIG/addr_match<0>.CE
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE
|
|
AUTOCONFIG/ide_base<1>.CE
|
|
AUTOCONFIG/ide_base<2>.CE
|
|
AUTOCONFIG/ide_configured.CE
|
|
AUTOCONFIG/ram_configured.CE
|
|
BA<0>.CE
|
|
BA<0>.D
|
|
BA<1>.CE
|
|
BA<1>.D
|
|
CAS_n.D
|
|
CKE.CE
|
|
CKE.D
|
|
DQMH.D
|
|
DQML.D
|
|
IDE/ds_delay<0>.D
|
|
IDE/ds_delay<1>.D
|
|
IDE/ds_delay<2>.D
|
|
IDE/rom_bankSel<0>.D 17.7 17.7
|
|
IDE/rom_bankSel<1>.D 17.7 17.7
|
|
IOR_n.D
|
|
IOW_n.CE
|
|
IOW_n.D
|
|
MA<0>.D
|
|
MA<10>.D
|
|
MA<11>.D
|
|
MA<1>.D
|
|
MA<2>.D
|
|
MA<3>.D
|
|
MA<4>.D
|
|
MA<5>.D
|
|
MA<6>.D
|
|
MA<7>.D
|
|
MA<8>.D
|
|
MA<9>.D
|
|
MEMW_n.D
|
|
RAMCS_n.D
|
|
RAS_n.D
|
|
SDRAM/init_refreshed.CE
|
|
SDRAM/ram_state_FSM_FFd1.D
|
|
SDRAM/ram_state_FSM_FFd2.D
|
|
SDRAM/ram_state_FSM_FFd3.D
|
|
SDRAM/ram_state_FSM_FFd4.D
|
|
SDRAM/refresh_request<1>.D
|
|
SDRAM/refreshing.D
|
|
SDRAM/timer_tRFC<0>.D
|
|
SDRAM/timer_tRFC<1>.D
|
|
as_n_sync<1>.D
|
|
autoconf_dtack.D
|
|
autoconfig_dout<0>.CE
|
|
autoconfig_dout<0>.D
|
|
autoconfig_dout<1>.CE
|
|
autoconfig_dout<1>.D 10.0
|
|
autoconfig_dout<2>.CE
|
|
autoconfig_dout<2>.D 11.0
|
|
autoconfig_dout<3>.CE
|
|
autoconfig_dout<3>.D 11.0
|
|
enable_maprom.D 10.0 17.7 17.7
|
|
ide_enabled.D 10.0
|
|
idereg_dtack.D 10.0 10.0
|
|
ideregister_dout<0>.D 10.0 25.4 25.4 10.0
|
|
ideregister_dout<1>.D 25.4 25.4 10.0
|
|
ideregister_dout<2>.D 25.4 25.4
|
|
ideregister_dout<3>.D 25.4 25.4
|
|
lds_n_sync<1>.D
|
|
otherram_en.D 17.7 17.7
|
|
ovl.CE
|
|
ram_dtack.D
|
|
ram_ready.CE
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D
|
|
z2_state_FSM_FFd2.D 17.7 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From i i l l o o r r
|
|
\ d d d d t v a a
|
|
\ e e s s h l m m
|
|
\ r r _ _ e . _ _
|
|
\ e e n n r Q d r
|
|
\ g g _ _ r t e
|
|
\ i i s s a a a
|
|
\ s s y y m c d
|
|
\ t t n n _ k y
|
|
\ e e c c e . .
|
|
\ r r < < n Q Q
|
|
\ _ _ 0 1 .
|
|
\ d d > > Q
|
|
\ o o . .
|
|
\ u u Q Q
|
|
\ t t
|
|
\ < <
|
|
\ 2 3
|
|
\ > >
|
|
\ . .
|
|
\ Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D
|
|
AUTOCONFIG/ac_state<1>.D
|
|
AUTOCONFIG/addr_match<0>.CE
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE
|
|
AUTOCONFIG/ide_base<1>.CE
|
|
AUTOCONFIG/ide_base<2>.CE
|
|
AUTOCONFIG/ide_configured.CE
|
|
AUTOCONFIG/ram_configured.CE
|
|
BA<0>.CE
|
|
BA<0>.D 10.0
|
|
BA<1>.CE
|
|
BA<1>.D 10.0
|
|
CAS_n.D
|
|
CKE.CE
|
|
CKE.D
|
|
DQMH.D
|
|
DQML.D 10.0
|
|
IDE/ds_delay<0>.D
|
|
IDE/ds_delay<1>.D
|
|
IDE/ds_delay<2>.D
|
|
IDE/rom_bankSel<0>.D
|
|
IDE/rom_bankSel<1>.D
|
|
IOR_n.D
|
|
IOW_n.CE
|
|
IOW_n.D
|
|
MA<0>.D
|
|
MA<10>.D 11.0
|
|
MA<11>.D 10.0
|
|
MA<1>.D
|
|
MA<2>.D
|
|
MA<3>.D
|
|
MA<4>.D
|
|
MA<5>.D
|
|
MA<6>.D
|
|
MA<7>.D
|
|
MA<8>.D
|
|
MA<9>.D 10.0
|
|
MEMW_n.D
|
|
RAMCS_n.D
|
|
RAS_n.D
|
|
SDRAM/init_refreshed.CE 10.0
|
|
SDRAM/ram_state_FSM_FFd1.D 26.4 26.4
|
|
SDRAM/ram_state_FSM_FFd2.D 27.4 27.4 10.0
|
|
SDRAM/ram_state_FSM_FFd3.D 27.4 27.4 11.0
|
|
SDRAM/ram_state_FSM_FFd4.D 27.4 27.4 11.0
|
|
SDRAM/refresh_request<1>.D
|
|
SDRAM/refreshing.D
|
|
SDRAM/timer_tRFC<0>.D
|
|
SDRAM/timer_tRFC<1>.D
|
|
as_n_sync<1>.D
|
|
autoconf_dtack.D
|
|
autoconfig_dout<0>.CE
|
|
autoconfig_dout<0>.D
|
|
autoconfig_dout<1>.CE
|
|
autoconfig_dout<1>.D
|
|
autoconfig_dout<2>.CE
|
|
autoconfig_dout<2>.D
|
|
autoconfig_dout<3>.CE
|
|
autoconfig_dout<3>.D
|
|
enable_maprom.D
|
|
ide_enabled.D
|
|
idereg_dtack.D
|
|
ideregister_dout<0>.D
|
|
ideregister_dout<1>.D 10.0
|
|
ideregister_dout<2>.D 10.0
|
|
ideregister_dout<3>.D 10.0
|
|
lds_n_sync<1>.D 10.0
|
|
otherram_en.D 10.0
|
|
ovl.CE
|
|
ram_dtack.D 10.0
|
|
ram_ready.CE
|
|
rw_sync<1>.D
|
|
uds_n_sync<1>.D
|
|
z2_state_FSM_FFd1.D 10.0
|
|
z2_state_FSM_FFd2.D 18.7 18.7 10.0
|
|
|
|
--------------------------------------------------------------------------------
|
|
Clock to Setup (tCYC) (nsec)
|
|
(Clock: MEMCLK)
|
|
|
|
\ From r r u u z z
|
|
\ w w d d 2 2
|
|
\ _ _ s s _ _
|
|
\ s s _ _ s s
|
|
\ y y n n t t
|
|
\ n n _ _ a a
|
|
\ c c s s t t
|
|
\ < < y y e e
|
|
\ 0 1 n n _ _
|
|
\ > > c c F F
|
|
\ . . < < S S
|
|
\ Q Q 0 1 M M
|
|
\ > > _ _
|
|
\ . . F F
|
|
\ Q Q F F
|
|
\ d d
|
|
\ 1 2
|
|
\ . .
|
|
\ Q Q
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
\
|
|
To \------------------------------------
|
|
|
|
AUTOCONFIG/ac_state<0>.D 17.7 17.7 17.7
|
|
AUTOCONFIG/ac_state<1>.D 17.7 17.7 17.7
|
|
AUTOCONFIG/addr_match<0>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/addr_match<0>.D
|
|
AUTOCONFIG/addr_match<1>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/addr_match<1>.D
|
|
AUTOCONFIG/addr_match<2>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/addr_match<2>.D
|
|
AUTOCONFIG/addr_match<3>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/addr_match<3>.D
|
|
AUTOCONFIG/ide_base<0>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/ide_base<1>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/ide_base<2>.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/ide_configured.CE 10.0 10.0 10.0
|
|
AUTOCONFIG/ram_configured.CE 10.0 10.0 10.0
|
|
BA<0>.CE
|
|
BA<0>.D
|
|
BA<1>.CE
|
|
BA<1>.D
|
|
CAS_n.D
|
|
CKE.CE
|
|
CKE.D 10.0 10.0
|
|
DQMH.D 11.0
|
|
DQML.D
|
|
IDE/ds_delay<0>.D
|
|
IDE/ds_delay<1>.D
|
|
IDE/ds_delay<2>.D
|
|
IDE/rom_bankSel<0>.D 17.7 17.7
|
|
IDE/rom_bankSel<1>.D 17.7 17.7
|
|
IOR_n.D
|
|
IOW_n.CE
|
|
IOW_n.D
|
|
MA<0>.D
|
|
MA<10>.D
|
|
MA<11>.D
|
|
MA<1>.D
|
|
MA<2>.D
|
|
MA<3>.D
|
|
MA<4>.D
|
|
MA<5>.D
|
|
MA<6>.D
|
|
MA<7>.D
|
|
MA<8>.D
|
|
MA<9>.D
|
|
MEMW_n.D
|
|
RAMCS_n.D
|
|
RAS_n.D
|
|
SDRAM/init_refreshed.CE
|
|
SDRAM/ram_state_FSM_FFd1.D 26.4 18.7 17.7
|
|
SDRAM/ram_state_FSM_FFd2.D 27.4 19.7 18.7
|
|
SDRAM/ram_state_FSM_FFd3.D 27.4 19.7 18.7
|
|
SDRAM/ram_state_FSM_FFd4.D 27.4 19.7 18.7
|
|
SDRAM/refresh_request<1>.D
|
|
SDRAM/refreshing.D
|
|
SDRAM/timer_tRFC<0>.D
|
|
SDRAM/timer_tRFC<1>.D
|
|
as_n_sync<1>.D
|
|
autoconf_dtack.D 10.0 10.0
|
|
autoconfig_dout<0>.CE 10.0 10.0 10.0
|
|
autoconfig_dout<0>.D
|
|
autoconfig_dout<1>.CE 10.0 10.0 10.0
|
|
autoconfig_dout<1>.D
|
|
autoconfig_dout<2>.CE 10.0 10.0 10.0
|
|
autoconfig_dout<2>.D
|
|
autoconfig_dout<3>.CE 10.0 10.0 10.0
|
|
autoconfig_dout<3>.D
|
|
enable_maprom.D 17.7 17.7
|
|
ide_enabled.D
|
|
idereg_dtack.D 10.0 10.0
|
|
ideregister_dout<0>.D 25.4 25.4
|
|
ideregister_dout<1>.D 25.4 25.4
|
|
ideregister_dout<2>.D 25.4 25.4
|
|
ideregister_dout<3>.D 25.4 25.4
|
|
lds_n_sync<1>.D
|
|
otherram_en.D 17.7 17.7
|
|
ovl.CE 10.0
|
|
ram_dtack.D 10.0
|
|
ram_ready.CE
|
|
rw_sync<1>.D 10.0
|
|
uds_n_sync<1>.D 10.0
|
|
z2_state_FSM_FFd1.D 10.0 10.0 10.0
|
|
z2_state_FSM_FFd2.D 18.7 10.0 10.0
|
|
|
|
Path Type Definition:
|
|
|
|
Pad to Pad (tPD) - Reports pad to pad paths that start
|
|
at input pads and end at output pads.
|
|
Paths are not traced through
|
|
registers.
|
|
|
|
Clock Pad to Output Pad (tCO) - Reports paths that start at input
|
|
pads trace through clock inputs of
|
|
registers and end at output pads.
|
|
Paths are not traced through PRE/CLR
|
|
inputs of registers.
|
|
|
|
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
|
|
to clock at pad. Data path starts at
|
|
an input pad and ends at register
|
|
(Fast Input Register for tSUF) D/T
|
|
input. Clock path starts at input pad
|
|
and ends at the register clock input.
|
|
Paths are not traced through
|
|
registers. Pin-to-pin setup
|
|
requirement is not reported or
|
|
guaranteed for product-term clocks
|
|
derived from macrocell feedback
|
|
signals.
|
|
|
|
Clock to Setup (tCYC) - Register to register cycle time.
|
|
Include source register tCO and
|
|
destination register tSU. Note that
|
|
when the computed Maximum Clock Speed
|
|
is limited by tCYC it is computed
|
|
assuming that all registers are
|
|
rising-edge sensitive.
|
|
|